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1. 发明授权

US07667473B1 Flip-chip package having thermal expansion posts 有权
标题翻译：具有热膨胀柱的倒装芯片封装
公开(公告)号：US07667473B1
公开(公告)日：2010-02-23
申请号：US11238419
申请日：2005-09-28
申请人： Robert O. Conn , Steven J. Carey
发明人： Robert O. Conn , Steven J. Carey
IPC分类号： G01R31/02
CPC分类号： H01L23/10 , H01L21/563 , H01L23/3128 , H01L23/3675 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L2224/0554 , H01L2224/05572 , H01L2224/05573 , H01L2224/10175 , H01L2224/13016 , H01L2224/131 , H01L2224/13147 , H01L2224/16057 , H01L2224/16225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81193 , H01L2224/81385 , H01L2224/814 , H01L2224/81447 , H01L2224/81815 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/19041 , H01L2924/014 , H01L2924/01014 , H01L2924/00 , H01L2924/3512 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor package having a substrate and a die includes a plurality of conductive posts attached to the substrate and bonded to an active surface of the die via a plurality of corresponding microbumps. The conductive posts are flexible and extend beyond the top surface of the substrate a sufficient distance to absorb lateral forces exerted upon the microbumps.
摘要翻译：具有基板和模具的半导体封装包括附接到基板的多个导电柱，并且经由多个相应的微凸块结合到模具的有效表面。导电柱是柔性的并且延伸超过基板的顶表面足够的距离以吸收施加在微胶片上的横向力。

2. 发明授权

US06891258B1 Interposer providing low-inductance decoupling capacitance for a packaged integrated circuit 有权
标题翻译：插入器为封装集成电路提供低电感去耦电容
公开(公告)号：US06891258B1
公开(公告)日：2005-05-10
申请号：US10313482
申请日：2002-12-06
申请人： Mark A. Alexander , Robert O. Conn , Steven J. Carey
发明人： Mark A. Alexander , Robert O. Conn , Steven J. Carey
IPC分类号： H01G4/232 , H01G4/35 , H01L23/498 , H05K1/02 , H05K1/14 , H05K1/16 , H01L23/48 , H01L23/34
CPC分类号： H01G4/232 , H01G4/35 , H01L23/49822 , H01L23/49827 , H01L2224/16 , H01L2924/01078 , H01L2924/15311 , H01L2924/19103 , H05K1/0231 , H05K1/141 , H05K1/162 , H05K2201/09309 , H05K2201/10378 , H05K2201/10515 , H05K2201/10734
摘要： Structures that provide decoupling capacitance to packaged IC devices with reduced capacitor and via parasitic inductance. A capacitive interposer structure is physically interposed between the packaged IC and the PCB, thus eliminating the leads and vias that traverse the PCB in known structures. A capacitive interposer is mounted to a PCB and the packaged IC is mounted on the interposer. The interposer has an array of lands on an upper surface, to which the packaged IC is coupled, and an array of terminals on a lower surface, which are coupled to the PCB. Electrically conductive vias interconnect each land with an associated terminal on the opposite surface of the interposer. Within the interposer, layers of a conductive material alternate with layers of a dielectric material, thus forming parallel plate capacitors between adjacent dielectric layers. Each conductive layer is either electrically coupled to, or is electrically isolated from, each via.
摘要翻译：为具有降低电容器和寄生电感的封装IC器件提供去耦电容的结构。电容式内插器结构被物理地置于封装的IC和PCB之间，从而消除了在已知结构中穿过PCB的引线和通孔。电容式插入器安装在PCB上，封装的IC安装在插入器上。插入器具有在上表面上的焊盘的阵列，封装的IC耦合到该焊盘的阵列，以及耦合到PCB的下表面上的端子阵列。导电通孔将每个焊盘与中介层的相对表面上的相关端子互连。在插入器内，导电材料的层与电介质材料的层交替，从而在相邻的电介质层之间形成平行的平板电容器。每个导电层或者电耦合到每个导通电极，或者与每个导通电隔离。

3. 发明授权

US07362121B1 Self-heating mechanism for duplicating microbump failure conditions in FPGAs and for logging failures 有权
标题翻译：用于复制FPGA中的微型计算机故障条件和记录故障的自加热机制
公开(公告)号：US07362121B1
公开(公告)日：2008-04-22
申请号：US10860237
申请日：2004-06-02
申请人： Robert O. Conn , Steven J. Carey , Siuki Chan , William H. Pabst
发明人： Robert O. Conn , Steven J. Carey , Siuki Chan , William H. Pabst
IPC分类号： G01R31/02
CPC分类号： G01R31/2875 , G01R31/287 , G01R31/31905
摘要： A system replicates the rapid temperature increases that are believed to cause microbump failures in certain applications of programmable logic devices (PLDs). The system configures a PLD under test with a circuit that switches a large amount of current and generates a large amount of heat when the circuit is clocked. The system monitors the temperature of the PLD and controls the switching of the circuit to achieve a predetermined temperature within a predetermined time period. The PLD is cooled, and the thermal cycling is repeated. The system detects microbump failures and communicates failure data to a computer for logging and analysis.
摘要翻译：系统复制了在可编程逻辑器件（PLD）的某些应用中被认为导致微型块故障的快速升温。该系统通过切换大量电流的电路来配置待测的PLD，并在电路被计时时产生大量的热量。系统监视PLD的温度并控制电路的切换以在预定时间段内达到预定温度。 PLD被冷却，重复热循环。系统检测微型计算机故障，并将故障数据传送到计算机进行记录和分析。

4. 发明授权

US06961231B1 Interposer providing low-inductance decoupling capacitance for a packaged integrated circuit 有权
公开(公告)号：US06961231B1
公开(公告)日：2005-11-01
申请号：US11074967
申请日：2005-03-08
申请人： Mark A. Alexander , Robert O. Conn , Steven J. Carey
发明人： Mark A. Alexander , Robert O. Conn , Steven J. Carey
IPC分类号： H01G4/232 , H01G4/35 , H01L23/498 , H05K1/02 , H05K1/14 , H05K1/16 , H01G4/06
CPC分类号： H01G4/232 , H01G4/35 , H01L23/49822 , H01L23/49827 , H01L2224/16 , H01L2924/01078 , H01L2924/15311 , H01L2924/19103 , H05K1/0231 , H05K1/141 , H05K1/162 , H05K2201/09309 , H05K2201/10378 , H05K2201/10515 , H05K2201/10734
摘要： Structures that provide decoupling capacitance to packaged IC devices with reduced capacitor and via parasitic inductance. A capacitive interposer structure is physically interposed between the packaged IC and the PCB, thus eliminating the leads and vias that traverse the PCB in known structures. A capacitive interposer is mounted to a PCB and the packaged IC is mounted on the interposer. The interposer has an array of lands on an upper surface, to which the packaged IC is coupled, and an array of terminals on a lower surface, which are coupled to the PCB. Electrically conductive vias interconnect each land with an associated terminal on the opposite surface of the interposer. Within the interposer, layers of a conductive material alternate with layers of a dielectric material, thus forming parallel plate capacitors between adjacent dielectric layers. Each conductive layer is either electrically coupled to, or is electrically isolated from, each via.

5. 发明授权

US08129834B2 Integral metal structure with conductive post portions 有权
标题翻译：具有导电柱部分的整体金属结构
公开(公告)号：US08129834B2
公开(公告)日：2012-03-06
申请号：US12321833
申请日：2009-01-26
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L23/482 , H01L23/49 , H01L23/492 , H01L23/367
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A plurality of FPGA dice is disposed upon a semiconductor substrate. In order to supply the immense power required by the plurality of FPGA dice, power is routed through the semiconductor substrate vertically from thick metal layers and large integral metal structures located on the other side of the semiconductor substrate. Because the semiconductor substrate has a different coefficient of thermal linear expansion than metal layers in contact with the substrate, delamination may occur when the structure is subject to changes in temperature. To prevent delamination of metal layers connected to the semiconductor substrate and in electrical contact with the integral metal structures, the integral metal structures are manufactured with an array of post portions. During changes in temperature, the post portions of the integral metal structures bend and slide relative to metal layers connected to the semiconductor substrate and prevent linear stresses that may otherwise cause delamination.
摘要翻译：多个FPGA管芯设置在半导体衬底上。为了提供多个FPGA芯片所需的巨大功率，功率从位于半导体衬底另一侧的厚金属层和大的整体金属结构垂直地穿过半导体衬底。由于半导体衬底与与衬底接触的金属层具有不同的热线性膨胀系数，所以当结构经受温度变化时，可能发生分层。为了防止与半导体衬底连接并与整体金属结构电接触的金属层的分层，整体金属结构被制成具有一定数量的柱部分。在温度变化期间，整体金属结构的后部相对于连接到半导体衬底的金属层弯曲和滑动，并且防止否则会引起分层的线性应力。

6. 发明申请

US20110239456A1 In system reflow of low temperature eutectic bond balls 失效
标题翻译：在低温共晶粘结球的系统回流中
公开(公告)号：US20110239456A1
公开(公告)日：2011-10-06
申请号：US12798132
申请日：2010-03-30
申请人： Robert O. Conn , Daniel S. Stevenson
发明人： Robert O. Conn , Daniel S. Stevenson
IPC分类号： H05K3/34
CPC分类号： H01L24/81 , H01L23/147 , H01L23/49816 , H01L23/49827 , H01L23/50 , H01L23/5384 , H01L24/13 , H01L24/16 , H01L24/97 , H01L25/0655 , H01L2224/05147 , H01L2224/10135 , H01L2224/10165 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13562 , H01L2224/13655 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/8114 , H01L2224/81141 , H01L2224/81191 , H01L2224/81234 , H01L2224/81815 , H01L2224/97 , H01L2924/01322 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H05K3/3436 , H05K3/3494 , H05K2203/047 , H05K2203/163 , Y02P70/613 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49169 , H01L2924/00 , H01L2924/00014 , H01L2924/00012
摘要： Low temperature bond balls connect two structures having disparate coefficients of linear thermal expansion. An integrated circuit is made to heat the device such that the low temperature bond balls melt. After melting, the bond balls solidify, and the device is operated with the bond balls solidified. In one example, one of the two structures is a semiconductor substrate, and the other structure is a printed circuit board. The integrated circuit is a die mounted to the semiconductor substrate. The bond balls include at least five percent indium, and the integrated circuit is an FPGA loaded with a bit stream. The bit stream configures the FPGA such that the FPGA has increased power dissipation, which melts the balls. After the melting, a second bit stream is loaded into the FPGA and the FPGA is operated in a normal user-mode using the second bit stream.
摘要翻译：低温焊球连接两个具有不同的线性热膨胀系数的结构。制造集成电路以加热该器件，使得低温接合球熔化。熔化后，粘结球固化，并且使粘合球固化的装置进行操作。在一个示例中，两个结构之一是半导体衬底，而另一个结构是印刷电路板。集成电路是安装到半导体衬底的裸片。结合球包括至少5％的铟，并且集成电路是装载有位流的FPGA。位流配置FPGA，使得FPGA具有增加的功率耗散，其熔化了球。熔化后，将第二位流装载到FPGA中，并使用第二位流以正常用户模式操作FPGA。

7. 发明授权

US07709966B2 Large substrate structural vias 有权
标题翻译：大衬底结构通孔
公开(公告)号：US07709966B2
公开(公告)日：2010-05-04
申请号：US11952495
申请日：2007-12-07
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L23/48
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/147 , H01L2924/0002 , H01L2924/14 , H01L2924/1433 , H01L2924/15165 , H01L2924/157 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , Y10T29/49117 , Y10T29/49165 , H01L2924/00
摘要： An electronic package and methods by which the package reduces thermal fatigue failure of conductors in the electronic package. The electronic package includes a carrier substrate having first and second surfaces and a plurality of anchor vias having a via material extending from the first surface toward the second surface. The electronic package includes a first conducting layer having a length and a width extending laterally in two dimensions across a major part of the first surface of the carrier substrate. The anchor vias have plural attachments along the length and the width of the first conducting layer to secure the first conducting layer to the carrier substrate.
摘要翻译：电子封装和封装的方法减少电子封装中导体的热疲劳失效。电子封装包括具有第一和第二表面的载体基板和具有从第一表面向第二表面延伸的通孔材料的多个锚定通孔。电子封装包括第一导电层，第一导电层的长度和宽度横向延伸穿过载体衬底的第一表面的主要部分。锚定通孔沿着第一导电层的长度和宽度具有多个附着物，以将第一导电层固定到载体基底。

8. 发明申请

US20090079058A1 Semiconductor substrate elastomeric stack 有权
标题翻译：半导体衬底弹性体叠层
公开(公告)号：US20090079058A1
公开(公告)日：2009-03-26
申请号：US11975007
申请日：2007-10-16
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L23/538 , H01L21/58
CPC分类号： H05K7/20927 , H01L23/473 , H01L23/481 , H01L24/05 , H01L24/29 , H01L24/32 , H01L25/0652 , H01L2224/0557 , H01L2224/29101 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06589 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/00 , H01L2224/05552
摘要： A reconfigurable high performance computer occupies less than 360 cubic inches and has an approximate compute power of 0.7 teraflops per second while consuming less than 1000 watts. The computer includes a novel stack of semiconductor substrate assemblies. Some semiconductor substrate assemblies involve field programmable gate array (FPGA) dice that are directly surface mounted, as bare die, to a semiconductor substrate. Other semiconductor substrate assemblies of the stack involve bare memory integrated circuit dice that are directly surface mounted to a semiconductor substrate. Elastomeric connectors interconnect adjacent semiconductor substrates proceeding down the stack. Tines of novel comb-shaped power bus bar assembly structures extend into the stack to supply DC supply voltages. The supply voltages are supplied from bus bars, through vias in the semiconductor substrates, and to the integrated circuits on the other side of the substrates. The power bus bars also serve as capacitors and guides for liquid coolant.
摘要翻译：可重新配置的高性能计算机占用小于360立方英寸，并且具有每秒0.7 teraflops的近似计算能力，同时消耗少于1000瓦特。该计算机包括一组新的半导体衬底组件。一些半导体衬底组件涉及作为裸芯片直接表面安装到半导体衬底的现场可编程门阵列（FPGA）裸片。堆叠的其他半导体衬底组件包括直接表面安装到半导体衬底的裸存储器集成电路裸片。弹性连接器将相邻的半导体衬底互相连接，沿堆叠进入。新颖的梳状电源母线组合结构的齿条延伸到堆叠中以提供直流电源电压。电源电压由母线，半导体衬底中的通孔以及衬底另一侧的集成电路提供。电力母线还用作液体冷却剂的电容器和导轨。

9. 发明授权

US07098689B1 Disabling unused/inactive resources in programmable logic devices for static power reduction 有权
公开(公告)号：US07098689B1
公开(公告)日：2006-08-29
申请号：US10666669
申请日：2003-09-19
申请人： Tim Tuan , Kameswara K. Rao , Robert O. Conn
发明人： Tim Tuan , Kameswara K. Rao , Robert O. Conn
IPC分类号： H03K19/094 , H03K19/177 , G05F1/10 , G11C5/14
CPC分类号： H03K19/17784
摘要： A method of operating a programmable logic device, including the steps of enabling resources of the programmable logic device being used in a circuit design implemented by the programmable logic device, and disabling unused or inactive resources of the programmable logic device that are not being used in the circuit design. The step of disabling can include de-coupling the unused or inactive resources from one or more power supply terminals. Alternatively, the step of disabling can include regulating a supply voltage applied to the unused or inactive resources. The step of disabling can be performed in response to configuration data bits stored by the programmable logic device and/or in response to user controlled signals. The step of disabling can be initiated during design time and/or run time of the programmable logic device.

10. 发明授权

US07046071B1 Series capacitor coupling multiplexer for programmable logic devices 失效
标题翻译：用于可编程逻辑器件的串联电容耦合多路复用器
公开(公告)号：US07046071B1
公开(公告)日：2006-05-16
申请号：US10633727
申请日：2003-08-04
申请人： Robert O. Conn , Kameswara K. Rao
发明人： Robert O. Conn , Kameswara K. Rao
IPC分类号： H03K17/62 , H03K17/693
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/1778 , H03K19/17796
摘要： A series capacitor coupling (SCC) structure is controllable to capacitively couple a data input lead of the SCC structure to an output lead of the SCC, or to de-couple the data input lead from the data output lead. An SCC is controlled by a control bit stored in an associated memory cell. A multiplexer is fashioned out of a plurality of such SCC structures such that the edges of a digital signal received on a selected one of a plurality of multiplexer data input leads is coupled through the SCC structures onto an intervening node. The edges of the digital signal on the intervening node are then latched to recreate the incoming digital signal and the latched signal is output onto a multiplexer data output lead. The multiplexer is very fast and has a low leakage current in comparison to conventional transmission gate multiplexers used in programmable logic devices.
摘要翻译：串联电容耦合（SCC）结构是可控制的，以将SCC结构的数据输入引线电容耦合到SCC的输出引线，或者从数据输出引线去耦合数据输入引线。 SCC由存储在关联的存储单元中的控制位控制。从多个这样的SCC结构中形成多路复用器，使得在多个多路复用器数据输入引线中的选定的一个上接收的数字信号的边缘通过SCC结构耦合到中间节点上。然后中断节点上的数字信号的边沿被锁存以重建输入的数字信号，并且锁存的信号被输出到多路复用器数据输出引线上。与可编程逻辑器件中使用的常规传输栅极复用器相比，多路复用器非常快，具有低漏电流。

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