专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20090063061A1 MONITORING DEGRADATION OF CIRCIUT SPEED 审中-公开
标题翻译：监测速度的降低
公开(公告)号：US20090063061A1
公开(公告)日：2009-03-05
申请号：US11847426
申请日：2007-08-30
申请人： RONALD J. BOLAM , Keith A. Jenkins , Kevin G. Stawiasz
发明人： RONALD J. BOLAM , Keith A. Jenkins , Kevin G. Stawiasz
IPC分类号： G01R31/3193
CPC分类号： G01R31/318522 , G01R31/31727
摘要： A circuit, method, and computer readable medium that enables on-chip monitoring of transistor degradation. The circuit includes an on-chip reference ring oscillator electrically coupled to an on-chip reference counter. An on-chip stressed ring oscillator is electrically coupled to an on-chip test counter. A test enable input is electrically coupled with the reference counter, the test counter, and the reference ring oscillator. When the test enable input is asserted the reference ring oscillator places a bit sequence proportional to the reference ring oscillator frequency on the reference counter simultaneously while the stressed ring oscillator places bit sequence proportional to the stressed ring oscillator frequency on the test counter. A difference in bit sequence between the reference counter and the test counter is compared to determine a relative difference there between.
摘要翻译：一种电路，方法和计算机可读介质，可实现晶体管降级的片上监控。电路包括电耦合到芯片上参考计数器的片上参考环形振荡器。片上应力环形振荡器电耦合到片上测试计数器。测试使能输入与参考计数器，测试计数器和参考环形振荡器电耦合。当测试使能输入被置位时，参考环形振荡器将与参考环形振荡器频率成比例的比特序列同时放置在参考计数器上，同时应力环形振荡器将比特序列与测试计数器上的应力环形振荡器频率成比例。比较参考计数器和测试计数器之间的位序列的差异，以确定其间的相对差异。

22. 发明申请

US20080284477A1 ON-CHIP JITTER MEASUREMENT CIRCUIT 失效
标题翻译：片上抖动测量电路
公开(公告)号：US20080284477A1
公开(公告)日：2008-11-20
申请号：US12125730
申请日：2008-05-22
申请人： David F. Heidel , Keith A. Jenkins
发明人： David F. Heidel , Keith A. Jenkins
IPC分类号： H03L7/24
CPC分类号： H04L1/205 , G01R29/26 , G01R31/3016 , G01R31/31709 , G01R31/31725
摘要： An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, including a latch for comparing the arrival time of the signal of interest to the reference clock, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, a middle stage, and a last stage, a voltage controller in signal communication with the middle stage of the delay chain for controlling the delay of the arrival time of the reference clock while permitting the first and last stages of the delay chain to retain a full voltage swing independent of the delay.
摘要翻译：提供片上抖动测量电路和相应的方法，用于接收参考时钟和感兴趣的信号，包括用于比较感兴趣信号的到达时间与参考时钟的锁存器，与参考时钟信号通信的延迟链用于改变参考时钟的到达时间的时钟，具有第一级，中级和最后级的延迟链，与延迟链的中间级信号通信的电压控制器，用于控制到达时间的延迟的参考时钟，同时允许延迟链的第一级和最后级保持独立于延迟的全电压摆幅。

23. 发明授权

US07439755B2 Electronic circuit for measurement of transistor variability and the like 有权
标题翻译：用于测量晶体管变化性的电子电路等
公开(公告)号：US07439755B2
公开(公告)日：2008-10-21
申请号：US11669250
申请日：2007-01-31
申请人： Keith A. Jenkins , Jae-Joon Kim , Rahul M. Rao
发明人： Keith A. Jenkins , Jae-Joon Kim , Rahul M. Rao
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided.
摘要翻译：电子电路包括输出端子和至少第一测量FET。待测试的多个FET的第二漏极 - 源极端子与第一测量FET和输出端子的第一漏极 - 源极端子互连。第一测量FET的第二漏极 - 源极端子与第一偏置端子互连。要测试的FETS的第一漏极 - 源极端子与第二偏置端子互连。状态机耦合到要测试的FETs的栅极和第一测量FET的栅极。状态机被配置为对第一测量FET的栅极通电并且顺序地激励要测试的FETS的栅极，使得输出电压出现在输出端子上。还提供了将输出电压与参考值进行比较的电路。

24. 发明授权

US07378831B1 System and method for determining a delay time interval of components 有权
标题翻译：用于确定组件的延迟时间间隔的系统和方法
公开(公告)号：US07378831B1
公开(公告)日：2008-05-27
申请号：US11624392
申请日：2007-01-18
申请人： Keith A. Jenkins , Seongwon Kim
发明人： Keith A. Jenkins , Seongwon Kim
IPC分类号： G01R19/00 , G01R29/02 , H03H11/26
CPC分类号： G01R31/3016
摘要： A system and a method for determining a delay time interval of components are provided. The system includes a delay chain of components having a plurality of components wherein each component of the delay chain of components has a first delay time interval. The system utilizes a reference clock signal to stimulate the delay change of components and monitors a delay clock signal output by the delay chain of components to determine a delay time interval associated with each component in the delay chain of components.
摘要翻译：提供了一种用于确定组件的延迟时间间隔的系统和方法。该系统包括具有多个部件的部件的延迟链，其中部件的延迟链的每个部件具有第一延迟时间间隔。该系统利用参考时钟信号来刺激部件的延迟变化并且监视由部件的延迟链输出的延迟时钟信号，以确定与部件的延迟链中的每个部件相关联的延迟时间间隔。

25. 发明申请

US20080055036A1 Electrical component tuned by conductive layer deletion 失效
标题翻译：通过导电层删除调整的电气元件
公开(公告)号：US20080055036A1
公开(公告)日：2008-03-06
申请号：US11512014
申请日：2006-08-29
申请人： Keith A. Jenkins , Mounir Meghelli
发明人： Keith A. Jenkins , Mounir Meghelli
IPC分类号： H01F5/00
CPC分类号： H01F17/0013 , H01F21/12 , H01F41/045 , H01F2021/125 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H05K1/165 , H01L2924/00
摘要： Techniques are disclosed for fabricating tunable electrical components in integrated circuits. For example, a method of tuning a value of an electrical component, such as a planar inductor, includes the steps of placing a conductive layer in proximity of the electrical component, and adjusting an amount of material that constitutes the conductive layer such that the value of the electrical component is tuned to a particular value. The adjustment step may be performed so as to select a frequency band with which the inductor is associated or to correct a manufacturing deviation in a frequency with which the inductor is associated.
摘要翻译：公开了用于在集成电路中制造可调电气部件的技术。例如，调整诸如平面电感器的电气部件的值的方法包括以下步骤：将导电层放置在电气部件附近，以及调整构成导电层的材料的量，使得值的电气元件被调谐到特定的值。可以执行调整步骤以便选择与电感器相关联的频带或者校正与电感器相关联的频率中的制造偏差。

26. 发明授权

US09276524B2 High frequency oscillator circuit 有权
标题翻译：高频振荡电路
公开(公告)号：US09276524B2
公开(公告)日：2016-03-01
申请号：US13569815
申请日：2012-08-08
申请人： Keith A. Jenkins , Yu-ming Lin
发明人： Keith A. Jenkins , Yu-ming Lin
IPC分类号： H03B7/06 , H03B5/12 , H01L29/16 , H01L29/786
CPC分类号： H03B5/1228 , H01L29/1606 , H01L29/78684 , H03B5/1203 , H03B7/06 , H03B2200/0084
摘要： An oscillator circuit includes a field effect transistor and a resonant circuit having a first terminal connected to the field effect transistor. The resonant circuit includes an inductance and a capacitance and has a second terminal for connecting to a radiator. The field effect transistor includes a gate electrode coupled to a source of gate voltage, a source electrode, a drain electrode and a graphene channel disposed between the source electrode and the drain electrode and electrically connected thereto. The graphene channel is disposed relative to the gate electrode for being biased by the gate electrode into a negative differential resistance region of operation. The oscillator circuit is capable of generating a continuous wave THz frequency signal, and is further capable of being enabled and disabled by the bias applied to the gate electrode.
摘要翻译：振荡器电路包括场效应晶体管和具有连接到场效应晶体管的第一端子的谐振电路。谐振电路包括电感和电容，并且具有用于连接到散热器的第二端子。场效应晶体管包括耦合到栅极电压源的栅电极，源电极，漏电极和设置在源电极和漏电极之间并与其电连接的石墨烯通道。石墨烯通道相对于栅电极设置，以便被栅电极偏压成负的差分电阻区域。振荡器电路能够产生连续波THz频率信号，并且还能够通过施加到栅电极的偏置而被使能和禁止。

27. 发明授权

US08987693B2 High density memory device 有权
标题翻译：高密度存储器件
公开(公告)号：US08987693B2
公开(公告)日：2015-03-24
申请号：US13570390
申请日：2012-08-09
申请人： Tymon Barwicz , Keith A. Jenkins , Supratik Guha
发明人： Tymon Barwicz , Keith A. Jenkins , Supratik Guha
IPC分类号： H01L47/00 , G11C11/404 , H01L49/02 , G11C13/00 , H01L49/00
CPC分类号： G11C11/404 , G11C13/0007 , H01L28/40 , H01L49/003
摘要： A method of operating a memory device having a dielectric material layer, a transition metal oxide layer and a set of electrodes each formed over a substrate, includes applying a voltage across the set of electrodes producing an electric field across the transition metal oxide layer enabling the transition metal oxide layer to undergo a metal-insulation transition (MIT) to perform a read or write operation on memory device.
摘要翻译：一种操作具有介电材料层，过渡金属氧化物层和一组电极的存储器件的方法，每个形成在衬底上，包括在整个电极组上施加电压，从而在过渡金属氧化物层上产生电场，从而能够过渡金属氧化物层进行金属绝缘转变（MIT）以对存储器件执行读或写操作。

28. 发明授权

US08729920B2 Circuit and method for RAS-enabled and self-regulated frequency and delay sensor 有权
标题翻译： RAS使能和自调节频率和延迟传感器的电路和方法
公开(公告)号：US08729920B2
公开(公告)日：2014-05-20
申请号：US12953828
申请日：2010-11-24
申请人： Carole D. Graas , Keith A. Jenkins , Pascal A. Nsame , Kevin G. Stawiasz
发明人： Carole D. Graas , Keith A. Jenkins , Pascal A. Nsame , Kevin G. Stawiasz
IPC分类号： G01R31/26
CPC分类号： G11C29/50 , G01R31/2882 , G11C16/349 , G11C2029/5002
摘要： Circuits and methods are provided for a reliability, availability and serviceability (RAS) enabled and self-regulated frequency and delay sensor of a semiconductor. A circuit for measuring and compensating for time-dependent performance degradation of an integrated circuit, includes at least one critical functional path of the integrated circuit, and Wearout Isolation Registers (WIR's) connected to boundaries of the critical functional path. The circuit also includes a feedback path connected to the WIR's, and a sensor control module operable to disconnect the critical functional path from preceding and succeeding functional paths of the integrated circuit, connect the critical functional path to the feedback path to form a critical path ring oscillator (CPRO), and enable the CPRO to generate an operating signal. A delay sensor module is operable to measure a frequency of the operating signal to determine and compensate for a degradation of application performance over a lifetime of a semiconductor product.
摘要翻译：为可靠性，可用性和可服务性（RAS）使能和半自动调节频率和延迟传感器提供了电路和方法。用于测量和补偿集成电路的时间依赖性能劣化的电路包括集成电路的至少一个关键功能路径和连接到关键功能路径边界的扰动隔离寄存器（WIR）。电路还包括连接到WIR的反馈路径，以及传感器控制模块，其可操作以将关键功能路径与集成电路的先前和后续功能路径断开连接，将关键功能路径连接到反馈路径以形成关键路径环振荡器（CPRO），并使CPRO产生操作信号。延迟传感器模块可操作以测量操作信号的频率，以确定并补偿半导体产品的寿命期间的应用性能的劣化。

29. 发明申请

US20140022025A1 HIGH FREQUENCY OSCILLATOR CIRCUIT AND METHOD TO OPERATE SAME 有权
标题翻译：高频振荡器电路及其操作方法
公开(公告)号：US20140022025A1
公开(公告)日：2014-01-23
申请号：US13551708
申请日：2012-07-18
申请人： Keith A. Jenkins , Yu-ming Lin
发明人： Keith A. Jenkins , Yu-ming Lin
IPC分类号： H03B5/30
CPC分类号： H03B7/06 , H03B2200/0084
摘要： A method includes providing an oscillator having a field effect transistor connected with a resonant circuit. The field effect transistor has a gate electrode coupled to a source of gate voltage, a source electrode, a drain electrode and a graphene channel disposed between the source electrode and the drain electrode and electrically connected thereto. The method further includes biasing the graphene channel via the gate electrode into a negative differential resistance region of operation to cause the oscillator to generate a frequency signal having a resonant frequency f0. There can be an additional step of varying the gate voltage so as to bias the graphene channel into the negative differential resistance region of operation and out of the negative differential resistance region of operation so as to turn on the frequency signal and to turn off the frequency signal, respectively.
摘要翻译：一种方法包括提供具有与谐振电路连接的场效应晶体管的振荡器。场效应晶体管具有耦合到栅极电压源的栅电极，源电极，漏电极和设置在源电极和漏电极之间并与其电连接的石墨烯通道。该方法还包括经由栅电极将石墨烯通道偏压成负的差分电阻区域，以使振荡器产生具有谐振频率f0的频率信号。可以存在改变栅极电压以便将石墨烯通道偏压到负的差分电阻区域和负的差分电阻区域的附加步骤，以便接通频率信号并且关闭频率信号。

30. 发明授权

US07863918B2 Disposable built-in self-test devices, systems and methods for testing three dimensional integrated circuits 有权
标题翻译：一次性内置自检装置，三维集成电路测试系统和方法
公开(公告)号：US07863918B2
公开(公告)日：2011-01-04
申请号：US11939145
申请日：2007-11-13
申请人： Keith A. Jenkins , Seongwon Kim
发明人： Keith A. Jenkins , Seongwon Kim
IPC分类号： G01R31/02
CPC分类号： G01R31/2884 , H01L22/20 , H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： A device and method for self-testing an integrated circuit layer for a three-dimensional integrated circuit includes integrally forming a disposable self-test circuit on a common substrate with a first circuit to be tested. The first circuit forms a layer in a three-dimensional integrated circuit structure. The first circuit is tested using circuitry of the self-test circuit. The self-test circuit is removed by detaching the self-test circuit from the first circuit.
摘要翻译：用于对三维集成电路的集成电路层进行自检的装置和方法包括在具有待测试的第一电路的共同衬底上一体地形成一次性自检电路。第一电路形成三维集成电路结构的层。第一个电路使用自检电路的电路进行测试。通过从第一电路分离自检电路来去除自检电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式