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21. 发明申请

US20060180868A1 STRUCTURE AND METHOD FOR IMPROVED DIODE IDEALITY 有权
标题翻译：改善二极管理想的结构和方法
公开(公告)号：US20060180868A1
公开(公告)日：2006-08-17
申请号：US10906366
申请日：2005-02-16
申请人： Edward Maciejewski , Sherry Womack , Shreesh Narasimha , Christopher Sheraw
发明人： Edward Maciejewski , Sherry Womack , Shreesh Narasimha , Christopher Sheraw
IPC分类号： H01L23/62
CPC分类号： H01L27/0629 , H01L27/0814 , H01L29/66136 , H01L29/861
摘要： A device is provided which includes a single-crystal semiconductor region disposed in a substrate. The single-crystal region includes a first semiconductor material and a diode disposed in the single-crystal region. The diode includes an anode region including a first alloy region, being an alloy of the first semiconductor material with a second semiconductor material, and a second region which consists essentially of the first semiconductor material, the diode further including a cathode region.
摘要翻译：提供一种器件，其包括设置在衬底中的单晶半导体区域。单晶区域包括设置在单晶区域中的第一半导体材料和二极管。该二极管包括一个阳极区域，该阳极区域包括第一合金区域，该第一合金区域是第一半导体材料与第二半导体材料的合金，以及第二区域，该第二区域基本上由第一半导体材料组成，二极管还包括阴极区域。

22. 发明申请

US20060128145A1 DEVICE HAVING DUAL ETCH STOP LINER AND REFORMED SILICIDE LAYER AND RELATED METHODS 有权
标题翻译：具有双层蚀刻层和改性硅酸盐层的装置及相关方法
公开(公告)号：US20060128145A1
公开(公告)日：2006-06-15
申请号：US10905027
申请日：2004-12-10
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
IPC分类号： H01L21/44 , H01L21/8238
CPC分类号： H01L29/7842 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823864 , H01L29/7843
摘要： The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed silicide layer has a thickness and resistance substantially similar to a silicide layer not exposed to the formation of the dual silicon nitride liners. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to a silicide layer, removing a portion of the first silicon nitride liner, reforming a portion of the silicide layer removed during the removal step, and applying a second silicon nitride liner to the silicide layer.
摘要翻译：本发明提供一种具有双重氮化硅衬垫和重整硅化物层的半导体器件以及用于制造这种器件的相关方法。重整的硅化物层的厚度和电阻基本上类似于未暴露于形成双重氮化硅衬里的硅化物层。本发明的第一方面提供一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到硅化物层，去除第一氮化硅衬垫的一部分，重整硅化物层的一部分在去除步骤期间去除，并且将第二氮化硅衬垫施加到硅化物层。

23. 发明申请

US20060040497A1 Material for contact etch layer to enhance device performance 审中-公开
标题翻译：用于接触蚀刻层的材料以增强器件性能
公开(公告)号：US20060040497A1
公开(公告)日：2006-02-23
申请号：US11253622
申请日：2005-10-20
申请人： Ashima Chakravarti , Shreesh Narasimha , Victor Chan , Judson Holt , Satya Chakravarti
发明人： Ashima Chakravarti , Shreesh Narasimha , Victor Chan , Judson Holt , Satya Chakravarti
IPC分类号： H01L21/44
CPC分类号： H01L21/0217 , C23C16/345 , H01L21/02271 , H01L21/02274 , H01L21/3185 , H01L29/7843
摘要： Stress level of a nitride film is adjusted as a function of two or more of the following: identity of a starting material precursor used to make the nitride film; identity of a nitrogen-containing precursor with which is treated the starting material precursor; ratio of the starting material precursor to the nitrogen-containing precursor; a set of CVD conditions under which the film is grown; and/or a thickness to which the film is grown. A rapid thermal chemical vapor deposition (RTCVD) film produced by reacting a compound containing silicon, nitrogen and carbon (such as bis-tertiary butyl amino silane (BTBAS)) with NH3 can provide advantageous properties, such as high stress and excellent performance in an etch-stop application. An ammonia-treated BTBAS film is particularly excellent in providing a high-stress property, and further having maintainability of that high-stress property over repeated annealing.
摘要翻译：氮化膜的应力水平作为以下两个或更多个的函数来调节：用于制造氮化物膜的原料前体的同一性; 同时处理起始原料前体的含氮前体; 原料前体与含氮前体的比例; 电影种植的一系列CVD条件; 和/或薄膜生长的厚度。通过使含有硅，氮和碳（例如双叔丁基氨基硅烷（BTBAS））的化合物与NH 3 N 3反应制备的快速热化学气相沉积（RTCVD）膜可以提供有利的性质，例如在蚀刻停止应用中作为高应力和优异的性能。氨处理的BTBAS膜在提供高应力性能方面特别优异，并且在反复退火时还具有高应力性能的可维护性。

24. 发明申请

US20050245081A1 Material for contact etch layer to enhance device performance 失效
标题翻译：用于接触蚀刻层的材料以增强器件性能
公开(公告)号：US20050245081A1
公开(公告)日：2005-11-03
申请号：US10835949
申请日：2004-04-30
申请人： Ashima Chakravarti , Shreesh Narasimha , Victor Chan , Judson Holt , Satya Chakravarti
发明人： Ashima Chakravarti , Shreesh Narasimha , Victor Chan , Judson Holt , Satya Chakravarti
IPC分类号： H01L21/768 , C23C16/34 , H01L21/318 , H01L21/469 , H01L29/78
CPC分类号： H01L21/0217 , C23C16/345 , H01L21/02271 , H01L21/02274 , H01L21/3185 , H01L29/7843
摘要： Stress level of a nitride film is adjusted as a function of two or more of the following: identity of a starting material precursor used to make the nitride film; identity of a nitrogen-containing precursor with which is treated the starting material precursor; ratio of the starting material precursor to the nitrogen-containing precursor; a set of CVD conditions under which the film is grown; and/or a thickness to which the film is grown. A rapid thermal chemical vapor deposition (RTCVD) film produced by reacting a compound containing silicon, nitrogen and carbon (such as bis-tertiary butyl amino silane (BTBAS)) with NH3 can provide advantageous properties, such as high stress and excellent performance in an etch-stop application. An ammonia-treated BTBAS film is particularly excellent in providing a high-stress property, and further having maintainability of that high-stress property over repeated annealing.
摘要翻译：氮化膜的应力水平作为以下两个或更多个的函数来调节：用于制造氮化物膜的原料前体的同一性; 同时处理起始原料前体的含氮前体; 原料前体与含氮前体的比例; 电影种植的一系列CVD条件; 和/或薄膜生长的厚度。通过使含有硅，氮和碳（例如双叔丁基氨基硅烷（BTBAS））的化合物与NH 3 N 3反应制备的快速热化学气相沉积（RTCVD）膜可以提供有利的性质，例如在蚀刻停止应用中作为高应力和优异的性能。氨处理的BTBAS膜在提供高应力性能方面特别优异，并且在反复退火时还具有高应力性能的可维护性。

25. 发明授权

US08779551B2 Gated diode structure for eliminating RIE damage from cap removal 失效
标题翻译：门二极管结构，用于消除去除盖子的RIE损坏
公开(公告)号：US08779551B2
公开(公告)日：2014-07-15
申请号：US13489537
申请日：2012-06-06
申请人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
发明人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
IPC分类号： H01L27/06
CPC分类号： H01L21/8238 , H01L21/265 , H01L21/77 , H01L21/823835 , H01L27/0629 , H01L27/1203 , H01L29/42364 , H01L29/7391 , H01L29/861
摘要： A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.
摘要翻译：一种半导体结构，其具有多个具有硅化阳极（p掺杂区域）和阴极（n掺杂区域）的门控二极管和由非硅化栅极材料制成的高K栅极堆叠，该门控二极管相邻其中每一个具有硅化源，硅化物漏极和硅化HiK栅极叠层。半导体结构消除了栅极第一高K金属栅极流从栅极二极管的区域流出的帽去除RIE。优选在栅极第一工艺流程期间，在二极管的栅极上缺少硅化物和存在氮化物阻挡层。没有帽去除RIE是有益的，因为二极管的扩散不经受帽去除RIE，这避免了损伤并且允许保持其高度理想的结特性。

26. 发明授权

US08729637B2 Work function adjustment by carbon implant in semiconductor devices including gate structure 有权
标题翻译：通过碳植入在包括栅极结构的半导体器件中进行功能调整
公开(公告)号：US08729637B2
公开(公告)日：2014-05-20
申请号：US13253268
申请日：2011-10-05
申请人： Yue Liang , Dechao Guo , William K. Henson , Shreesh Narasimha , Yanfeng Wang
发明人： Yue Liang , Dechao Guo , William K. Henson , Shreesh Narasimha , Yanfeng Wang
IPC分类号： H01L21/70 , H01L21/20 , H01L21/00
CPC分类号： H01L27/092 , H01L21/26506 , H01L21/28088 , H01L21/28176 , H01L21/28194 , H01L21/823857 , H01L29/1054 , H01L29/517
摘要： A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.
摘要翻译：一种在半导体衬底上包括p型半导体器件和n型半导体器件的器件。 n型半导体器件包括具有高k栅极电介质的栅极结构。在n型半导体器件的栅极结构的高k栅极电介质和半导体衬底之间的界面处存在浓度范围为1×1016原子/ cm3至1×1021原子/ cm3的碳掺杂剂。还公开了形成上述装置的方法。

27. 发明授权

US08536563B2 Nanowire field effect transistors 有权
标题翻译：纳米线场效应晶体管
公开(公告)号：US08536563B2
公开(公告)日：2013-09-17
申请号：US12884707
申请日：2010-09-17
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L29/06
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/84 , H01L29/0673 , H01L29/42392 , H01L29/4966 , H01L29/513 , H01L29/66439 , H01L29/78696
摘要： A method for forming a nanowire field effect transistor (FET) device including forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a substrate, patterning a first hardmask layer over the second SOI portion, forming a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer, forming a second suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire, and removing the second hardmask layer.
摘要翻译：一种用于形成纳米线场效应晶体管（FET）器件的方法，包括形成绝缘体上硅（SOI）焊盘区域，第二SOI焊盘区域，第三SOI焊盘区域，将第一SOI焊盘区域连接到第一SOI焊盘区域的第一SOI部分第二SOI焊盘区域和将第二SOI焊盘区域连接到衬底上的第三SOI焊盘区域的第二SOI部分，在第二SOI部分上形成第一硬掩模层，在半导体衬底上形成第一悬浮的纳米线，形成第一围绕第一悬浮纳米线的一部分构造栅极结构，在第一栅极结构和第一悬置纳米线上图案化第二硬掩模层，去除第一硬掩模层，在半导体衬底上形成第二悬浮纳米线，在第二栅极结构周围形成第二栅极结构第二悬浮纳米线的一部分，以及去除第二硬掩模层。

28. 发明授权

US08490029B2 Method of fabricating a device using low temperature anneal processes, a device and design structure 有权
标题翻译：使用低温退火工艺制造器件的方法，器件和设计结构
公开(公告)号：US08490029B2
公开(公告)日：2013-07-16
申请号：US13421400
申请日：2012-03-15
申请人： Anthony G. Domenicucci , Terence L. Kane , Shreesh Narasimha , Karen A. Nummy , Viorel Ontalus , Yun-Yu Wang
发明人： Anthony G. Domenicucci , Terence L. Kane , Shreesh Narasimha , Karen A. Nummy , Viorel Ontalus , Yun-Yu Wang
IPC分类号： G06F17/50
CPC分类号： H01L21/324 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7847
摘要： A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.
摘要翻译：提供了使用退火处理序列制造器件的方法。更具体地，示出并描述了使用低温退火制造以消除位错缺陷的逻辑NFET器件，制造NFET器件的方法和设计结构。该方法包括在栅极结构上形成应力衬垫，并对栅极结构和应力衬垫进行低温退火处理，以在栅极结构附近的单晶硅中形成堆叠力，作为记忆应力的方法。该方法还包括从栅极结构剥离应力衬垫并在器件上在高温下进行激活退火。

29. 发明申请

US20130105896A1 Threshold Voltage Adjustment For Thin Body Mosfets 审中-公开
标题翻译：薄体硅片的阈值电压调整
公开(公告)号：US20130105896A1
公开(公告)日：2013-05-02
申请号：US13625350
申请日：2012-09-24
申请人： MaryJane Brodsky , Ming Cai , Dechao Guo , William K. Henson , Shreesh Narasimha , Yue Liang , Liyang Song , Yanfeng Wang , Chun-Chen Yeh
发明人： MaryJane Brodsky , Ming Cai , Dechao Guo , William K. Henson , Shreesh Narasimha , Yue Liang , Liyang Song , Yanfeng Wang , Chun-Chen Yeh
IPC分类号： H01L27/12
CPC分类号： H01L29/66803
摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor.
摘要翻译：一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。

30. 发明授权

US08236709B2 Method of fabricating a device using low temperature anneal processes, a device and design structure 有权
标题翻译：使用低温退火工艺制造器件的方法，器件和设计结构
公开(公告)号：US08236709B2
公开(公告)日：2012-08-07
申请号：US12511535
申请日：2009-07-29
申请人： Anthony G. Domenicucci , Terence L. Kane , Shreesh Narasimha , Karen A. Nummy , Viorel Ontalus , Yun-Yu Wang
发明人： Anthony G. Domenicucci , Terence L. Kane , Shreesh Narasimha , Karen A. Nummy , Viorel Ontalus , Yun-Yu Wang
IPC分类号： H01L21/322 , H01L21/324
CPC分类号： H01L21/324 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7847
摘要： A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.
摘要翻译：提供了使用退火处理序列制造器件的方法。更具体地，示出并描述了使用低温退火制造以消除位错缺陷的逻辑NFET器件，制造NFET器件的方法和设计结构。该方法包括在栅极结构上形成应力衬垫，并对栅极结构和应力衬垫进行低温退火处理，以在栅极结构附近的单晶硅中形成堆叠力，作为记忆应力的方法。该方法还包括从栅极结构剥离应力衬垫并在器件上在高温下进行激活退火。

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