专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06337833B1 Memory device 有权
标题翻译：内存设备
公开(公告)号：US06337833B1
公开(公告)日：2002-01-08
申请号：US09346919
申请日：1999-07-02
申请人： Kazuyuki Kanazashi , Toshiya Uchida , Masaki Okuda
发明人： Kazuyuki Kanazashi , Toshiya Uchida , Masaki Okuda
IPC分类号： G11C800
CPC分类号： G11C7/225 , G11C7/1051 , G11C7/1072
摘要： One aspect of the present invention is that, when the memory is in the non-power-down state, the supply of clock signals to the data output circuit is limited to the read status after the reception of a read command, and no clock signal supply is performed when either the active status or the write status is in effect. In the best aspect, furthermore, in the read status after the reception of a read command, the supply of clock signals to the data output circuit starts after a number of clock signals corresponding to a set CAS latency following the read command, and stops after a number of clock signals corresponding to a set burst length, after the output of the read out data from the data output circuit starts. Accordingly, even in the non-power-down state, clock signals are only supplied during the time required for the read out data to be actually output from the data output circuit to the outside, whereby it is possible to reduce the number of clock signal supply actions that require large current drive.
摘要翻译：本发明的一个方面是，当存储器处于非掉电状态时，向数据输出电路提供时钟信号被限制在接收到读命令之后的读状态，并且没有时钟信号当活动状态或写入状态都有效时执行供电。此外，在最佳方面，在接收到读取命令之后的读取状态下，在与读取命令之后的设定的CAS延迟相对应的多个时钟信号之后，向数据输出电路提供时钟信号开始，并且在后面停止在从数据输出电路输出读出数据开始之后，与设定的突发长度对应的多个时钟信号。因此，即使在非掉电状态下，时钟信号仅在从数据输出电路向外部输出的读出数据所需的时间内提供，从而可以减少时钟信号的数量提供需要大电流驱动的动作。

22. 发明授权

US07650536B2 Forced termination condition monitoring device, forced termination condition monitoring method and storage medium embodying forced termination condition monitoring program 失效
标题翻译：强制终止条件监测装置，强制终止条件监测方法和体现强制终止条件监测程序的存储介质
公开(公告)号：US07650536B2
公开(公告)日：2010-01-19
申请号：US11448055
申请日：2006-06-07
申请人： Kouitirou Takahasi , Masaki Okuda
发明人： Kouitirou Takahasi , Masaki Okuda
IPC分类号： G06F11/00
CPC分类号： G06F11/004 , G06F11/0748 , G06F11/0793
摘要： To terminate startup of an application on an ASP side irrespective of checking on a user side whether or not the application is in the middle of processing. A monitoring device includes means monitoring an operating status of an information processing device for providing a service by starting up an information processing program to a user terminal specified by user identifying information, means judging whether or not the operating status of the information processing device meets a predetermined condition, means terminating the startup of the information processing program if the operating status meets the predetermined condition, and means notifying the user terminal of the termination of the startup of the information processing program.
摘要翻译：无论用户方检查应用程序是否在处理中，都要终止ASP侧应用程序的启动。监视装置包括监视信息处理装置的操作状态的装置，用于通过向由用户识别信息指定的用户终端启动信息处理程序来提供服务，判断信息处理装置的操作状态是否满足如果操作状态满足预定条件，则意味着终止信息处理程序的启动，并且意味着通知用户终端信息处理程序的启动的终止。

23. 发明授权

US07649796B2 Semiconductor memory and operating method of same 有权
标题翻译：半导体存储器及其操作方法相同
公开(公告)号：US07649796B2
公开(公告)日：2010-01-19
申请号：US12005389
申请日：2007-12-27
申请人： Masaki Okuda , Atsushi Fujii
发明人： Masaki Okuda , Atsushi Fujii
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/401 , G11C11/406 , G11C29/14 , G11C29/50012 , G11C2211/4061
摘要： A semiconductor memory has a memory cell array having dynamic memory cells. An access control circuit accesses the memory cells in response to an access command which is supplied externally. A refresh control circuit generates, during a test mode, a test refresh request signal in synchronization with the access command so as to execute a refresh operation of the memory cells when a refresh mask signal is at an invalid level. Also, the refresh control circuit prohibits generation of the test refresh request signal when the refresh mask signal is at a valid level. The test refresh request signal is generated or prohibited from being generated according to the level of the refresh mask signal. Thus, only a refresh operation needed for a test can be executed, and hence test efficiency can be improved.
摘要翻译：半导体存储器具有具有动态存储单元的存储单元阵列。访问控制电路响应于外部提供的访问命令来访问存储器单元。刷新控制电路在测试模式期间与访问命令同步地生成测试刷新请求信号，以便当刷新屏蔽信号处于无效级时执行存储器单元的刷新操作。此外，当刷新屏蔽信号处于有效电平时，刷新控制电路禁止产生测试刷新请求信号。生成或禁止根据刷新屏蔽信号的电平生成测试刷新请求信号。因此，可以仅执行测试所需的刷新操作，因此可以提高测试效率。

24. 发明授权

US07190204B2 Logical circuit 有权
标题翻译：逻辑电路
公开(公告)号：US07190204B2
公开(公告)日：2007-03-13
申请号：US11042335
申请日：2005-01-26
申请人： Hiroyuki Kobayashi , Masaki Okuda
发明人： Hiroyuki Kobayashi , Masaki Okuda
IPC分类号： H03H11/16
CPC分类号： H03K5/1515 , H03K5/26 , H03K19/00323 , H03K19/21 , H03L7/0812 , H03L7/089
摘要： A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected. A second unit changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.
摘要翻译：逻辑电路接收第一和第二输入信号，其中第一逻辑电平的周期部分地重叠，并输出其中第一逻辑电平的周期不重叠的第一和第二输出信号。逻辑电路包括第一单元，当从第二逻辑电平到第一逻辑电平的第一输入信号的改变被检测到时，将第一输出信号的相位从第二逻辑电平改变到第一逻辑电平。当检测到第一输入信号的变化时，第二输入信号被检测为处于第一逻辑电平时，第二单元将第二输出信号的相位从第一逻辑电平改变为第二逻辑电平。

25. 发明申请

US20060044038A1 Semiconductor device 有权
公开(公告)号：US20060044038A1
公开(公告)日：2006-03-02
申请号：US11020169
申请日：2004-12-27
申请人： Masaki Okuda
发明人： Masaki Okuda
IPC分类号： G06F1/04
CPC分类号： G06F1/26 , H01L2924/0002 , H01L2924/00
摘要： In order to prevent a signal of a signal wiring from receiving a bad influence due to a power supply capacitor, provided is a semiconductor including a high reference potential terminal and a low reference potential terminal composing power supply voltage terminals; a first MOS capacitor in which a gate of a p-channel MOS field effect transistor is connected to the low reference potential terminal, and a source and a drain are connected to the high reference potential terminal; and a first signal wiring connected to the gate via a parasitic capacitor and a signal in the low reference potential is supplied at the time of starting the power supply.

26. 发明申请

US20050289070A1 Server providing computer resources to user terminals 审中-公开
标题翻译：向用户终端提供计算机资源的服务器
公开(公告)号：US20050289070A1
公开(公告)日：2005-12-29
申请号：US10940813
申请日：2004-09-15
申请人： Kouitirou Takahasi , Masaki Okuda , Shinya Shibata , Yoshiaki Watanabe
发明人： Kouitirou Takahasi , Masaki Okuda , Shinya Shibata , Yoshiaki Watanabe
IPC分类号： G06Q30/04 , G06F15/00 , G06Q30/06 , G06Q50/00 , G06Q50/10 , H02J7/00
CPC分类号： G06Q30/02
摘要： Provided are a predetermined usage amount acquisition unit acquiring predetermined usage amount information within a predetermined period about the computer resources from the user terminals, a real usage amount calculation unit calculating real usage amount information indicating amount of actual usage of the user terminals within the predetermined period, and a charge calculation unit calculating, when calculating a charge imposed on the user terminals on the basis of the predetermined usage amount information and the real usage amount information, respectively a charge for a real usage amount equal to or larger than the predetermined usage amount and a charge for a real usage amount equal to or smaller than the predetermined usage amount in the whole usage amount by applying amount of money per different unit usage amount.
摘要翻译：预定使用量获取单元，从用户终端获取关于计算机资源的规定期间内的预定使用量信息，实际使用量计算单元，计算表示规定期间内的用户终端的实际使用量的实际使用量信息以及计费单元，计算在根据预定使用量信息和实际使用量信息计算施加在用户终端上的费用时，分别计算等于或大于预定使用量的实际使用量的费用以及通过应用不同单位使用量的金额，对整个使用量的等于或小于预定使用量的实际使用量的费用。

27. 发明授权

US06754126B2 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US06754126B2
公开(公告)日：2004-06-22
申请号：US10106597
申请日：2002-03-27
申请人： Shusaku Yamaguchi , Toshiya Uchida , Yoshimasa Yagishita , Yoshihide Bando , Masahiro Yada , Masaki Okuda , Hiroyuki Kobayashi , Kota Hara , Shinya Fujioka , Waichiro Fujieda
发明人： Shusaku Yamaguchi , Toshiya Uchida , Yoshimasa Yagishita , Yoshihide Bando , Masahiro Yada , Masaki Okuda , Hiroyuki Kobayashi , Kota Hara , Shinya Fujioka , Waichiro Fujieda
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C8/12 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4087 , G11C2211/4061 , G11C2211/4062
摘要： A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.
摘要翻译：形成多个第一存储块和用于再现第一存储块的数据的第二存储块。当读命令和刷新命令彼此冲突时，读控制电路根据刷新命令访问第一存储块，并通过使用第二存储块再现读数据。当写命令和刷新命令彼此冲突时，写控制电路根据命令接收的顺序操作存储块。因此，可以在不被用户识别的情况下进行刷新操作。即，可以提供用户友好的半导体存储器。

28. 发明授权

US06667913B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06667913B2
公开(公告)日：2003-12-23
申请号：US10285425
申请日：2002-11-01
申请人： Masaki Okuda , Hiroyuki Kobayashi
发明人： Masaki Okuda , Hiroyuki Kobayashi
IPC分类号： G11C1604
CPC分类号： G11C29/028 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C29/02 , G11C29/50 , G11C29/56012
摘要： A phase adjustment circuit delays an external clock signal to generate an adjusted clock signal. A phase comparator compares phases of the external clock signal and the adjusted clock signal, and outputs a phase adjustment signal for adjusting a delay time of the phase adjustment circuit. A data output circuit outputs read data to a data terminal in synchronization with the adjusted clock signal. A data input circuit receives write data supplied to the data terminal, in synchronization with the adjusted clock signal. When performing input of the write data and output of the read data successively, switching control between the input operation of the write data and the output operation of the read data only has to be completed within one clock cycle. The clock cycle can thus be reduced to the time required for the switching control. Consequently, maximum frequency of the external clock signal can be increased.
摘要翻译：相位调整电路延迟外部时钟信号以产生经调整的时钟信号。相位比较器比较外部时钟信号和调整后的时钟信号的相位，并输出用于调整相位调整电路的延迟时间的相位调整信号。数据输出电路与被调整的时钟信号同步地将数据输出到数据终端。数据输入电路与调整后的时钟信号同步地接收提供给数据终端的写入数据。当连续执行写入数据的输入和读取数据的输出时，必须在一个时钟周期内完成写入数据的输入操作和读取数据的输出操作之间的切换控制。因此，时钟周期可以减少到开关控制所需的时间。因此，可以增加外部时钟信号的最大频率。

29. 发明授权

US06535452B2 Semiconductor memory device having error correction function for data reading during refresh operation 有权
标题翻译：具有用于刷新操作期间的数据读取的纠错功能的半导体存储器件
公开(公告)号：US06535452B2
公开(公告)日：2003-03-18
申请号：US10097621
申请日：2002-03-15
申请人： Masaki Okuda , Toshiya Uchida
发明人： Masaki Okuda , Toshiya Uchida
IPC分类号： G11C800
CPC分类号： G06F11/1032 , G11C7/1006 , G11C11/406 , G11C11/4096 , G11C2207/002 , G11C2207/065 , G11C2207/108
摘要： A semiconductor memory device includes a plurality of memory blocks, each of which is refreshed independently of one another, m (m>1) data pins, each of which continuously receives or outputs n (n>1) data pieces, a conversion circuit which converts data of each of the data pins between parallel data and serial data, m×n data bus lines on which the n data pieces are expanded in parallel with respect to each of the m data pins, m address selection lines which are connected to m respective blocks of the memory blocks corresponding to the m respective data pins, and are simultaneously activated, the activation of any one of the address selection lines connecting the data bus lines to a corresponding one of the m respective blocks and resulting in the n data pieces being input/output to/from the corresponding one of the m respective blocks.
摘要翻译：一种半导体存储器件包括多个存储块，每个存储块彼此独立地刷新，m（m> 1）个数据引脚，每个存储块连续地接收或输出n（n> 1）个数据段，转换电路在并行数据和串行数据之间转换每个数据引脚的数据，相对于每个m个数据引脚并行扩展n个数据段的m×n数据总线，连接到m个相应块的m个地址选择线的对应于各个数据引脚的存储器块，并且同时被激活，将数据总线线路中的任何一个地址选择线激活到相应的m个块中的相应一个，并且导致n个数据段被输入 /输出到相应的m个相应块中的一个。

30. 发明授权

US6104659A Memory device 有权
标题翻译：内存设备
公开(公告)号：US6104659A
公开(公告)日：2000-08-15
申请号：US338599
申请日：1999-06-23
申请人： Yoshimasa Yagishita , Toshiya Uchida , Masaki Okuda
发明人： Yoshimasa Yagishita , Toshiya Uchida , Masaki Okuda
IPC分类号： G11C11/413 , G05F1/00 , G11C5/14 , G11C11/401 , G11C11/406 , G11C11/407 , G11C7/00
CPC分类号： G11C5/143 , G11C5/147
摘要： A memory device comprises: a plurality of banks each of which includes an array of memory cells; and at least a first and a second internal power generator, provided for each of the plurality of banks, for generating an internal power source voltage which differs from a voltage supplied by an external power source. If the internal common power source voltage in the memory device is lower than the first voltage when the power is on, the first and the second internal power generators in a plurality of banks are activated so as to rapidly raise the common internal power source voltage. When the common internal power source voltage in the memory device is higher than the first voltage and lower than the second voltage, the second internal power generators in the banks are activated to compensate for a drop in the internal power source voltage, which is caused by current leakage. When the internal power source voltage in a bank in the activated state is lower than the third voltage, the first and the second internal power generators in the corresponding bank are activated and satisfactorily drive the internal power source voltage in the bank so as to operate the memory device at a high speed.
摘要翻译：存储器件包括：多个存储体，每个存储体包括存储器单元的阵列; 以及为多个组中的每一个提供的至少第一和第二内部发电机，用于产生不同于由外部电源提供的电压的内部电源电压。如果在电源接通时存储器件内部的公共电源电压低于第一电压，则多个组中的第一和第二内部发电机被激活，以便迅速提高公共内部电源电压。当存储器件中的公共内部电源电压高于第一电压并低于第二电压时，该组中的第二内部发电机被激活以补偿内部电源电压的下降，这是由电流泄漏。当处于激活状态的组中的内部电源电压低于第三电压时，相应组中的第一和第二内部发电机被激活并令人满意地驱动组中的内部电源电压，以便操作高速存储设备。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式