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21. 发明申请

US20090198963A1 COMPLETION OF ASYNCHRONOUS MEMORY MOVE IN THE PRESENCE OF A BARRIER OPERATION 失效
标题翻译：在障碍物操作中完成异步记忆移动
公开(公告)号：US20090198963A1
公开(公告)日：2009-08-06
申请号：US12024513
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/02 , G06F9/30
CPC分类号： G06F9/30087 , G06F9/30032 , G06F9/3004 , G06F9/3834 , G06F9/3885 , G06F12/0831 , G06F12/0862 , G06F12/10
摘要： A method within a data processing system by which a processor executes an asynchronous memory move (AMM) store (ST) instruction to complete a corresponding AMM operation in parallel with an ongoing (not yet completed), previously issued barrier operation. The processor receives the AMM ST instruction after executing the barrier operation (or SYNC instruction) and before the completion of the barrier operation or SYNC on the system fabric. The processor continues executing the AMM ST instruction, which performs a move in virtual address space and then triggers the generation of the AMM operation. The AMM operation proceeds while the barrier operation continues, independent of the processor. The processor stops further execution of all other memory access requests, excluding AMM ST instructions that are received after the barrier operation, but before completion of the barrier operation.
摘要翻译：数据处理系统中的方法，通过该方法，处理器执行异步存储器移动（AMM）存储（ST）指令以与正在进行的（未完成）先前发布的屏障操作并行地完成对应的AMM操作。执行屏障操作（或SYNC指令）后，在系统结构上完成屏障操作或SYNC之前，处理器接收AMM ST指令。处理器继续执行AMM ST指令，其在虚拟地址空间中执行移动，然后触发AMM操作的生成。无障碍操作继续进行，与处理器无关，AMM操作继续进行。处理器停止所有其他存储器访问请求的进一步执行，排除在屏障操作之后但在屏障操作完成之前接收的AMM ST指令。

22. 发明申请

US20090198905A1 Techniques for Prediction-Based Indirect Data Prefetching 有权
标题翻译：基于预测的间接数据预取技术
公开(公告)号：US20090198905A1
公开(公告)日：2009-08-06
申请号：US12024248
申请日：2008-02-01
申请人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/02
CPC分类号： G06F12/0862 , G06F12/0897 , G06F12/1027 , G06F2212/6026
摘要： A technique for data prefetching using indirect addressing includes monitoring data pointer values, associated with an array, in an access stream to a memory. The technique determines whether a pattern exists in the data pointer values. A prefetch table is then populated with respective entries that correspond to respective array address/data pointer pairs based on a predicted pattern in the data pointer values. Respective data blocks (e.g., respective cache lines) are then prefetched (e.g., from the memory or another memory) based on the respective entries in the prefetch table.
摘要翻译：使用间接寻址的数据预取技术包括在到存储器的访问流中监视与阵列相关联的数据指针值。该技术确定数据指针值中是否存在模式。然后基于数据指针值中的预测模式，填充与各个阵列地址/数据指针对相对应的条目的预取表。然后，基于预取表中的相应条目，预取（例如，从存储器或另一存储器）分别的数据块（例如，相应的高速缓存行）。

23. 发明申请

US20090198904A1 Techniques for Data Prefetching Using Indirect Addressing with Offset 有权
标题翻译：使用偏移量进行间接寻址的数据预取技术
公开(公告)号：US20090198904A1
公开(公告)日：2009-08-06
申请号：US12024246
申请日：2008-02-01
申请人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/1045 , G06F2212/6028
摘要： A technique for performing data prefetching using indirect addressing includes determining a first memory address of a pointer associated with a data prefetch instruction. Content, that is included in a first data block (e.g., a first cache line) of a memory, at the first memory address is then fetched. An offset is then added to the content of the memory at the first memory address to provide a first offset memory address. A second memory address is then determined based on the first offset memory address. A second data block (e.g., a second cache line) that includes data at the second memory address is then fetched (e.g., from the memory or another memory). A data prefetch instruction may be indicated by a unique operational code (opcode), a unique extended opcode, or a field (including one or more bits) in an instruction.
摘要翻译：使用间接寻址执行数据预取的技术包括确定与数据预取指令相关联的指针的第一存储器地址。然后取出包含在第一存储器地址的存储器的第一数据块（例如，第一高速缓存行）中的内容。然后将偏移量添加到第一存储器地址处的存储器的内容以提供第一偏移存储器地址。然后基于第一偏移存储器地址确定第二存储器地址。包括第二存储器地址上的数据的第二数据块（例如，第二高速缓存行）然后被取出（例如，从存储器或另一个存储器）。数据预取指令可以由指令中的唯一操作代码（操作码），唯一扩展操作码或字段（包括一个或多个位）来指示。

24. 发明授权

US08458439B2 Block driven computation using a caching policy specified in an operand data structure 有权
标题翻译：使用在操作数数据结构中指定的缓存策略进行块驱动计算
公开(公告)号：US08458439B2
公开(公告)日：2013-06-04
申请号：US12336350
申请日：2008-12-16
申请人： Ravi K. Arimilli , Balaram Sinharoy
发明人： Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F2212/6028
摘要： A processor has an associated memory hierarchy including a cache memory. The processor includes an instruction sequencing unit that fetches instructions for processing, an operand data structure including a plurality of entries corresponding to operands of operations to be performed by the processor, and a computation engine. A first entry among the plurality of entries in the operand data structure specifies a first caching policy for a first operand, and a second entry specifies a second caching policy for a second operand. The computation engine computes and stores operands in the memory hierarchy in accordance with the cache policies indicated within the operand data structure.
摘要翻译：处理器具有包括高速缓冲存储器的相关联的存储器层级。所述处理器包括：指令排序单元，其提取用于处理的指令;操作数数据结构，包括与由所述处理器执行的操作操作数对应的多个条目;以及计算引擎。操作数数据结构中的多个条目中的第一条目指定第一操作数的第一高速缓存策略，第二条目指定用于第二操作数的第二高速缓存策略。计算引擎根据操作数数据结构中指示的缓存策略计算并存储存储器层次结构中的操作数。

25. 发明授权

US08327101B2 Cache management during asynchronous memory move operations 有权
标题翻译：异步存储器移动操作期间的缓存管理
公开(公告)号：US08327101B2
公开(公告)日：2012-12-04
申请号：US12024526
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/02
CPC分类号： G06F12/0815 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3017 , G06F9/3877 , G06F12/10
摘要： A data processing system includes a mechanism for completing an asynchronous memory move (AMM) operation in which the processor receives an AMM ST instruction and processes a processor-level move of data in virtual address space and an asynchronous memory mover then completes a physical move of the data within the real address space (memory). A status/control field of the AMM ST instruction includes an indication of a requested treatment of the lower level cache(s) on completion of the AMM operation. When the status/control field indicates an update to at least one cache should be performed, the asynchronous memory mover automatically forwards a copy of the data from the data move to the lower level cache, and triggers an update of a coherency state for a cache line in which the copy of the data is placed.
摘要翻译：数据处理系统包括用于完成异步存储器移动（AMM）操作的机制，其中处理器接收AMM ST指令并处理虚拟地址空间中的数据的处理器级移动，然后异步存储器移动器完成物理移动实际地址空间（内存）中的数据。 AMM ST指令的状态/控制字段在完成AMM操作时包括对低级缓存的请求处理的指示。当状态/控制字段指示应该执行至少一个缓存的更新时，异步存储器移动器自动将数据的副本从数据移动转发到较低级的高速缓存，并触发高速缓存的一致性状态的更新其中放置数据副本的行。

26. 发明授权

US08281106B2 Specifying an addressing relationship in an operand data structure 有权
标题翻译：在操作数数据结构中指定寻址关系
公开(公告)号：US08281106B2
公开(公告)日：2012-10-02
申请号：US12336342
申请日：2008-12-16
申请人： Ravi K. Arimilli , Balaram Sinharoy
发明人： Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F9/345
摘要： A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit, and an instruction sequencing unit that fetches instructions for execution by the execution unit. The processor further includes an operand data structure and an address generation accelerator. The operand data structure specifies a first relationship between addresses of sequential accesses within a first address region and a second relationship between addresses of sequential accesses within a second address region. The address generation accelerator computes a first address of a first memory access in the first address region by reference to the first relationship and a second address of a second memory access in the second address region by reference to the second relationship.
摘要翻译：处理器包括执行指令的至少一个执行单元，耦合到所述至少一个执行单元的至少一个寄存器文件，其缓冲由所述至少一个执行单元访问的操作数，以及指令排序单元，其提取用于执行的指令由执行单位。处理器还包括操作数数据结构和地址生成加速器。操作数数据结构指定第一地址区域内的顺序访问的地址与第二地址区域内的顺序存取的地址之间的第一关系。参考第二关系，地址生成加速器通过参考第一关系和第二地址区中的第二存储器访问的第二地址来计算第一地址区中的第一存储器访问的第一地址。

27. 发明授权

US08250307B2 Sourcing differing amounts of prefetch data in response to data prefetch requests 失效
标题翻译：根据数据预取请求采购不同数量的预取数据
公开(公告)号：US08250307B2
公开(公告)日：2012-08-21
申请号：US12024165
申请日：2008-02-01
申请人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/30043 , G06F9/3455
摘要： According to a method of data processing, a memory controller receives a prefetch load request from a processor core of a data processing system. The prefetch load request specifies a requested line of data. In response to receipt of the prefetch load request, the memory controller determines by reference to a stream of demand requests how much data is to be supplied to the processor core in response to the prefetch load request. In response to the memory controller determining to provide less than all of the requested line of data, the memory controller provides less than all of the requested line of data to the processor core.
摘要翻译：根据数据处理的方法，存储器控制器从数据处理系统的处理器核心接收预取负载请求。预取加载请求指定所请求的数据行。响应于接收到预取加载请求，存储器控制器通过参考需求请求流来确定响应于预取加载请求将多少数据提供给处理器核。响应于存储器控制器确定提供少于全部所请求的数据行，存储器控制器将少于所有请求的数据行提供给处理器核。

28. 发明授权

US08166277B2 Data prefetching using indirect addressing 有权
标题翻译：使用间接寻址进行数据预取
公开(公告)号：US08166277B2
公开(公告)日：2012-04-24
申请号：US12024186
申请日：2008-02-01
申请人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A technique for performing indirect data prefetching includes determining a first memory address of a pointer associated with a data prefetch instruction. Content of a memory at the first memory address is then fetched. A second memory address is determined from the content of the memory at the first memory address. Finally, a data block (e.g., a cache line) including data at the second memory address is fetched (e.g., from the memory or another memory).
摘要翻译：用于执行间接数据预取的技术包括确定与数据预取指令相关联的指针的第一存储器地址。然后获取第一个存储器地址上的存储器的内容。从第一存储器地址处的存储器的内容确定第二存储器地址。最后，取出包括第二存储器地址上的数据的数据块（例如，高速缓存行）（例如，从存储器或另一个存储器）。

29. 发明授权

US08161265B2 Techniques for multi-level indirect data prefetching 有权
标题翻译：多级间接数据预取技术
公开(公告)号：US08161265B2
公开(公告)日：2012-04-17
申请号：US12024260
申请日：2008-02-01
申请人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F13/00
CPC分类号： G06F12/1027 , G06F12/0862 , G06F12/0897 , G06F2212/6026 , G06F2212/681
摘要： A technique for performing data prefetching using multi-level indirect data prefetching includes determining a first memory address of a pointer associated with a data prefetch instruction. Content that is included in a first data block (e.g., a first cache line of a memory) at the first memory address is then fetched. A second memory address is then determined based on the content at the first memory address. Content that is included in a second data block (e.g., a second cache line) at the second memory address is then fetched (e.g., from the memory or another memory). A third memory address is then determined based on the content at the second memory address. Finally, a third data block (e.g., a third cache line) that includes another pointer or data at the third memory address is fetched (e.g., from the memory or the another memory).
摘要翻译：使用多级间接数据预取来执行数据预取的技术包括确定与数据预取指令相关联的指针的第一存储器地址。然后取出包含在第一存储器地址的第一数据块（例如，存储器的第一高速缓存行）中的内容。然后基于第一存储器地址处的内容来确定第二存储器地址。包含在第二存储器地址的第二数据块（例如，第二高速缓存行）中的内容然后被取出（例如，从存储器或另一个存储器）。然后基于第二存储器地址处的内容来确定第三存储器地址。最后，取出（例如，从存储器或另一个存储器）中包含第三存储器地址处的另一指针或数据的第三数据块（例如，第三高速缓存行）。

30. 发明授权

US08161263B2 Techniques for indirect data prefetching 有权
标题翻译：间接数据预取技术
公开(公告)号：US08161263B2
公开(公告)日：2012-04-17
申请号：US12024239
申请日：2008-02-01
申请人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A processor includes a first address translation engine, a second address translation engine, and a prefetch engine. The first address translation engine is configured to determine a first memory address of a pointer associated with a data prefetch instruction. The prefetch engine is coupled to the first translation engine and is configured to fetch content, included in a first data block (e.g., a first cache line) of a memory, at the first memory address. The second address translation engine is coupled to the prefetch engine and is configured to determine a second memory address based on the content of the memory at the first memory address. The prefetch engine is also configured to fetch (e.g., from the memory or another memory) a second data block (e.g., a second cache line) that includes data at the second memory address.
摘要翻译：处理器包括第一地址转换引擎，第二地址转换引擎和预取引擎。第一地址转换引擎被配置为确定与数据预取指令相关联的指针的第一存储器地址。预取引擎被耦合到第一翻译引擎，并被配置为在第一存储器地址处提取包含在存储器的第一数据块（例如，第一高速缓存行）中的内容。第二地址转换引擎耦合到预取引擎，并且被配置为基于第一存储器地址处的存储器的内容来确定第二存储器地址。预取引擎还被配置为从第二存储器地址提取包括数据的第二数据块（例如，第二高速缓存行）（例如，从存储器或另一存储器）。

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