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21. 发明授权

US08592290B1 Cut-very-last dual-EPI flow 有权
标题翻译：切割最后的双EPI流程
公开(公告)号：US08592290B1
公开(公告)日：2013-11-26
申请号：US13545456
申请日：2012-07-10
申请人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E. Standaert , Tenko Yamashita
发明人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E. Standaert , Tenko Yamashita
IPC分类号： H01L21/20
CPC分类号： H01L29/66795 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/6681
摘要： A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.
摘要翻译：描述了制造双外延FinFET的方法。该方法包括将第一外延材料添加到翅片阵列。该方法还包括使用第一掩蔽材料覆盖翅片阵列的至少第一部分并且从翅片阵列的未覆盖部分移除第一外延材料。在散热片阵列的未覆盖部分中的翅片上添加第二外延材料包括在该方法中。该方法还包括使用第二掩模材料覆盖翅片阵列的第二部分，并使用第一掩模材料和第二掩模材料执行定向蚀刻。还描述了装置和计算机程序产品。

22. 发明申请

US20120146175A1 INSULATING REGION FOR A SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：半导体衬底的绝缘区域
公开(公告)号：US20120146175A1
公开(公告)日：2012-06-14
申请号：US12963715
申请日：2010-12-09
申请人： Nicolas Loubet , Qing Liu , Sanjay C. Mehta , Spyridon Skordas
发明人： Nicolas Loubet , Qing Liu , Sanjay C. Mehta , Spyridon Skordas
IPC分类号： H01L29/02 , H01L21/762
CPC分类号： H01L29/78603 , H01L21/02112 , H01L21/02274 , H01L21/0228 , H01L21/76224 , H01L21/7624 , H01L29/66772
摘要： An insulating region for a semiconductor wafer and a method of forming same. The insulating region can include a tri-layer structure of silicon oxide, boron nitride and silicon oxide. The insulating region may be used to insulate a semiconductor device layer from an underlying bulk semiconductor substrate. The insulating region can be formed by coating the sides of a very thin cavity with silicon oxide, and filling the remainder of the cavity between the silicon oxide regions with boron nitride.
摘要翻译：半导体晶片的绝缘区域及其形成方法。绝缘区域可以包括氧化硅，氮化硼和氧化硅的三层结构。绝缘区域可以用于使半导体器件层与下面的体半导体衬底绝缘。绝缘区域可以通过用氧化硅涂覆非常薄的腔体的侧面并且用氮化硼填充氧化硅区域之间的空腔的其余部分来形成。

23. 发明授权

US08900973B2 Method to enable compressively strained pFET channel in a FinFET structure by implant and thermal diffusion 有权
标题翻译：通过植入和热扩散使得FinFET结构中的压应变应变pFET通道的方法
公开(公告)号：US08900973B2
公开(公告)日：2014-12-02
申请号：US13221198
申请日：2011-08-30
申请人： Nathaniel C. Berliner , Pranita Kulkarni , Nicolas Loubet , Kingsuk Maitra , Sanjay C. Mehta , Paul A. Ronsheim , Toyoji Yamamoto , Zhengmao Zhu
发明人： Nathaniel C. Berliner , Pranita Kulkarni , Nicolas Loubet , Kingsuk Maitra , Sanjay C. Mehta , Paul A. Ronsheim , Toyoji Yamamoto , Zhengmao Zhu
IPC分类号： H01L21/326 , H01L21/84 , H01L27/12 , H01L29/78
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/7848
摘要： A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.
摘要翻译：制造半导体器件的方法在pFET区域中形成第一鳍，并且在nFET区域中形成第二鳍。包含应变材料的多个保形微层沉积在第一和第二鳍片上。在第一翅片上形成保护盖材料，并且从第二翅片选择性地去除保形层。然后将应变材料热扩散到第一鳍中。在热退火之后以及在从第二散热片选择性地去除保形微层之后，从第一散热片上去除保护帽材料。

24. 发明申请

US20140024203A1 SHALLOW HEAVILY DOPED SEMICONDUCTOR LAYER BY CYCLIC SELECTIVE EPITAXIAL DEPOSITION PROCESS 有权
标题翻译：通过循环选择性外延沉积工艺沉积重金属半导体层
公开(公告)号：US20140024203A1
公开(公告)日：2014-01-23
申请号：US13988436
申请日：2010-11-19
申请人： Vincent Destefanis , Nicolas Loubet
发明人： Vincent Destefanis , Nicolas Loubet
IPC分类号： H01L21/02
CPC分类号： H01L21/0226 , H01L21/02499 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02642
摘要： The deposition method comprises providing a substrate with a first mono-crystalline zone made of a semiconductor material and a second zone made of an insulating material. During a passivation step, a passivation atmosphere is applied on the substrate so as to cover the first zone with doping impurities. During a deposition step, gaseous silicon and/or germanium precursors are introduced and a doped semiconductor film is formed. The semiconductor film is mono-crystalline over the first zone and has a different texture over the second zone. During an etching step, a chloride gaseous precursor is applied on the substrate so as to remove the semiconductor layer over the second zone.
摘要翻译：沉积方法包括提供具有由半导体材料制成的第一单晶区和由绝缘材料制成的第二区的衬底。在钝化步骤期间，钝化气氛被施加在衬底上，以便用掺杂杂质覆盖第一区域。在沉积步骤期间，引入气态硅和/或锗前体并形成掺杂半导体膜。半导体膜在第一区域上是单晶的，并且在第二区域上具有不同的纹理。在蚀刻步骤期间，将氯化物气体前体施加在衬底上，以便在第二区域上移除半导体层。

25. 发明申请

US20090023275A1 METHOD FOR FORMING SILICON WELLS OF DIFFERENT CRYSTALLOGRAPHIC ORIENTATIONS 有权
标题翻译：用于形成不同晶体取向方位硅的方法
公开(公告)号：US20090023275A1
公开(公告)日：2009-01-22
申请号：US12175877
申请日：2008-07-18
申请人： Nicolas Loubet , Didier Dutartre , Frederic Boeuf
发明人： Nicolas Loubet , Didier Dutartre , Frederic Boeuf
IPC分类号： H01L21/20
CPC分类号： H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/0262 , H01L21/02639
摘要： A method for manufacturing silicon wells of various crystallographic orientations in a silicon support, including the steps of: forming a silicon layer having a first orientation on a silicon substrate having a second orientation; forming insulating walls, defining wells extend at least down to the border between the silicon substrate and the silicon layer; performing, in first wells, a chemical vapor etch (CVE) of the silicon layer by means of hydrochloric acid, in an epitaxy reactor, at a temperature ranging between 700° C. and 950° C.; and performing, in the first wells, a vapor-phase epitaxy on the silicon substrate in the presence of a precursor of silicon and hydrochloric acid, at a temperature ranging between 700° C. and 900° C. and up to the upper surface of the silicon layer.
摘要翻译：一种用于制造硅载体中各种晶体取向硅阱的方法，包括以下步骤：在具有第二取向的硅衬底上形成具有第一取向的硅层; 形成绝缘壁，限定阱至少向下延伸到硅衬底和硅层之间的边界; 在外延反应器中，在700℃至950℃的温度范围内，通过盐酸在第一个阱中进行硅层的化学气相蚀刻（CVE）。并且在第一个阱中，在硅和盐酸的前体存在下，在700℃和900℃之间的温度范围内，在硅衬底上进行气相外延，直到上述表面硅层。

26. 发明申请

US20120252174A1 PROCESS FOR FORMING AN EPITAXIAL LAYER, IN PARTICULAR ON THE SOURCE AND DRAIN REGIONS OF FULLY-DEPLETED TRANSISTORS 审中-公开
标题翻译：形成外延层的方法，特别是完全放电的晶体管的源和漏区
公开(公告)号：US20120252174A1
公开(公告)日：2012-10-04
申请号：US13434923
申请日：2012-03-30
申请人： Didier Dutartre , Nicolas Loubet , Yves Campidelli , Denis Pellissier-Tanon
发明人： Didier Dutartre , Nicolas Loubet , Yves Campidelli , Denis Pellissier-Tanon
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/0262 , H01L21/02636 , H01L29/66628 , H01L29/78 , H01L29/7848
摘要： A layer of a semiconductor material is epitaxially grown on a single-crystal semiconductor structure and on a polycrystalline semiconductor structure. The epitaxial layer is then etched in order to preserve a non-zero thickness of said material on the single-crystal structure and a zero thickness on the polycrystalline structure. The process of growth and etch is repeated, with the same material or with a different material in each repetition, until a stack of epitaxial layers on said single-crystal structure has reached a desired thickness. The single crystal structure is preferably a source/drain region of a transistor, and the polycrystalline structure is preferably a gate of that transistor.
摘要翻译：在单晶半导体结构和多晶半导体结构上外延生长半导体材料层。然后蚀刻外延层，以便在单晶结构上保留所述材料的非零厚度，并在多晶结构上保持零厚度。在每个重复中，使用相同的材料或不同的材料重复生长和蚀刻的过程，直到所述单晶结构上的一叠外延层已经达到期望的厚度。单晶结构优选为晶体管的源/漏区，多晶结构优选为该晶体管的栅极。

27. 发明授权

US07906381B2 Method for integrating silicon-on-nothing devices with standard CMOS devices 有权
标题翻译：将无硅器件与标准CMOS器件集成的方法
公开(公告)号：US07906381B2
公开(公告)日：2011-03-15
申请号：US12167282
申请日：2008-07-03
申请人： Nicolas Loubet , Didier Dutartre , Stéphane Monfray
发明人： Nicolas Loubet , Didier Dutartre , Stéphane Monfray
IPC分类号： H01L21/84
CPC分类号： H01L27/1203 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1207
摘要： A method is provided for fabricating transistors of first and second types in a single substrate. First and second active zones of the substrate are delimited by lateral isolation trench regions, and a portion of the second active zone is removed so that the second active zone is below the first active zone. First and second layers of semiconductor material are formed on the second active zone, so that the second layer is substantially in the same plane as the first active zone. Insulated gates are produced on the first active zone and the second layer. At least one isolation trench region is selectively removed, and the first layer is selectively removed so as to form a tunnel under the second layer. The tunnel is filled with a dielectric material to insulate the second layer from the second active zone of the substrate. Also provided is such an integrated circuit.
摘要翻译：提供了一种用于在单个衬底中制造第一和第二类型的晶体管的方法。衬底的第一和第二活性区由横向隔离沟槽区限定，并且去除第二活性区的一部分，使得第二活性区位于第一活性区以下。第一和第二层半导体材料形成在第二有源区上，使得第二层基本上处于与第一活性区相同的平面。在第一活性区和第二层产生绝缘栅。选择性地去除至少一个隔离沟槽区域，并且选择性地去除第一层，以便在第二层下形成隧道。隧道填充有电介质材料以使第二层与衬底的第二活性区绝缘。还提供了这种集成电路。

28. 发明授权

US07776745B2 Method for etching silicon-germanium in the presence of silicon 有权
标题翻译：在硅存在下蚀刻硅锗的方法
公开(公告)号：US07776745B2
公开(公告)日：2010-08-17
申请号：US11704799
申请日：2007-02-09
申请人： Nicolas Loubet , Didier Dutartre , Alexandre Talbot , Laurent Rubaldo
发明人： Nicolas Loubet , Didier Dutartre , Alexandre Talbot , Laurent Rubaldo
IPC分类号： H01L21/302
CPC分类号： H01L21/306 , H01L21/3065
摘要： A method for selectively etching single-crystal silicon-germanium in the presence of single-crystal silicon, including a chemical etch based on hydrochloric acid in gaseous phase at a temperature lower than approximately 700° C.
摘要翻译：在单晶硅存在下选择性蚀刻单晶硅锗的方法，包括在低于大约700℃的温度下在气相中基于盐酸的化学蚀刻。

29. 发明授权

US07622368B2 Forming of a single-crystal semiconductor layer portion separated from a substrate 有权
标题翻译：从衬底分离的单晶半导体层部分的形成
公开(公告)号：US07622368B2
公开(公告)日：2009-11-24
申请号：US11704638
申请日：2007-02-09
申请人： Didier Dutartre , Nicolas Loubet , Alexandre Talbot
发明人： Didier Dutartre , Nicolas Loubet , Alexandre Talbot
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L29/66772 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02639
摘要： A method for forming a single-crystal semiconductor layer portion above a hollowed area, including growing by selective epitaxy on an active single-crystal semiconductor region a sacrificial single-crystal semiconductor layer and a single-crystal semiconductor layer, and removing the sacrificial layer. The epitaxial growth is performed while the active region is surrounded with a raised insulating layer and the removal of the sacrificial single-crystal semiconductor layer is performed through an access resulting from an at least partial removal of the raised insulating layer.
摘要翻译：一种用于在中空区域上方形成单晶半导体层部分的方法，包括通过牺牲单晶半导体层和单晶半导体层在活性单晶半导体区域上的选择性外延生长，以及去除牺牲层。在有源区域被凸起的绝缘层围绕的同时进行外延生长，并且通过由至少部分去除凸起的绝缘层获得的访问来执行牺牲单晶半导体层的去除。

30. 发明授权

US08546203B1 Semiconductor structure having NFET extension last implants 有权
标题翻译：具有NFET延伸最后植入物的半导体结构
公开(公告)号：US08546203B1
公开(公告)日：2013-10-01
申请号：US13551100
申请日：2012-07-17
申请人： Kangguo Cheng , Bruce B. Doris , Bala S. Haran , Pranita Kulkarni , Nicolas Loubet , Amlan Majumdar , Stefan Schmitz
发明人： Kangguo Cheng , Bruce B. Doris , Bala S. Haran , Pranita Kulkarni , Nicolas Loubet , Amlan Majumdar , Stefan Schmitz
IPC分类号： H01L21/00
CPC分类号： H01L21/84 , H01L29/66628
摘要： Method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. Low quality nitride and high quality nitride are formed on the semiconductor structure. The high quality nitride in the NFET portion is damaged by ion implantation to facilitate its removal. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The high quality nitride in the PFET portion is damaged by ion implantation to facilitate its removal. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.
摘要翻译：形成半导体结构的方法包括具有PFET部分和NFET部分的极薄的绝缘上硅（ETSOI）半导体结构，PFET部分中的栅极结构和NFET部分，与 PFET部分中的栅极结构和NFET部分以及PFET部分中的掺杂多面外延硅锗升高源极/漏极（RSD）。在半导体结构上形成低质量的氮化物和高质量的氮化物。 NFET部分中的高质量氮化物被离子注入损坏以便于其去除。在与NFET部分中的高质量氮化物相邻的ETSOI上形成刻面外延硅RSD。 PFET部分中的高质量氮化物被离子注入损坏以便于其去除。扩展件被离子注入到NFET部分中的栅极结构下面的ETSOI中。

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