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21. 发明申请

US20140252470A1 Semiconductor Device with Integrated Electrostatic Discharge (ESD) Clamp 有权
标题翻译：具有集成静电放电（ESD）钳位的半导体器件
公开(公告)号：US20140252470A1
公开(公告)日：2014-09-11
申请号：US13792748
申请日：2013-03-11
申请人： Weize Chen , Patrice M. Parris
发明人： Weize Chen , Patrice M. Parris
IPC分类号： H01L27/02 , H01L21/82
CPC分类号： H01L27/0259 , H01L21/76224 , H01L21/76895 , H01L27/027 , H01L27/0711 , H01L27/0722 , H01L29/0623 , H01L29/0649 , H01L29/0653 , H01L29/1083 , H01L29/1087 , H01L29/6625 , H01L29/66659 , H01L29/66681 , H01L29/78 , H01L29/7835
摘要： A device includes a substrate, a body region in the substrate and having a first conductivity type, source and drain regions in the substrate, having a second conductivity type, and spaced from one another to define a conduction path that passes through the body region, a doped isolating region in the substrate, having the second conductivity type, and configured to surround a device area in which the conduction path is disposed, an isolation contact region in the substrate, having the second conductivity type, and electrically coupled to the doped isolating region to define a collector region of a bipolar transistor, and first and second contact regions within the body region, having the first and second conductivity types, respectively, and configured to define a base contact region and an emitter region of the bipolar transistor, respectively.
摘要翻译：一种器件包括衬底，衬底中的体区，并且具有第一导电类型，衬底中的源区和漏区，具有第二导电类型，并且彼此间隔开以限定通过体区的导电路径，衬底中的掺杂隔离区域，具有第二导电类型，并且被配置为围绕其中设置导电路径的器件区域，具有第二导电类型的衬底中的隔离接触区域，并且电耦合到掺杂隔离层区域以限定双极晶体管的集电极区域，以及体区内的第一和第二接触区域，分别具有第一和第二导电类型，并且被配置为分别限定双极晶体管的基极接触区域和发射极区域。

22. 发明申请

US20130270635A1 Semiconductor Device with False Drain 有权
标题翻译：漏水半导体器件
公开(公告)号：US20130270635A1
公开(公告)日：2013-10-17
申请号：US13448062
申请日：2012-04-16
申请人： Patrice M. Parris , Weize Chen
发明人： Patrice M. Parris , Weize Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/823418 , H01L27/088 , H01L29/063 , H01L29/0634 , H01L29/0653 , H01L29/402 , H01L29/66659 , H01L29/7835
摘要： An electronic apparatus includes a semiconductor substrate and first and second transistors disposed in the semiconductor substrate. The first transistor includes a channel region and a drain region adjacent the channel region. The second transistor includes a channel region, a false drain region adjacent the channel region, and a drain region electrically coupled to the channel region by a drift region such that the second transistor is configured for operation at a higher voltage level than the first transistor. The respective channel regions of the first and second transistors have a common configuration characteristic.
摘要翻译：电子设备包括半导体衬底和设置在半导体衬底中的第一和第二晶体管。第一晶体管包括与沟道区相邻的沟道区和漏极区。第二晶体管包括沟道区，邻近沟道区的假漏极区，以及通过漂移区电耦合到沟道区的漏极区，使得第二晶体管被配置为在比第一晶体管更高的电压电平下工作。第一和第二晶体管的各个沟道区具有共同的配置特性。

23. 发明申请

US20110299337A1 METHODS AND APPARATUS FOR AN ISFET 有权
标题翻译：用于ISFET的方法和装置
公开(公告)号：US20110299337A1
公开(公告)日：2011-12-08
申请号：US12794591
申请日：2010-06-04
申请人： Patrice M. Parris , Weize Chen , Richard J. De Souza , Md M. Hoque , John M. McKenna
发明人： Patrice M. Parris , Weize Chen , Richard J. De Souza , Md M. Hoque , John M. McKenna
IPC分类号： G11C16/04 , H01L21/28 , H01L27/108
CPC分类号： G01N27/4148 , G05F1/575 , G11C16/0416 , H01L21/28035 , H01L23/5223 , H01L27/11526 , H01L27/11558 , H01L28/40 , H01L28/60 , H01L29/66825 , H01L29/788 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.
摘要翻译： ISFET包括耦合到CMOS器件中的浮动栅极的控制栅极。控制栅极，例如多孔阱电容器被配置为接收偏置电压并且在控制栅极和浮置栅极之间实现俘获电荷的移动。因此，ISFET的阈值电压可以被修整到预定值，从而将修剪信息（浮置栅极中的俘获电荷的量）存储在ISFET本身内。

24. 发明申请

US20090290437A1 CIRCUIT FOR AND AN ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY CELL AND A PROCESS OF FORMING THE ELECTRONIC DEVICE 有权
标题翻译：包括非易失性存储单元的电子设备和形成电子设备的方法
公开(公告)号：US20090290437A1
公开(公告)日：2009-11-26
申请号：US12126069
申请日：2008-05-23
申请人： Weize Chen , Patrice M. Parris
发明人： Weize Chen , Patrice M. Parris
IPC分类号： G11C7/00 , H01L21/82
CPC分类号： G11C16/0441 , G11C16/10 , H01L27/11519 , H01L27/11521
摘要： A circuit for a nonvolatile memory cell can include a charge-altering terminal and an output terminal. The circuit can also include a first transistor having a gate electrode that electrically floats and an active region including a current-carrying electrode, wherein the current-carrying electrode is coupled to the output terminal. The circuit can further include a second transistor having a first electrode and a second electrode, wherein the first electrode is coupled to the gate electrode of the first transistor, and the second electrode is coupled to the charge-altering terminal. When changing the state of the memory cell, the second transistor can be active and no significant amount of charge carriers are transferred between the gate electrode of the first transistor and the active region of the first transistor. Other embodiments can include the electronic device itself and a process of forming the electronic device.
摘要翻译：用于非易失性存储单元的电路可以包括电荷变换端子和输出端子。电路还可以包括具有电浮置的栅电极的第一晶体管和包括载流电极的有源区，其中载流电极耦合到输出端。电路还可以包括具有第一电极和第二电极的第二晶体管，其中第一电极耦合到第一晶体管的栅电极，第二电极耦合到电荷改变端。当改变存储单元的状态时，第二晶体管可以是有效的，并且在第一晶体管的栅电极和第一晶体管的有源区之间不传输大量的电荷载流子。其他实施例可以包括电子设备本身和形成电子设备的过程。

25. 发明授权

US09673188B2 Integrated electrostatic discharge (ESD) clamping for an LDMOS transistor device having a bipolar transistor 有权
公开(公告)号：US09673188B2
公开(公告)日：2017-06-06
申请号：US14966688
申请日：2015-12-11
申请人： Weize Chen , Patrice M. Parris
发明人： Weize Chen , Patrice M. Parris
IPC分类号： H01L27/07 , H01L27/02 , H01L21/762 , H01L29/78 , H01L29/66 , H01L21/768 , H01L29/06 , H01L29/10
CPC分类号： H01L27/0259 , H01L21/76224 , H01L21/76895 , H01L27/027 , H01L27/0711 , H01L27/0722 , H01L29/0623 , H01L29/0649 , H01L29/0653 , H01L29/1083 , H01L29/1087 , H01L29/6625 , H01L29/66659 , H01L29/66681 , H01L29/78 , H01L29/7835
摘要： A method of fabricating a laterally diffused metal-oxide-semiconductor (LDMOS) transistor device having a bipolar transistor for electrostatic discharge (ESD) protection includes doping a substrate to form a body region of the LDMOS transistor device in the substrate, the body region having a first conductivity type, forming a doped isolating region of the LDMOS transistor device in the substrate, the doped isolating region having a second conductivity type and surrounding a device area of the LDMOS transistor device in which the body region is disposed, forming a base contact region of the bipolar transistor, the base contact region being disposed within the body region and having the first conductivity type, and doping the substrate to form an isolation contact region for the doped isolating region that defines a collector region of the bipolar transistor, to form source and drain regions of the LDMOS transistor device in the substrate, and to form an emitter region of the bipolar transistor within the body region.

26. 发明申请

US20160365422A1 INTEGRATED CIRCUIT DEVICES WITH COUNTER-DOPED CONDUCTIVE GATES 有权
标题翻译：具有反向导电门的集成电路装置
公开(公告)号：US20160365422A1
公开(公告)日：2016-12-15
申请号：US15246262
申请日：2016-08-24
申请人： Weize Chen , Richard J. de Souza , Md M. Hoque , Patrice M. Parris
发明人： Weize Chen , Richard J. de Souza , Md M. Hoque , Patrice M. Parris
IPC分类号： H01L29/49 , H01L21/8234 , H01L29/66 , H01L29/78 , H01L21/28 , H01L29/06
CPC分类号： H01L29/4933 , H01L21/28052 , H01L21/28105 , H01L21/823443 , H01L21/823842 , H01L27/0922 , H01L29/0653 , H01L29/4983 , H01L29/66477 , H01L29/66575 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要： Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.
摘要翻译：具有反掺杂导电栅极的集成电路器件。这些器件具有具有衬底表面的半导体衬底。器件还具有第一导电类型的第一阱，第二导电类型的源极和第二导电类型的漏极。通道在源极和漏极之间延伸。导电栅极延伸穿过沟道。导电栅极包括第一导电类型的第一栅极区域和第二栅极区域以及第一导电类型的第三栅极区域。第三栅极区域在第一和第二栅极区域之间延伸。器件还包括在导电栅极和衬底之间延伸并且还包括与第一，第二和第三栅极区域电连通的硅化物区域的栅极电介质。这些方法包括制造器件的方法。

27. 发明申请

US20160356740A1 PROTECTED SENSOR FIELD EFFECT TRANSISTORS 有权
公开(公告)号：US20160356740A1
公开(公告)日：2016-12-08
申请号：US14731795
申请日：2015-06-05
申请人： Patrice M. Parris , Weize Chen , Richard J. de Souza , Jose Fernandez Villasenor , Md M. Hoque , David E. Niewolny , Raymond M. Roop
发明人： Patrice M. Parris , Weize Chen , Richard J. de Souza , Jose Fernandez Villasenor , Md M. Hoque , David E. Niewolny , Raymond M. Roop
IPC分类号： G01N27/414 , B01L3/00
CPC分类号： G01N27/4148 , B01L3/5027 , B01L3/502715 , B01L3/50273 , B01L2200/10 , B01L2200/12 , B01L2300/04 , B01L2300/041 , B01L2300/0645 , B01L2300/0887 , B01L2400/0415 , B01L2400/0418 , G01N27/28 , G01N27/414 , H01L21/67259 , H01L29/4933 , H01L29/66431 , H01L29/66462 , H01L29/7833 , H01L31/119
摘要： Protected sensor field effect transistors (SFETs). The SFETs include a semiconductor substrate, a field effect transistor, and a sense electrode. The SFETs further include an analyte-receiving region that is supported by the semiconductor substrate, is in contact with the sense electrode, and is configured to receive an analyte fluid. The analyte-receiving region is at least partially enclosed. In some embodiments, the analyte-receiving region can be an enclosed analyte channel that extends between an analyte inlet and an analyte outlet. In these embodiments, the enclosed analyte channel extends such that the analyte inlet and the analyte outlet are spaced apart from the sense electrode. In some embodiments, the SFETs include a cover structure that at least partially encloses the analyte-receiving region and is formed from a cover material that is soluble within the analyte fluid. The methods include methods of manufacturing the SFETs.

28. 发明授权

US09330961B2 Stacked protection devices and related fabrication methods 有权
标题翻译：堆叠式保护装置及相关制造方法
公开(公告)号：US09330961B2
公开(公告)日：2016-05-03
申请号：US14034213
申请日：2013-09-23
申请人： Weize Chen , Patrice M. Parris
发明人： Weize Chen , Patrice M. Parris
IPC分类号： H01L21/768 , H01L27/02
CPC分类号： H01L21/768 , H01L27/0248 , H01L27/0255 , H01L27/0259
摘要： Protection device structures and related fabrication methods and devices are provided. An exemplary device includes a first interface, a second interface, a first protection circuitry arrangement coupled to the first interface, and a second protection circuitry arrangement coupled between the first protection circuitry arrangement and the second interface. The second protection circuitry arrangement includes a first transistor and a diode coupled to the first transistor, wherein the first transistor and the diode are configured electrically in series between the first protection circuitry arrangement and the second interface.
摘要翻译：提供保护装置结构及相关制造方法和装置。示例性装置包括第一接口，第二接口，耦合到第一接口的第一保护电路装置，以及耦合在第一保护电路装置和第二接口之间的第二保护电路装置。第二保护电路装置包括耦合到第一晶体管的第一晶体管和二极管，其中第一晶体管和二极管被串联配置在第一保护电路装置和第二接口之间。

29. 发明申请

US20160099349A1 SEMICONDUCTOR DEVICE WITH NON-ISOLATED POWER TRANSISTOR WITH INTEGRATED DIODE PROTECTION 有权
标题翻译：具有集成二极管保护功能的非隔离型功率晶体管的半导体器件
公开(公告)号：US20160099349A1
公开(公告)日：2016-04-07
申请号：US14507063
申请日：2014-10-06
申请人： Patrice M. Parris , Hubert M. Bode , Weize Chen , Richard J. DeSouza , Andreas Laudenbach , Kurt U. Neugebauer
发明人： Patrice M. Parris , Hubert M. Bode , Weize Chen , Richard J. DeSouza , Andreas Laudenbach , Kurt U. Neugebauer
IPC分类号： H01L29/78 , H01L29/66 , H01L29/08 , H01L27/07
CPC分类号： H01L29/7823 , H01L21/761 , H01L27/0255 , H01L27/0727 , H01L29/0619 , H01L29/0623 , H01L29/063 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/36 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.
摘要翻译：在非隔离功率晶体管器件和电子设备中配置有一个或多个集成击穿保护二极管的半导体器件，以及用于制造器件的方法。

30. 发明授权

US09214542B2 Semiconductor device with integrated electrostatic discharge (ESD) clamp 有权
标题翻译：具有集成静电放电（ESD）钳位的半导体器件
公开(公告)号：US09214542B2
公开(公告)日：2015-12-15
申请号：US13792748
申请日：2013-03-11
申请人： Weize Chen , Patrice M. Parris
发明人： Weize Chen , Patrice M. Parris
IPC分类号： H01L29/78 , H01L21/82 , H01L27/088 , H01L27/02
CPC分类号： H01L27/0259 , H01L21/76224 , H01L21/76895 , H01L27/027 , H01L27/0711 , H01L27/0722 , H01L29/0623 , H01L29/0649 , H01L29/0653 , H01L29/1083 , H01L29/1087 , H01L29/6625 , H01L29/66659 , H01L29/66681 , H01L29/78 , H01L29/7835
摘要： A device includes a substrate, a body region in the substrate and having a first conductivity type, source and drain regions in the substrate, having a second conductivity type, and spaced from one another to define a conduction path that passes through the body region, a doped isolating region in the substrate, having the second conductivity type, and configured to surround a device area in which the conduction path is disposed, an isolation contact region in the substrate, having the second conductivity type, and electrically coupled to the doped isolating region to define a collector region of a bipolar transistor, and first and second contact regions within the body region, having the first and second conductivity types, respectively, and configured to define a base contact region and an emitter region of the bipolar transistor, respectively.
摘要翻译：一种器件包括衬底，衬底中的体区，并且具有第一导电类型，衬底中的源区和漏区，具有第二导电类型，并且彼此间隔开以限定通过体区的导电路径，衬底中的掺杂隔离区域，具有第二导电类型，并且被配置为围绕其中设置导电路径的器件区域，具有第二导电类型的衬底中的隔离接触区域，并且电耦合到掺杂隔离层区域以限定双极晶体管的集电极区域，以及体区内的第一和第二接触区域，分别具有第一和第二导电类型，并且被配置为分别限定双极晶体管的基极接触区域和发射极区域。

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