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21. 发明授权

US07199032B2 Metal silicide induced lateral excessive encroachment reduction by silicon <110> channel stuffing 有权
标题翻译：金属硅化物通过硅<110>通道填料引起横向过度侵蚀
公开(公告)号：US07199032B2
公开(公告)日：2007-04-03
申请号：US10903319
申请日：2004-07-30
申请人： Duofeng Yue , Peijun J. Chen , Sue Ellen Crank , Thomas D. Bonifield , Jiong-Ping Lu , Jie-Jie Xu
发明人： Duofeng Yue , Peijun J. Chen , Sue Ellen Crank , Thomas D. Bonifield , Jiong-Ping Lu , Jie-Jie Xu
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/28518 , H01L29/6659
摘要： The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises implanting small atoms into an nMOS semiconductor substrate (130) to a depth (132) no greater than about 30 nanometers into the nMOS semiconductor substrate. The method further comprises depositing a transition metal layer (400) over the nMOS semiconductor substrate. The transition metal layer and the nMOS semiconductor substrate are reacted to form the metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit (700).
摘要翻译：本发明提供一种制造用于半导体器件（110）的金属硅化物电极（100）的方法。该方法包括将小原子注入nMOS半导体衬底（130）至nMOS半导体衬底中不大于约30纳米的深度（132）。该方法还包括在nMOS半导体衬底上沉积过渡金属层（400）。使过渡金属层和nMOS半导体衬底反应以形成金属硅化物电极。本发明的其它方面包括制造集成电路（700）的方法。

22. 发明授权

US06967349B2 Method for fabricating a multi-level integrated circuit having scatterometry test structures stacked over same footprint area 有权
标题翻译：一种制造具有堆叠在同一占地面积上的散射测试结构的多级集成电路的方法
公开(公告)号：US06967349B2
公开(公告)日：2005-11-22
申请号：US10251498
申请日：2002-09-20
申请人： Thomas D. Bonifield , Vladimir A. Ukraintsev
发明人： Thomas D. Bonifield , Vladimir A. Ukraintsev
IPC分类号： G03F7/20 , H01L29/04
CPC分类号： G03F7/70625
摘要： The present invention describes a plurality of scatterometry test structures for use in process control during fabrication of a semiconductor wafer having multilevel integrated circuit chips, many of said levels having a feature size of a critical dimension. The scatterometry test structures on the wafer are at each level, suitable to measure critical dimensions. The second level and each subsequent level of the test structures are located to fit into the same footprint area as the first level.
摘要翻译：本发明描述了在具有多级集成电路芯片的半导体晶片的制造期间用于过程控制的多个散射测试结构，许多所述级具有临界尺寸的特征尺寸。晶圆上的散射测试结构位于每个级别，适合于测量临界尺寸。测试结构的第二级和每个后续级别被定位成适合与第一级相同的占用面积。

23. 发明授权

US5055423A Planarized selective tungsten metallization system 失效
标题翻译：平面选择性钨金属化系统
公开(公告)号：US5055423A
公开(公告)日：1991-10-08
申请号：US383304
申请日：1989-07-18
申请人： Gregory C. Smith , Thomas D. Bonifield
发明人： Gregory C. Smith , Thomas D. Bonifield
IPC分类号： H01L21/3205 , H01L21/768
CPC分类号： H01L21/32051 , H01L21/76801 , H01L21/76816 , H01L21/76829 , H01L21/76879 , H01L21/76807
摘要： In an improved selection tungsten metallization system, a plurality of orifices (20) are cut into a first level dielectric layer (18). A nucleation layer (52), preferably Ti-W alloy, is then formed in each orifice (20) and on the outer surface of the first dielectric layer (18) in a second-level metallization pattern. A second dielectric layer (30) is deposited over the first dielectric layer (18) and the nucleation layer (52), and a reverse second level metallization pattern is used to etch slots (58) back down to the nucleation layers (52) and into orifices (20). Thereafter, tungsten is deposited by selective CVD to fill the first level orifices (20) and the second level slots (58) until the upper surfaces (62) of the tungsten conductors (60) are substantially coplanar with the upper surface (38) of the second dielectric layer (30).
摘要翻译：在改进的选择钨金属化系统中，将多个孔（20）切割成第一级介电层（18）。然后在每个孔口（20）中以第二级金属化图案形成第一介电层（18）的外表面上的成核层（52），优选Ti-W合金。沉积在第一介电层（18）和成核层（52）上的第二介电层（30），并且使用反向第二级金属化图案来蚀刻回到成核层（52）的槽（58）和进入孔（20）。此后，通过选择性CVD沉积钨以填充第一级孔（20）和第二级槽（58），直到钨导体（60）的上表面（62）与上表面（38）的上表面（38）基本共面第二电介质层（30）。

24. 发明授权

US08912076B2 Crack deflector structure for improving semiconductor device robustness against saw-induced damage 有权
标题翻译：裂纹偏转器结构，用于提高半导体器件对锯损坏的鲁棒性
公开(公告)号：US08912076B2
公开(公告)日：2014-12-16
申请号：US12613175
申请日：2009-11-05
申请人： Jeffrey Alan West , Thomas D. Bonifield , Basab Chatterjee
发明人： Jeffrey Alan West , Thomas D. Bonifield , Basab Chatterjee
IPC分类号： H01L23/58 , H01L23/00
CPC分类号： H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal.
摘要翻译：一种集成电路，其包含将集成电路的内部区域与紧邻集成电路外部的划片线分隔开的裂纹偏转划线密封件及其形成方法。裂纹偏转划线密封件包括连续金属层和连续金属层之间的连续接触和连续通孔。连续金属层不延伸经过连续接触和连续通孔。连续接触和连续的通孔从划线密封的划线侧的下面的连续金属层的边缘凹陷，在划线密封件上提供成角度的外表面，其可以期望地终止裂纹扩展或将裂纹传播向上偏转到顶部表面划线或裂纹偏转划痕。

25. 发明申请

US20120193814A1 IC Device Having Low Resistance TSV Comprising Ground Connection 有权
标题翻译：具有低电阻TSV的IC器件包括接地连接
公开(公告)号：US20120193814A1
公开(公告)日：2012-08-02
申请号：US13444508
申请日：2012-04-11
申请人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
发明人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
IPC分类号： H01L23/48
CPC分类号： H01L23/49513 , H01L23/481 , H01L23/49575 , H01L24/16 , H01L24/30 , H01L24/33 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/0557 , H01L2224/05647 , H01L2224/16145 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73204 , H01L2224/73207 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/04953 , H01L2924/078 , H01L2924/14 , H01L2924/1461 , H01L2924/30107 , H01L2924/00 , H01L2924/01083 , H01L2924/0665 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/013
摘要： A semiconductor device includes an integrated circuit (IC) die including a substrate, and a plurality of through substrate via (TSV) that extends through the substrate to a protruding integral tip and which is partially covered with a dielectric liner and partially exposed from the dielectric liner. A metal layer is on the bottom surface of the IC die die physically connecting the plurality of TSVs and physically and electrically connected to connecting the first metal protruding tips of TSVs.
摘要翻译：半导体器件包括：集成电路（IC）管芯，其包括衬底;以及多个通过衬底通孔（TSV），其穿过衬底延伸到突出的整体尖端，并且部分地被电介质衬垫覆盖并部分地从电介质暴露衬垫。金属层位于IC芯片的底表面上，物理连接多个TSV，并物理和电连接到连接TSV的第一金属突出尖端。

26. 发明授权

US07968974B2 Scribe seal connection 有权
标题翻译：划痕密封连接
公开(公告)号：US07968974B2
公开(公告)日：2011-06-28
申请号：US12201394
申请日：2008-08-29
申请人： Scott R. Summerfelt , Thomas D. Bonifield
发明人： Scott R. Summerfelt , Thomas D. Bonifield
IPC分类号： H01L23/02
CPC分类号： H01L23/585 , H01L23/562 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： A feedthrough in an IC scribe seal is disclosed. The feedthrough is structured to maintain isolation of components in the IC from mechanical damage and chemical impurities introduced during fabrication and assembly operations. A conductive structure penetrates the scribe seal, possibly in more than one location, connecting an interior region to an exterior region. A feedthrough vertical seal surrounds the conductive element in the IC and connects to the scribe seal. A horizontal diffusion barrier connects to the scribe seal and the feedthrough vertical seal. The feedthrough vertical seal, the horizontal diffusion barrier and the IC substrate form a continuous barrier to chemical impurities around the conductive element in the interior region. The conductive structure includes any combination of a doped region in an active area, an MOS transistor gate layer, and one or more interconnect metal layers. The feedthrough is compatible with aluminum and copper interconnect metallization.
摘要翻译：公开了IC划片印章中的馈通。馈通的结构是保持IC中组件的隔离，防止在制造和组装操作过程中引入的机械损伤和化学杂质。导电结构可能在不止一个位置上穿过划线密封，将内部区域连接到外部区域。馈通垂直密封件围绕IC中的导电元件并连接到划线密封件。水平扩散屏障连接到划线密封和馈通垂直密封。馈通垂直密封件，水平扩散阻挡层和IC基板在内部区域内对导电元件周围的化学杂质形成连续的屏障。导电结构包括有源区域中的掺杂区域，MOS晶体管栅极层和一个或多个互连金属层的任何组合。馈通与铝和铜互连金属化兼容。

27. 发明授权

US5444018A Metallization process for a semiconductor device 失效
标题翻译：半导体器件的金属化工艺
公开(公告)号：US5444018A
公开(公告)日：1995-08-22
申请号：US135863
申请日：1993-10-13
申请人： Dennis J. Yost , Thomas D. Bonifield , Roc Blumenthal
发明人： Dennis J. Yost , Thomas D. Bonifield , Roc Blumenthal
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L23/522 , H01L21/441
CPC分类号： H01L21/28512 , H01L21/76895 , H01L2924/0002
摘要： A contact for a semiconductor device has a via extending through a dielectric and collimated titanium in the via. Depositing titanium by collimation places sufficient metal into high aspect ratio contacts to make good electrical connection. The collimated titanium may be reacted in a nitrogen containing ambient to form a titanium silicide layer at the bottom of the contact and a titanium nitride layer over the titanium silicide layer. The titanium silicide layer provides good electrical contact to a device in a silicon semiconductor substrate and lowers contact resistance. Tungsten may be deposited over the colliminated titanium to form a conductor layer. The titanium nitride layer provides a sticking layer for the tungsten. The contact structure and the method are useful in high aspect ratio contacts present in VLSI multilevel interconnected devices such as dynamic random access memories.
摘要翻译：用于半导体器件的触点具有延伸穿过通孔中的电介质和准直钛的通孔。通过准直沉积钛将足够的金属置入高纵横比触点，以实现良好的电连接。准直的钛可以在含氮环境中反应以在接触的底部形成硅化钛层，并且在钛硅化物层上方形成氮化钛层。硅化钛层与硅半导体衬底中的器件提供良好的电接触并降低接触电阻。钨可以沉积在准直钛上以形成导体层。氮化钛层为钨提供粘附层。接触结构和方法对于存在于VLSI多级互连设备（例如动态随机存取存储器）中的高纵横比触点是有用的。

28. 发明授权

US5405807A Semiconductor hybrids and method of making same 失效
标题翻译：半导体混合物及其制备方法
公开(公告)号：US5405807A
公开(公告)日：1995-04-11
申请号：US042384
申请日：1993-03-31
申请人： James C. Baker , Emily A. Groves , Douglas Paradis , Charles P. Monaghan , Barry Lanier , Thomas D. Bonifield , Julie S. England
发明人： James C. Baker , Emily A. Groves , Douglas Paradis , Charles P. Monaghan , Barry Lanier , Thomas D. Bonifield , Julie S. England
IPC分类号： H01L21/3105 , H01L21/60
CPC分类号： H01L21/31051
摘要： A method of making a hybrid semiconductor device and the device comprising providing a semiconductor substrate having electrical devices therein, providing a first resilient layer of electrically insulating material over the substrate which can be disposed directly onto the substrate with a substantially planar exposed surface, providing a second resilient layer of electrically insulating material over the first resilient layer which can be disposed directly onto the first layer with a substantially planar exposed surface, the second layer having a relatively resilient state and a rigid state, providing resilient standoff from the third resilient layer at spaced locations on the second layer by removing predetermined portions of the third layer, securing a semiconductor superstrate to the semiconductor device, forming electrical devices on the superstrate, and then connecting the electrical devices on the superstrate to the electrical devices on the substrate.
摘要翻译：一种制造混合半导体器件的方法，所述器件包括提供其中具有电子器件的半导体衬底，在衬底上提供电绝缘材料的第一弹性层，所述第一弹性层可以直接布置在具有基本平坦的暴露表面的衬底上，从而提供所述第一弹性层上的电绝缘材料的第二弹性层可以直接布置在具有基本上平坦的暴露表面的第一层上，所述第二层具有相对弹性状态和刚性状态，从第三弹性层提供弹性支座通过去除第三层的预定部分，将半导体衬底固定到半导体器件上，在衬底上形成电器件，然后将衬底上的电子器件连接到衬底上的电气器件上，从而在第二层上的间隔位置。

29. 发明授权

US5244839A Semiconductor hybrids and method of making same 失效
标题翻译：半导体混合物及其制备方法
公开(公告)号：US5244839A
公开(公告)日：1993-09-14
申请号：US717149
申请日：1991-06-18
申请人： James C. Baker , Emily A. Groves , Douglas Paradis , Charles P. Monaghan , Barry Lanier , Thomas D. Bonifield , Julie S. England , Glenn A. Cerny
发明人： James C. Baker , Emily A. Groves , Douglas Paradis , Charles P. Monaghan , Barry Lanier , Thomas D. Bonifield , Julie S. England , Glenn A. Cerny
IPC分类号： H01L21/3105
CPC分类号： H01L21/31051
摘要： A method of making a hybrid semiconductor device and the device comprising providing a semiconductor substrate having electrical devices therein, providing a first resilient layer of electrically insulating material over the substrate which can be disposed directly onto the substrate with a substantially planar exposed surface, providing a second resilient layer of electrically insulating material over the first resilient layer which can be disposed directly onto the first layer with a substantially planar exposed surface, the second layer having a relatively resilient state and a rigid state, providing resilient standoff from the third resilient layer at spaced locations on the second layer by removing predetermined portions of the third layer, securing a semiconductor superstrate to the semiconductor device, forming electrical devices on the superstrate, and then connecting the electrical devices on the superstrate to the electrical devices on the substrate.
摘要翻译：一种制造混合半导体器件的方法，所述器件包括提供其中具有电子器件的半导体衬底，在衬底上提供电绝缘材料的第一弹性层，所述第一弹性层可以直接布置在具有基本平坦的暴露表面的衬底上，从而提供所述第一弹性层上的电绝缘材料的第二弹性层可以直接布置在具有基本上平坦的暴露表面的第一层上，所述第二层具有相对弹性状态和刚性状态，从第三弹性层提供弹性支座通过去除第三层的预定部分，将半导体衬底固定到半导体器件上，在衬底上形成电器件，然后将衬底上的电子器件连接到衬底上的电气器件上，从而在第二层上的间隔位置。

30. 发明授权

US4758305A Contact etch method 失效
标题翻译：接触蚀刻法
公开(公告)号：US4758305A
公开(公告)日：1988-07-19
申请号：US838965
申请日：1986-03-11
申请人： Thomas D. Bonifield , Vic B. Marriott , Rhett B. Jucha , Monte A. Douglas
发明人： Thomas D. Bonifield , Vic B. Marriott , Rhett B. Jucha , Monte A. Douglas
IPC分类号： H01L21/28 , H01L21/027 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/768 , H01L21/8234 , H01L27/088 , B44C1/22 , B29C37/00 , C03C15/00 , C03C25/06
CPC分类号： H01L21/31116 , H01L21/0274 , H01L21/31144 , H01L21/76804 , Y10S438/948 , Y10S438/952
摘要： A method for patterning small-geometry contacts with sloped sidewalls in integrated circuit fabrication. A multilayer resist process is used, and the spacer layer is undercut by overexposure and overdevelopment at the pattern transfer stage. This provides a cantilever etch mask structure, without the need to use any hardmask layers.
摘要翻译：在集成电路制造中用于图形具有倾斜侧壁的小几何接触的方法。使用多层抗蚀剂工艺，并且间隔层在图案转移阶段被过度曝光和过度发展所削弱。这提供了悬臂蚀刻掩模结构，而不需要使用任何硬掩模层。

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