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21. 发明申请

US20070046323A1 Control circuitry for power gating virtual power supply rails at differing voltage potentials 失效
公开(公告)号：US20070046323A1
公开(公告)日：2007-03-01
申请号：US11211954
申请日：2005-08-25
申请人： Jente Kuang , Hung Ngo , Kevin Nowka
发明人： Jente Kuang , Hung Ngo , Kevin Nowka
IPC分类号： H03K17/16
CPC分类号： H03K19/0016
摘要： A single-stage level shifting circuit is used to interface control signals across the boundary between voltage domains with differing positive or ground voltage potentials Asserted states are determined by the difference between the positive voltages potentials and the ground potentials. A lower positive power supply potential is not used to turn OFF PFET coupled to a higher positive power supply potential. Likewise a higher ground power supply potential is not used to turn OF NFETs coupled to a power domain where is significant ground shift. The single stage level shifting circuit has keeper devices that hold asserted states using voltages within the power gated domain.

22. 发明申请

US20070040584A1 Dual-gate dynamic logic circuit with pre-charge keeper 有权
公开(公告)号：US20070040584A1
公开(公告)日：2007-02-22
申请号：US11204401
申请日：2005-08-16
申请人： Hung Ngo , Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
发明人： Hung Ngo , Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.

23. 发明申请

US20060082389A1 Dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control 失效
标题翻译：用于通过单独的时钟和输出级控制来减少泄漏功耗的动态逻辑电路装置和方法
公开(公告)号：US20060082389A1
公开(公告)日：2006-04-20
申请号：US10992488
申请日：2004-11-18
申请人： Hung Ngo , Jente Kuang , Harmander Deogun , AJ Kleinosowski
发明人： Hung Ngo , Jente Kuang , Harmander Deogun , AJ Kleinosowski
IPC分类号： H03K19/096
CPC分类号： H03K19/0016 , H03K19/0966
摘要： A dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control reduces power consumption of processors and other systems incorporating dynamic circuits. The power control signal may be a delayed version of the logic clock and turns on the output inverter foot device after the dynamic node has had sufficient time to evaluate, providing a fast evaluate time and reducing leakage through the inverter input when the foot device is off. Alternatively, a coarsely timed static power control signal may be used to control the inverter foot devices. The drains of the inverter foot devices can be commonly connected across multiple circuits, reducing the foot device total area.
摘要翻译：用于通过单独的时钟和输出级控制减少泄漏功率消耗的动态逻辑电路装置和方法降低了处理器和结合动态电路的其他系统的功耗。功率控制信号可以是逻辑时钟的延迟版本，并且在动态节点有足够的时间评估之后接通输出的反相器脚装置，当脚装置关闭时提供快速的评估时间并减少逆变器输入的泄漏。或者，可以使用粗定时静态功率控制信号来控制逆变器脚装置。逆变器脚踏装置的排水管可以通过多个回路共同连接，减少了脚踏装置总面积。

24. 发明申请

US20060076991A1 LOW POWER HIGH FREQUENCY PHASE DETECTOR 失效
标题翻译：低功率高频相位检测器
公开(公告)号：US20060076991A1
公开(公告)日：2006-04-13
申请号：US10960608
申请日：2004-10-07
申请人： Seung-Moon Yoo , Hung Ngo
发明人： Seung-Moon Yoo , Hung Ngo
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03D13/004 , H03L7/0812 , H03L7/0891
摘要： A phase detector employs a modified logic gate in conjunction with a set/reset latch to make a phase detector that generates control outputs for use in increasing and decreasing the delay in a delay circuit in the path of a feedback clock generated by delaying a reference clock. The delay circuit provides a controllable delay from less than to greater than one clock cycle of the reference clock. The phase detector generates an up control (UP) signal for increasing delay when the feedback clock leads the reference clock and a down control (DN) signal for decreasing delay when the feedback clock lags the reference clock. The UP signal and DN signal are updated each clock cycle when the leading clock edge makes a transition.
摘要翻译：相位检测器使用修改的逻辑门与设置/复位锁存器相结合，以产生相位检测器，该相位检测器产生控制输出，用于增加和减少在延迟参考时钟产生的反馈时钟的路径中的延迟电路中的延迟。延迟电路从参考时钟的小于一个时钟周期提供可控延迟。当反馈时钟引导参考时钟时，相位检测器产生上调控制（UP）信号，用于增加延迟，当反馈时钟延迟参考时钟时，降低控制（DN）信号以减小延迟。当前沿时钟沿进行转换时，每个时钟周期更新UP信号和DN信号。

25. 发明申请

US20060035531A1 High speed, high signal integrity electrical connectors 失效
标题翻译：高速，高信号完整性电连接器
公开(公告)号：US20060035531A1
公开(公告)日：2006-02-16
申请号：US10918169
申请日：2004-08-13
申请人： Hung Ngo
发明人： Hung Ngo
IPC分类号： H01R13/514
CPC分类号： H01R13/6658 , H01R12/721 , H01R13/514 , H01R13/516 , H01R13/6215
摘要： An electrical connector may include a connector housing and a terminal tray. The terminal tray may include a tray body having a latch extending therefrom. The connector housing may define a latch receiving window. The latch and latch receiving window may be disposed such that the latch engages the latch receiving window only when the terminal tray is received in the housing in a preferred orientation. The terminal tray may include an electrically conductive contact having a board receiving end adapted to receive a printed circuit board and to exert sufficient pressure on the printed circuit board to retain the printed circuit board between the contact and the tray body. The connector may also include a plurality of cables bundled by a band, such as double-sided tape, such that respective portions of the cables are restrained from movement relative to one another.
摘要翻译：电连接器可以包括连接器壳体和端子托盘。端子盘可以包括具有从其延伸的闩锁的托盘主体。连接器壳体可以限定闩锁接收窗口。闩锁和闩锁接收窗口可以被布置成使得仅当终端托盘以优选的方向容纳在壳体中时，闩锁接合闩锁接收窗口。端子托盘可以包括导电触点，其具有适于接收印刷电路板的板接收端并且在印刷电路板上施加足够的压力以将印刷电路板保持在接触件和托盘主体之间。连接器还可以包括由诸如双面胶带的带捆绑的多个电缆，使得电缆的相应部分被限制为相对于彼此移动。

26. 发明申请

US20050156637A1 Methods and arrangements for a low power phase-locked loop 失效
公开(公告)号：US20050156637A1
公开(公告)日：2005-07-21
申请号：US11037790
申请日：2005-01-18
申请人： Hung Ngo
发明人： Hung Ngo
IPC分类号： H03B19/00 , H03L7/06 , H03L7/099 , H03L7/18 , H03L7/183
CPC分类号： H03L7/183 , H03L7/0995 , H03L7/18
摘要： Methods and arrangements for a low power, phase-locked loop (PLL) are disclosed. Embodiments include a multi-phase oscillator like a voltage-controlled oscillator (VCO) to generate multiple phases of a clock signal. The multiple phases are then combined to generate a single clock signal having a frequency substantially equivalent to the number of phases multiplied by the frequency of the clock signal generated by the multi-phase VCO. Advantageously, embodiments can generate clock signals having frequencies that are multiples of the frequency generated by the VCO, reducing the power consumed by the VCO to produce a clock signal having the same frequency as a clock signal generated by a single phase VCO. Further, the achievable frequency for the VCO is increased. In many embodiments, a high speed, n-bit frequency divider that implements a pulse latch facilitates the use of the multi-phase VCO to generate the very high frequency clock signals.

27. 发明申请

US20050127961A1 Methods and arrangements for a low power phase-locked loop 失效
公开(公告)号：US20050127961A1
公开(公告)日：2005-06-16
申请号：US10733933
申请日：2003-12-10
申请人： Hung Ngo
发明人： Hung Ngo
IPC分类号： H03B19/00 , H03L7/06 , H03L7/099 , H03L7/18 , H03L7/183
CPC分类号： H03L7/183 , H03L7/0995 , H03L7/18
摘要： Methods and arrangements for a low power, phase-locked loop (PLL) are disclosed. Embodiments include a multi-phase oscillator like a voltage-controlled oscillator (VCO) to generate multiple phases of a clock signal. The multiple phases are then combined to generate a single clock signal having a frequency substantially equivalent to the number of phases multiplied by the frequency of the clock signal generated by the multi-phase VCO. Advantageously, embodiments can generate clock signals having frequencies that are multiples of the frequency generated by the VCO, reducing the power consumed by the VCO to produce a clock signal having the same frequency as a clock signal generated by a single phase VCO. Further, the achievable frequency for the VCO is increased. In many embodiments, a high speed, n-bit frequency divider that implements a pulse latch facilitates the use of the multi-phase VCO to generate the very high frequency clock signals.

28. 发明申请

US20050127950A1 FEEDFORWARD LIMITED SWITCH DYNAMIC LOGIC CIRCUIT 失效
标题翻译： FEEDFORWARD有限公司开关动态逻辑电路
公开(公告)号：US20050127950A1
公开(公告)日：2005-06-16
申请号：US10733950
申请日：2003-12-11
申请人： Hung Ngo
发明人： Hung Ngo
IPC分类号： H03K3/012 , H03K3/356 , H03K19/096
CPC分类号： H03K3/356121 , H03K3/012 , H03K19/0963
摘要： The N channel field effect transistor (NFET) of the inverting output stage of a LSDL gate is split into a large NFET and a small NFET. The large NFET is coupled to a feedforward pulse so that it is turned ON only when the inverting output is a logic one. When the inverting output is a logic one, another inverting stage turns ON if the dynamic node evaluates to a logic zero. The dynamic node is inverted and coupled to the large NFET on the inverting output stage thus quickly pulling the inverting output to a logic zero. The small NFET is turned ON as a keeper device through the normal logic path. If the inverting data output is a logic zero the feedforward pulse is not generated. By making the largest NFET a pulsed device the other FETs are reduced in size resulting in leakage and switching power savings.
摘要翻译： LSDL栅极的反相输出级的N沟道场效应晶体管（NFET）分为大NFET和小NFET。大的NFET耦合到前馈脉冲，使得仅当反相输出为逻辑1时才将其导通。当反相输出为逻辑1时，如果动态节点评估为逻辑0，则另一个反相级将变为ON。动态节点被反相并耦合到反相输出级上的大NFET，从而快速地将反相输出拉至逻辑0。小型NFET通过正常逻辑路径作为保持器装置接通。如果反相数据输出为逻辑0，则不产生前馈脉冲。通过使最大的NFET是脉冲器件，其他FET的尺寸减小，从而导致泄漏和开关功率节省。

29. 发明申请

US20070275586A1 Connectors and contacts for transmitting electrical power 有权
标题翻译：用于传输电力的连接器和触点
公开(公告)号：US20070275586A1
公开(公告)日：2007-11-29
申请号：US11441856
申请日：2006-05-26
申请人： Hung Ngo
发明人： Hung Ngo
IPC分类号： H01R13/28
CPC分类号： H01R13/28 , H01R12/7088
摘要： A connector system includes a first connector, and a second connector that mates with the first connector. The same type of power contact is used in the first and second connectors.
摘要翻译：连接器系统包括第一连接器和与第一连接器配合的第二连接器。在第一和第二连接器中使用相同类型的电源触点。

30. 发明申请

US20070197063A1 ELECTRICAL CONNECTORS HAVING POWER CONTACTS WITH ALIGNMENT AND/OR RESTRAINING FEATURES 有权
标题翻译：具有对准和/或限制功能的电源触点的电气连接器
公开(公告)号：US20070197063A1
公开(公告)日：2007-08-23
申请号：US11358168
申请日：2006-02-21
申请人： Hung Ngo , Wilfred Swain
发明人： Hung Ngo , Wilfred Swain
IPC分类号： H01R13/648
CPC分类号： H01R12/7088 , H01R12/724 , H01R12/727
摘要： Preferred embodiments of power contacts have alignment features that can maintain conductors of the power contacts in a state of alignment during and after insertion of the power contacts into a housing.
摘要翻译：功率触点的优选实施例具有对准特征，其可以在电力触头插入壳体期间和之后将电力触头的导体保持在对准状态。

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