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21. 发明授权

US5408114A Semiconductor memory device having cylindrical capacitor and manufacturing method thereof 失效
标题翻译：具有圆柱形电容器的半导体存储器件及其制造方法
公开(公告)号：US5408114A
公开(公告)日：1995-04-18
申请号：US70521
申请日：1993-06-03
申请人： Mitsuya Kinoshita , Tatsuo Okamoto , Hideaki Arima , Atsushi Hachisuka
发明人： Mitsuya Kinoshita , Tatsuo Okamoto , Hideaki Arima , Atsushi Hachisuka
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/68
CPC分类号： H01L27/10852 , H01L27/10817
摘要： The semiconductor memory device includes a semiconductor substrate 1 having a conductive layer 6 formed on its main surface. Word lines 4c, 4d and a bit line 11 is formed on the semiconductor substrate. Insulating films 8, 12 are provided to cover the word lines 4c, 4d and the bit line 11. A barrier film 14 is provided on the insulating films 8, 12 for protecting the insulating films 8, 12 from etchant. A cylindrical storage node 170 is electrically connected to the conductive layer 6. The cylindrical storage node 170 includes a bottom conductive portion 17a and a sidewall conductive portion 17b. An outer surface of the storage node 170 is covered with a capacitor insulating film 112. The outer surface of the cylindrical storage node 170 is covered with a cell plate 22, with the capacitor insulating film 112 interposed therebetween.
摘要翻译：半导体存储器件包括在其主表面上形成有导电层6的半导体衬底1。字线4c，4d和位线11形成在半导体衬底上。提供绝缘膜8,12以覆盖字线4c，4d和位线11.隔离膜14设置在绝缘膜8,12上，用于保护绝缘膜8,12免受蚀刻。圆柱形存储节点170电连接到导电层6.圆柱形存储节点170包括底部导电部分17a和侧壁导电部分17b。存储节点170的外表面被电容器绝缘膜112覆盖。圆筒形存储节点170的外表面被电池板22覆盖，电容器绝缘膜112插入其间。

22. 发明授权

US5323348A Semiconductor memory device having multiple memory arrays and including redundancy circuit for repairing a faulty bit 失效
标题翻译：具有多个存储器阵列并且包括用于修复故障位的冗余电路的半导体存储器件
公开(公告)号：US5323348A
公开(公告)日：1994-06-21
申请号：US767316
申请日：1991-09-30
申请人： Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Mitsuya Kinoshita , Makoto Suwa , Shigeru Kikuda , Michihiro Yamada
发明人： Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Mitsuya Kinoshita , Makoto Suwa , Shigeru Kikuda , Michihiro Yamada
IPC分类号： G11C11/401 , G11C11/409 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/848
摘要： Column repairing circuits 7a, 7b for repairing a DRAM in which there are defective memory cells in two columns are disclosed. The connection state of switching elements or circuits 51-5n, 61-6n, 71-7 (n+1), 81-8 (n+1) is determined as illustrated by appropriately disconnecting fuses in fuse links provided respectively in circuits 7a, 7b. Accordingly, column selecting lines Y2a and Y (n+1) b in memory array blocks 891a, 891b are not activated. The two repairing circuits 7a, 7b are provided spaced apart from each other on a semiconductor substrate, so that excessive concentration of fuse elements and switching elements or circuits is prevented.
摘要翻译：公开了用于修复其中存在两列不良存储器单元的DRAM的列修复电路7a，7b。开关元件或电路51-5n，61-6n，71-7（n + 1），81-8（n + 1）的连接状态通过适当地断开分别设置在电路7a， 7b。因此，存储器阵列块891a，891b中的列选择线Y2a和Y（n + 1）b未被激活。两个修复电路7a，7b在半导体衬底上彼此间隔开设置，从而防止了熔丝元件和开关元件或电路的过度集中。

23. 发明授权

US06845056B2 Semiconductor memory device with reduced power consumption 失效
标题翻译：具有降低功耗的半导体存储器件
公开(公告)号：US06845056B2
公开(公告)日：2005-01-18
申请号：US10325827
申请日：2002-12-23
申请人： Mitsuya Kinoshita
发明人： Mitsuya Kinoshita
IPC分类号： G11C11/407 , G11C8/08 , G11C8/12 , G11C11/406 , G11C11/408 , G11C11/409 , G11C11/4091 , G11C8/00
CPC分类号： G11C11/40611 , G11C8/08 , G11C8/12 , G11C11/406 , G11C11/4085 , G11C11/4091 , G11C2207/005
摘要： In a semiconductor memory device having a shared sense amplifier configuration, a control circuit outputting a bit line isolation signal latches a block selection signal in accordance with a change in a trigger signal. With this configuration, when the same block is selected, no change is caused in the bit line isolation signal. Consequently, charge/discharge current is reduced, and power consumption is reduced. Since a specific bit in a refresh counter is not used, unlike the conventional technique, the design changes little even in the case of changing the configuration of an array.
摘要翻译：在具有共享读出放大器配置的半导体存储器件中，输出位线隔离信号的控制电路根据触发信号的变化来锁存块选择信号。利用该配置，当选择相同的块时，在位线隔离信号中不会发生改变。因此，充放电电流降低，功耗降低。由于不使用刷新计数器中的特定位，与传统技术不同，即使在改变阵列的配置的情况下，设计也变化很小。

24. 发明授权

US06704231B1 Semiconductor memory device with circuit executing burn-in testing 失效
标题翻译：具有执行老化测试的电路的半导体存储器件
公开(公告)号：US06704231B1
公开(公告)日：2004-03-09
申请号：US10397211
申请日：2003-03-27
申请人： Fukashi Morishita , Mitsuya Kinoshita
发明人： Fukashi Morishita , Mitsuya Kinoshita
IPC分类号： G11C700
CPC分类号： G11C29/12005 , G11C29/12 , G11C2029/1204
摘要： A semiconductor memory device includes an isolation unit isolating a bit line in a first region including a memory cell formed of a thick film transistor and a second region including a sense amplifier formed of a thin film transistor. Voltage supply lines are provided corresponding to respective regions. In a test mode, the isolation unit isolates the two regions. A voltage for testing is supplied from the voltage supply line. Thus, a voltage for testing corresponding to a thick film transistor and a thin film transistor can be supplied to allow efficient execution of a burn-in test.
摘要翻译：半导体存储器件包括隔离单元，隔离包括由厚膜晶体管形成的存储单元的第一区域和包括由薄膜晶体管形成的读出放大器的第二区域的位线。对应于各个区域提供电压供应线。在测试模式下，隔离单元隔离两个区域。用于测试的电压从电源线供应。因此，可以提供与厚膜晶体管和薄膜晶体管相对应的用于测试的电压，以有效地执行老化测试。

25. 发明授权

US06407538B1 Voltage down converter allowing supply of stable internal power supply voltage 失效
标题翻译：降压转换器允许提供稳定的内部电源电压
公开(公告)号：US06407538B1
公开(公告)日：2002-06-18
申请号：US09793594
申请日：2001-02-27
申请人： Mitsuya Kinoshita , Fukashi Morishita
发明人： Mitsuya Kinoshita , Fukashi Morishita
IPC分类号： G05F316
CPC分类号： G05F1/465
摘要： A voltage down converter includes a first voltage down converting circuit and a second voltage down converting circuit. The first voltage down converting circuit supplies an internal power supply voltage VCCS1 to an internal circuit only during a period T when the internal power supply voltage VCCS1 falls below a predetermined voltage according to a signal DCE. In the first voltage down converting circuit, P channel MOS transistors are selectively activated according to the levels of the plurality of voltages, and a voltage down converting partial circuit supplies a current of an amount corresponding to the level of the external power supply voltage VCC to a power supply node. As a result, even during the period T, the internal power supply voltage can be maintained at a level of the reference voltage.
摘要翻译：降压转换器包括第一降压转换电路和第二降压转换电路。第一降压转换电路仅在内部电源电压VCCS1根据信号DCE下降到预定电压以下的时段T期间将内部电源电压VCCS1提供给内部电路。在第一降压转换电路中，根据多个电压的电平选择性地激活P沟道MOS晶体管，并且降压转换部分电路将对应于外部电源电压VCC的电平的电流提供给电源节点。结果，即使在周期T期间，也可以将内部电源电压维持在基准电压的水平。

26. 发明授权

US06215720B1 High speed operable semiconductor memory device with memory blocks arranged about the center 失效
标题翻译：具有围绕中心布置的存储块的高速可操作半导体存储器件
公开(公告)号：US06215720B1
公开(公告)日：2001-04-10
申请号：US09478528
申请日：2000-01-06
申请人： Teruhiko Amano , Takahiro Tsuruda , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Mitsuya Kinoshita , Fukashi Morishita , Mako Kobayashi
发明人： Teruhiko Amano , Takahiro Tsuruda , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Mitsuya Kinoshita , Fukashi Morishita , Mako Kobayashi
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C5/025 , G11C7/22 , G11C8/12
摘要： A master control circuit provides access to a corresponding memory block via four local control circuits. The memory blocks are arranged so as to surround the master control circuit and the local control circuits. The amount of delay of a control signal to each memory block is set substantially equal to suppress skew in the control signal. A DRAM of high speed can be realized.
摘要翻译：主控制电路通过四个本地控制电路提供对对应存储器块的访问。存储块被布置成围绕主控制电路和本地控制电路。控制信号到每个存储器块的延迟量被设置为基本上等于抑制控制信号中的偏斜。可以实现高速DRAM。

27. 发明授权

US6097052A Semiconductor device and a method of manufacturing thereof 失效
公开(公告)号：US6097052A
公开(公告)日：2000-08-01
申请号：US882300
申请日：1997-06-25
申请人： Yoshinori Tanaka , Mitsuya Kinoshita , Shinya Watanabe , Tatsuo Kasaoka , Moriaki Akazawa , Toshiaki Ogawa
发明人： Yoshinori Tanaka , Mitsuya Kinoshita , Shinya Watanabe , Tatsuo Kasaoka , Moriaki Akazawa , Toshiaki Ogawa
IPC分类号： H01L21/28 , H01L21/02 , H01L21/283 , H01L21/302 , H01L21/3065 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/10 , H01L27/108
CPC分类号： H01L27/1085 , H01L21/76802 , H01L23/5226 , H01L27/10852 , H01L28/82 , H01L28/86 , H01L28/90 , H01L2924/0002
摘要： A contact hole having an opening diameter smaller than the minimum dimension that can be formed by photolithographic technique is formed. Using an interlayer insulating film 8 formed on a semiconductor substrate as an etching mask, etching is carried out halfway to form an opening 8a. The etching mask is removed, and a TEOS film 10 is formed on the interlayer oxide film 8. The whole surface is then etched anisotropically to form a contact hole 11.

28. 发明授权

US6072743A High speed operable semiconductor memory device with memory blocks arranged about the center 失效
标题翻译：具有围绕中心布置的存储块的高速可操作半导体存储器件
公开(公告)号：US6072743A
公开(公告)日：2000-06-06
申请号：US110688
申请日：1998-07-07
申请人： Teruhiko Amano , Takahiro Tsuruda , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Mitsuya Kinoshita , Fukashi Morishita , Mako Kobayashi
发明人： Teruhiko Amano , Takahiro Tsuruda , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Mitsuya Kinoshita , Fukashi Morishita , Mako Kobayashi
IPC分类号： G11C5/02 , G11C7/22 , G11C8/12 , G11C8/00
CPC分类号： G11C7/222 , G11C5/025 , G11C7/22 , G11C8/12
摘要： A master control circuit provides access to a corresponding memory block via four local control circuits. The memory blocks are arranged so as to surround the master control circuit and the local control circuits. The amount of delay of a control signal to each memory block is set substantially equal to suppress skew in the control signal. A DRAM of high speed can be realized.
摘要翻译：主控制电路通过四个本地控制电路提供对对应存储器块的访问。存储块被布置成围绕主控制电路和本地控制电路。将控制信号到每个存储块的延迟量设置为基本上等于抑制控制信号中的偏移。可以实现高速DRAM。

29. 发明授权

US6064621A Multi-bank clock synchronous type semiconductor memory device having improved memory array and power supply arrangement 失效
标题翻译：具有改进的存储器阵列和电源配置的多存储体时钟同步型半导体存储器件
公开(公告)号：US6064621A
公开(公告)日：2000-05-16
申请号：US113147
申请日：1998-07-10
申请人： Tetsushi Tanizaki , Mitsuya Kinoshita , Takeshi Fujino , Takahiro Tsuruda , Fukashi Morishita , Teruhiko Amano , Kazutami Arimoto , Mako Kobayashi
发明人： Tetsushi Tanizaki , Mitsuya Kinoshita , Takeshi Fujino , Takahiro Tsuruda , Fukashi Morishita , Teruhiko Amano , Kazutami Arimoto , Mako Kobayashi
IPC分类号： G11C11/41 , G11C5/02 , G11C5/14 , G11C8/00 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/409 , H01L21/8242 , H01L27/108
CPC分类号： G11C5/025 , G11C5/14 , G11C8/12
摘要： A rectangular semiconductor substrate region is divided into regions arranged in a plurality of rows and columns, and memory array blocks are provided to surround a central region. The plurality of memory array blocks are divided into a plurality of banks. Peripheral regions on both sides of the rectangular semiconductor substrate region are used as regions for providing sense amplifier power supply circuits, and circuits for generating a voltage to be transmitted onto word lines are provided at the four corner regions of the central region. Thus, a large storage capacity semiconductor memory device operating stably at a high speed and with reduced power consumption can be implemented.
摘要翻译：矩形半导体衬底区域被分成多个行和列布置的区域，并且存储器阵列块被设置为围绕中心区域。多个存储器阵列块被分成多个存储体。矩形半导体衬底区域的两侧的周边区域被用作提供感测放大器电源电路的区域，并且在中心区域的四个角区域处设置用于产生要传输到字线上的电压的电路。因此，可以实现以高速和低功耗稳定运行的大容量半导体存储器件。

30. 发明授权

US5580813A Method of forming a semiconductor memory device having a contact region between memory cell and an interlayer insolating layer 失效
标题翻译：形成具有在存储单元与层间绝缘层之间的接触区域的半导体存储器件的方法
公开(公告)号：US5580813A
公开(公告)日：1996-12-03
申请号：US483037
申请日：1995-06-07
申请人： Atsushi Hachisuka , Kazuhiro Tsukamoto , Mitsuya Kinoshita
发明人： Atsushi Hachisuka , Kazuhiro Tsukamoto , Mitsuya Kinoshita
IPC分类号： H01L23/522 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10817
摘要： A portion of a cell plate 91 extending upon a field oxide film 107a and a silicon oxide film 123 is referred to as a lower layer interconnection film 109. The lower layer interconnection film 109 has a concave shape. A through hole 95a is formed in a silicon oxide film 93 reaching the bottom of the concave shape lower layer interconnection film 109. The depth of the through hole 95a is greater in comparison with the case where a through hole is formed on an upper face portion 123a of the silicon oxide film 123. Because the depth of through hole 95a is great, the thickness of the tungsten film 101a formed in through hole 95a becomes thicker. This eliminates the problem that all the tungsten film 101a in the through hole 95a, and then a portion of the lower layer interconnection film 109 are overetched. Therefore, electrical connection between the upper layer interconnection layer 103a and the lower layer interconnection layer 109 can be ensured.
摘要翻译：在场氧化膜107a和氧化硅膜123上延伸的单元板91的一部分被称为下层互连膜109.下层布线膜109具有凹形。在到达凹形下层互连膜109的底部的氧化硅膜93中形成通孔95a。与在上表面部分形成通孔的情况相比，通孔95a的深度更大 123a。由于通孔95a的深度大，所以形成在通孔95a中的钨膜101a的厚度变厚。这消除了通孔95a中的所有钨膜101a以及下层互连膜109的一部分被过蚀刻的问题。因此，可以确保上层布线层103a和下层布线层109之间的电连接。

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