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21. 发明授权

US07827360B2 Cache locking device and methods thereof 有权
标题翻译：缓存锁定装置及其方法
公开(公告)号：US07827360B2
公开(公告)日：2010-11-02
申请号：US11832797
申请日：2007-08-02
申请人： Syed R. Rahman , David F. Greenberg , Kathryn C. Stacer , Klas M. Bruce , Matt B. Smittle , Michael D. Snyder , Gary L. Whisenhunt
发明人： Syed R. Rahman , David F. Greenberg , Kathryn C. Stacer , Klas M. Bruce , Matt B. Smittle , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0846 , G06F12/0891
摘要： A method and device for locking a cache line of a cache is disclosed. The method includes automatically changing a state of a cache line from a valid locked state to an invalid locked state in response to receiving an indication that a memory location external to the cache and corresponding to the cache line is associated with an access request by a processor or other data access module. Thus, the locked state of a cache line is maintained even after data in the locked cache line is invalidated. By maintaining the invalid locked state, the cache line is not available for reallocation by the cache. This allows locked cache lines that become invalidated to remain locked without additional software overhead to periodically determine whether the lock has been lost due to invalidation of the cache line.
摘要翻译：公开了一种用于锁定高速缓存的高速缓存行的方法和设备。该方法包括响应于接收到高速缓存行外部的对应于高速缓存行的存储器位置与处理器的访问请求相关联的指示，自动将高速缓存行的状态从有效锁定状态改变为无效锁定状态或其他数据访问模块。因此，即使在锁定的高速缓存行中的数据无效之后，也保持高速缓存行的锁定状态。通过保持无效的锁定状态，高速缓存行不可用于高速缓存的重新分配。这允许被锁定的高速缓存行保持锁定，而不需要额外的软件开销来定期确定锁是否由于高速缓存行的无效而丢失。

22. 发明申请

US20100106872A1 DATA PROCESSOR FOR PROCESSING A DECORATED STORAGE NOTIFY 有权
标题翻译：用于处理装饰性存储通知的数据处理器
公开(公告)号：US20100106872A1
公开(公告)日：2010-04-29
申请号：US12259368
申请日：2008-10-28
申请人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
发明人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F13/4217 , G06F9/3004 , G06F9/30043 , G06F9/3834 , G06F9/3885 , G06F13/16 , G06F2213/0054
摘要： A data processing system having a processor and a target device processes decorated instructions (i.e. an instruction having a decoration value). A device of the data processing system such as the processor sends transactions to the target device over a system interconnect. A decorated storage notify (DSN) transaction includes an indication of an instruction operation, an address associated with the instruction operation, and a decoration value (i.e. a command to the target device to perform a function in addition to a store or a load). The transaction on the system interconnect includes an address phase and no data phase, thereby improving system bandwidth. In one form the target device (e.g. a memory with functionality in addition to storage functionality) performs a read-modify-write operation using information at a storage location of the target device.
摘要翻译：具有处理器和目标设备的数据处理系统处理装饰指令（即具有装饰值的指令）。诸如处理器之类的数据处理系统的设备通过系统互连将事务发送到目标设备。装饰存储通知（DSN）事务包括指令操作的指示，与指令操作相关联的地址，以及装饰值（即除了存储或负载之外还执行功能的目标设备的命令）。系统互连上的事务包括地址阶段和数据阶段，从而提高系统带宽。在一种形式中，目标设备（例如具有除了存储功能之外的功能的存储器）使用目标设备的存储位置处的信息执行读取 - 修改 - 写入操作。

23. 发明授权

US07689815B2 Debug instruction for use in a data processing system 有权
标题翻译：用于数据处理系统的调试指令
公开(公告)号：US07689815B2
公开(公告)日：2010-03-30
申请号：US11871847
申请日：2007-10-12
申请人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
发明人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F11/36
CPC分类号： G06F11/3656 , G06F9/3005 , G06F9/30072 , G06F9/30181
摘要： A method includes providing a debug instruction and providing a debug control register field, where if the debug control register field has a first value, the debug instruction executes a debug operation and where if the debug control register field has a second value, the debug instruction is to be executed as a no-operation (NOP) instruction. A data processing system includes instruction fetch circuitry for receiving a debug instruction, a debug control register field, and debug execution control circuitry for controlling execution of the debug instruction in a first manner if the debug control register field has a first value and in a second manner if the debug control register field has a second value, where in the first manner a debug operation is performed and in the second manner no debug operation is performed.
摘要翻译：一种方法包括提供调试指令并提供调试控制寄存器字段，其中如果调试控制寄存器字段具有第一值，则调试指令执行调试操作，并且如果调试控制寄存器字段具有第二值，则调试指令将作为无操作（NOP）指令执行。数据处理系统包括用于接收调试指令的指令提取电路，调试控制寄存器字段和调试执行控制电路，用于如果调试控制寄存器字段具有第一值，则以第一方式控制调试指令的执行如果调试控制寄存器字段具有第二值，则以第一方式执行调试操作，并且在第二方式中不执行调试操作。

24. 发明授权

US07688656B2 Integrated circuit memory having dynamically adjustable read margin and method therefor 有权
标题翻译：集成电路存储器具有动态可调的读取余量及其方法
公开(公告)号：US07688656B2
公开(公告)日：2010-03-30
申请号：US11875997
申请日：2007-10-22
申请人： Shayan Zhang , Hema Ramamurthy , Zheng Xu , Michael D. Snyder
发明人： Shayan Zhang , Hema Ramamurthy , Zheng Xu , Michael D. Snyder
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C11/41 , G11C29/026 , G11C29/028 , G11C2029/0409
摘要： A method for dynamically controlling sense amplifier differential margin of a memory during operation, in an integrated circuit, including a plurality of addressable units, is provided. The method includes setting the sense amplifier differential margin corresponding to the plurality of addressable units to a first value. The method further includes if a read data error occurs when data is read from a set of the plurality of addressable units, then setting the sense amplifier differential margin corresponding to the plurality of addressable units to a second value, wherein the second value is greater than the first value.
摘要翻译：提供了一种用于在包括多个可寻址单元的集成电路中在操作期间动态地控制存储器的读出放大器差分裕度的方法。该方法包括将与多个可寻址单元相对应的读出放大器差分裕度设置为第一值。该方法还包括如果当从多个可寻址单元的集合读取数据时发生读取数据错误，则将与多个可寻址单元相对应的读出放大器差分裕度设置为第二值，其中第二值大于第一个值。

25. 发明申请

US20080288724A1 METHOD AND APPARATUS FOR CACHE TRANSACTIONS IN A DATA PROCESSING SYSTEM 有权
标题翻译：数据处理系统中高速缓存交易的方法和装置
公开(公告)号：US20080288724A1
公开(公告)日：2008-11-20
申请号：US11748350
申请日：2007-05-14
申请人： William C. Moyer , Michael D. Snyder
发明人： William C. Moyer , Michael D. Snyder
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F11/3656
摘要： A plurality of new snoop transaction types are described. Some include address information in the requests, and others include cache entry information in the requests. Some responses include tag address information, and some do not. Some provide tag address content on the data bus lines during the data portion of the transaction. These new snoop transaction types are very helpful during debug of a data processing system.
摘要翻译：描述了多个新的窥探事务类型。一些请求中包含地址信息，其他包括请求中的缓存条目信息。一些响应包括标签地址信息，有些则没有。一些在事务的数据部分期间在数据总线上提供标签地址内容。这些新的侦听事务类型在数据处理系统的调试过程中非常有用。

26. 发明申请

US20080222389A1 INTERPROCESSOR MESSAGE TRANSMISSION VIA COHERENCY-BASED INTERCONNECT 有权
标题翻译：通过基于互连的互联互通信息传输
公开(公告)号：US20080222389A1
公开(公告)日：2008-09-11
申请号：US11682867
申请日：2007-03-06
申请人： Becky G. Bruce , Sanjay R. Deshpande , Michael D. Snyder , Gary L. Whisenhunt , Kumar Gala
发明人： Becky G. Bruce , Sanjay R. Deshpande , Michael D. Snyder , Gary L. Whisenhunt , Kumar Gala
IPC分类号： G06F15/76
CPC分类号： G06F15/16 , G06F9/546 , G06F12/0833
摘要： A method includes communicating a first message between processors of a multiprocessor system via a coherency interconnect, whereby the first message includes coherency information. The method further includes communicating a second message between processors of the multiprocessor system via the coherency interconnect, whereby the second message includes interprocessor message information. A system includes a coherency interconnect and a processor. The processor includes an interface configured to receive messages from the coherency interconnect, each message including one of coherency information or interprocessor message information. The processor further includes a coherency management module configured to process coherency information obtained from at least one of the messages and an interrupt controller configured to generate an interrupt based on interprocessor message information obtained from at least one of the messages.
摘要翻译：一种方法包括经由一致性互连在多处理器系统的处理器之间传送第一消息，由此第一消息包括一致性信息。该方法还包括经由一致性互连在多处理器系统的处理器之间传送第二消息，由此第二消息包括处理器间消息信息。系统包括一致性互连和处理器。处理器包括被配置为从一致性互连接收消息的接口，每个消息包括一致性信息或处理器间消息信息之一。该处理器还包括一个相关性管理模块，被配置为处理从至少一个消息获得的一致性信息，以及中断控制器，该中断控制器被配置为基于从至少一个消息获得的处理器间消息信息生成中断。

27. 发明申请

US20080209182A1 MULTI-MODE DATA PROCESSING DEVICE AND METHODS THEREOF 有权
标题翻译：多模式数据处理装置及其方法
公开(公告)号：US20080209182A1
公开(公告)日：2008-08-28
申请号：US11679590
申请日：2007-02-27
申请人： Michael D. Snyder , David C. Holloway , Trinh H. Nguyen , Sergio Schuler , Gary L. Whisenhunt
发明人： Michael D. Snyder , David C. Holloway , Trinh H. Nguyen , Sergio Schuler , Gary L. Whisenhunt
IPC分类号： G06F9/302
CPC分类号： G06F9/30181 , G06F9/30014 , G06F9/30189 , G06F9/342
摘要： A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.
摘要翻译：公开了一种数据处理装置及其方法。数据处理设备可以在三种不同的模式下工作。在第一N位模式中，数据处理装置根据N位值执行存储器访问，并使用N位值执行算术运算。在第二种混合N比特/ M比特模式中，数据处理装置基于M比特值执行存储器访问，其中M小于N，并且使用N比特值进行算术运算。在第三个M位模式中，数据处理设备基于M位值执行存储器访问，并使用M位值执行算术运算。这三种模式提供与广泛应用的兼容性。当实现与该模式兼容的应用时，在M位模式下的进一步操作可以提供功率节省。

28. 发明授权

US07281339B2 Encoder system 失效
标题翻译：编码器系统
公开(公告)号：US07281339B2
公开(公告)日：2007-10-16
申请号：US10840769
申请日：2004-05-06
申请人： Michael D. Snyder , Koen A. Gieskes
发明人： Michael D. Snyder , Koen A. Gieskes
IPC分类号： G01D5/347
CPC分类号： G01D11/30 , G01D5/24442 , G01D5/34707 , G01D5/34753 , G01D11/10
摘要： A structure and associated method to accurately read an encoder tape in an encoder system. The encoder system comprises, a read head, a shoe structure adjacent the read head, and an encoder tape. The encoder tape is adapted to be read by the read head. The shoe structure is adapted to locally support the encoder tape and locally dampen a vibration of the encoder tape as the encoder tape is read by the read head.
摘要翻译：一种在编码器系统中精确读取编码器带的结构和相关方法。编码器系统包括读头，与读头相邻的鞋结构和编码器带。编码器磁带适于被读头读取。鞋结构适于在读取头读取编码器带时局部地支撑编码器带并且局部地抑制编码器带的振动。

29. 发明授权

US06820325B2 Integrated air flow control for a pick and place spindle assembly 有权
标题翻译：用于拾取和放置主轴总成的集成气流控制
公开(公告)号：US06820325B2
公开(公告)日：2004-11-23
申请号：US10271761
申请日：2002-10-17
申请人： Koenraad Alexander Gieskes , Michael D. Snyder , John E. Danek
发明人： Koenraad Alexander Gieskes , Michael D. Snyder , John E. Danek
IPC分类号： B23P1900
CPC分类号： H05K13/0409 , Y10S29/044 , Y10T29/5313 , Y10T29/53174 , Y10T29/53178 , Y10T29/53183 , Y10T29/53191 , Y10T409/309464
摘要： A spindle assembly for a component pick and place machine includes a housing containing a spindle for movement therein along a longitudinal axis of the spindle; the housing accommodating a valve for controlling the flow of air to an inner bore of the spindle; the inner bore of the spindle having an opening at one end for communicating the flow of air for picking and placing the components; and the flow of air from the valve to the inner bore of the spindle is internal to the housing through passageways.
摘要翻译：用于部件拾取和放置机器的主轴组件包括：壳体，其包含用于沿主轴的纵向轴线在其中移动的主轴; 所述壳体容纳用于控制到所述心轴的内孔的空气流的阀; 主轴的内孔在一端具有开口，用于连通用于拾取和放置部件的空气流; 并且从阀的空气到主轴的内孔的流动通过通道在壳体的内部。

30. 发明授权

US5363924A Weight transfer system for an agricultural machine 失效
标题翻译：农机重量转移系统
公开(公告)号：US5363924A
公开(公告)日：1994-11-15
申请号：US38316
申请日：1993-03-29
申请人： Daniel M. Foley , Michael D. Snyder
发明人： Daniel M. Foley , Michael D. Snyder
IPC分类号： A01B63/14 , A01B59/042
CPC分类号： A01B63/145
摘要： A pair of grain drills are positional for side by side operation in the field and connected to a towing tractor by weight transfer hitch having a rear end portion connected to the grain drills and a forward tongue portion having its front end connectable to the tractor drawbar and its rearward end totally connected to the forward end of the rear hitch portion for swinging about a transverse horizontal pivot. A hydraulic cylinder has its ends respectively connected to the tongue and the rear hitch portion and pressure to the cylinder is controlled by an adjustable pressure control valve that delivers pressurized fluid from the tractor hydraulic system to the cylinder at a pre-selected pressure below the tractor system pressure, whereby the force exerted by the cylinder on the tongue transfers a portion of the weight of the machine to the tractor drawbar.
摘要翻译：一对颗粒钻头在现场并排操作，并且通过重量传递连接件连接到牵引拖拉机，该拖车具有连接到谷物钻头的后端部分，以及前端部分，其前端可连接到拖拉机牵引杆，其后端完全连接到后连结部分的前端，用于围绕横向水平枢轴摆动。液压缸的端部分别连接到舌头和后连结部分，并且通过可调节的压力控制阀来控制气缸的压力，该压力控制阀将拖拉机液压系统的加压流体以预先选定的压力下降到拖拉机系统压力，从而由气缸施加在舌上的力将机器的重量的一部分转移到拖拉机牵引杆。

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