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    • 22. 发明申请
    • RESIST UNDERLAYER FILM FORMING COMPOSITION CONTAINING SILICONE HAVING ONIUM GROUP
    • 含有硅集合体的耐下层膜成膜组合物
    • US20110143149A1
    • 2011-06-16
    • US13058109
    • 2009-08-13
    • Wataru ShibayamaMakoto NakajimaYuta Kanno
    • Wataru ShibayamaMakoto NakajimaYuta Kanno
    • B32B9/04C07F7/02C09D7/12H01L21/311
    • G03F7/0755C08G77/26C09D5/006C09D183/08G03F7/0045G03F7/0757G03F7/095Y10T428/31663
    • There is provided a resist underlayer film forming composition for lithography for forming a resist underlayer film capable of being used as a hard mask or a bottom anti-reflective coating, or a resist underlayer film causing no intermixing with a resist and having a dry etching rate higher than that of the resist. A film forming composition comprising a silane compound having an onium group, wherein the silane compound having an onium group is a hydrolyzable organosilane having, in a molecule thereof, an onium group, a hydrolysis product thereof, or a hydrolysis-condensation product thereof. The composition uses as a resist underlayer film forming composition for lithography. A composition comprising a silane compound having an onium group, and a silane compound having no onium group, wherein the silane compound having an onium group exists in the whole silane compound at a ratio of less than 1% by mol, for example 0.01 to 0.95% by mol. The hydrolyzable organosilane may be a compound of Formula: R1aR2bSi(R3)4-(a+b). A resist underlayer film obtained by applying the composition as claimed in any one of claims 1 to 14 onto a semiconductor substrate and by baking the composition.
    • 提供了用于形成抗蚀剂下层膜的光刻用抗蚀剂下层膜形成用组合物,能够用作硬掩模或底部抗反射涂层,或者不与抗蚀剂混合并具有干蚀刻速率的抗蚀剂下层膜 高于抗蚀剂。 一种包含具有鎓基的硅烷化合物的成膜组合物,其中具有鎓基的硅烷化合物是其分子中具有鎓基,其水解产物或其水解缩合产物的可水解的有机硅烷。 该组合物用作光刻的抗蚀剂下层膜形成组合物。 包含具有鎓基的硅烷化合物和不具有鎓基的硅烷化合物的组合物,其中具有鎓基的硅烷化合物以小于1摩尔%的比例存在于全部硅烷化合物中,例如0.01至0.95 %摩尔。 可水解的有机硅烷可以是式:R1aR2bSi(R3)4-(a + b)的化合物。 14.一种抗蚀剂下层膜,其通过将权利要求1〜14中任一项所述的组合物涂布在半导体基板上,并烘烤该组合物而得到。
    • 28. 发明授权
    • Pulse width modulation system and image forming apparatus having the pulse width modulation system
    • 脉宽调制系统和具有脉宽调制系统的图像形成装置
    • US06326993B1
    • 2001-12-04
    • US09526289
    • 2000-03-15
    • Hiroki SatohMakoto NakajimaKoji Tanimoto
    • Hiroki SatohMakoto NakajimaKoji Tanimoto
    • B41J247
    • G06K15/00G06K2215/0002G06K2215/0011G06K2215/0082
    • When a CPU begins to monitor whether delay variation characteristics of a pulse width variation circuit have varied, it selects a basic delay setting value in a basic delay value setting block from a smallest one. The CPU sets a division number in a phase select block from a given minimum desired division number for pulse width modulation. The CPU senses the level of a phase comparison result signal (PHASE) from the pulse width modulation circuit. If the phase comparison result signal is stable at “1”, the CPU 1 fixes the division number. If the phase comparison result signal is “0” and the division number is not maximum, the CPU increases the division number and goes back to the setting of the division number. If the division number is maximum, the CPU increases the basic delay and goes back to the basic delay setting.
    • 当CPU开始监视脉宽变化电路的延迟变化特性是否变化时,从最小的基本延迟值设定块中选择基本的延迟设定值。 CPU根据脉冲宽度调制的给定最小期望分频数设置相位选择块中的分频数。 CPU检测来自脉宽调制电路的相位比较结果信号(PHASE)的电平。 如果相位比较结果信号稳定在“1”,则CPU 1固定分割号。 如果相位比较结果信号为“0”且分频数不是最大值,则CPU增加分频数,并返回到分频数的设置。 如果分频数是最大值,则CPU会增加基本延时并返回到基本延时设置。