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21. 发明授权

US06635943B1 Method and system for reducing charge gain and charge loss in interlayer dielectric formation 有权
标题翻译：降低层间电介质形成中电荷增益和电荷损失的方法和系统
公开(公告)号：US06635943B1
公开(公告)日：2003-10-21
申请号：US09533617
申请日：2000-03-22
申请人： Angela T. Hui , Tuan Duc Pham , Richard J. Huang , Mark T. Ramsbey , Lu You
发明人： Angela T. Hui , Tuan Duc Pham , Richard J. Huang , Mark T. Ramsbey , Lu You
IPC分类号： H01L2900
CPC分类号： H01L21/823425 , H01L21/76819 , H01L21/76837
摘要： A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The interlayer dielectric is capable of gap filling while using only species of relatively low mobility. The method and system also include planarizing a surface of the interlayer dielectric.
摘要翻译：公开了一种用于将半导体器件的下层与半导体器件的上层绝缘的方法和系统。该方法和系统包括在下层上提供层间电介质。层间电介质能够间隙填充，同时仅使用相对较低迁移率的物质。该方法和系统还包括平坦化层间电介质的表面。

22. 发明授权

US06518167B1 Method of forming a metal or metal nitride interface layer between silicon nitride and copper 有权
标题翻译：在氮化硅和铜之间形成金属或金属氮化物界面层的方法
公开(公告)号：US06518167B1
公开(公告)日：2003-02-11
申请号：US10123588
申请日：2002-04-16
申请人： Lu You , Matthew S. Buynoski , Paul R. Besser , Jeremias D. Romero , Pin-Chin Connie Wang , Minh Q. Tran
发明人： Lu You , Matthew S. Buynoski , Paul R. Besser , Jeremias D. Romero , Pin-Chin Connie Wang , Minh Q. Tran
IPC分类号： H01L214763
CPC分类号： H01L21/76849 , H01L21/28562 , H01L21/76834
摘要： A method of forming a metal or metal nitride layer interface between a copper layer and a silicon nitride layer can include providing a metal organic gas or metal/metal nitride precursor over a copper layer, forming a metal or metal nitride layer from reactions between the metal organic gas or metal/metal nitride precursor and the copper layer, and depositing a silicon nitride layer over the metal or metal nitride layer and copper layer. The metal or metal nitride layer can provide a better interface adhesion between the silicon nitride layer and the copper layer. The metal layer can improve the interface between the copper layer and the silicon nitride layer, improving electromigration reliability and, thus, integrated circuit device performance.
摘要翻译：在铜层和氮化硅层之间形成金属或金属氮化物层界面的方法可以包括在铜层上提供金属有机气体或金属/金属氮化物前体，从金属或金属氮化物层之间的反应形成金属或金属氮化物层有机气体或金属/金属氮化物前体和铜层，以及在金属或金属氮化物层和铜层上沉积氮化硅层。金属或金属氮化物层可以在氮化硅层和铜层之间提供更好的界面粘合性。金属层可以改善铜层和氮化硅层之间的界面，提高电迁移可靠性，从而提高集成电路器件的性能。

23. 发明授权

US06420278B1 Method for improving the dielectric constant of silicon-based semiconductor materials 失效
标题翻译：改善硅基半导体材料介电常数的方法
公开(公告)号：US06420278B1
公开(公告)日：2002-07-16
申请号：US09096760
申请日：1998-06-12
申请人： Dawn M. Hopper , Richard J. Huang , Lu You
发明人： Dawn M. Hopper , Richard J. Huang , Lu You
IPC分类号： H01L2131
CPC分类号： H01L21/02134 , H01L21/02282 , H01L21/3124
摘要： An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials in which the dielectric constant has been reduced by spinning on the dielectric to silicon wafers, eliminating soft bake steps, and heating the wafers to about 400° C. for about one hour in a vacuum or inert atmosphere.
摘要翻译：通过使用硅基低介电常数材料制造超大规模集成电路，其中介电常数通过在电介质上旋转至硅晶片而减少，消除了软烘烤步骤，并将晶片加热至约400℃ 在真空或惰性气氛中约1小时。

24. 发明授权

US06376309B2 Method for reduced gate aspect ratio to improve gap-fill after spacer etch 有权
标题翻译：减小栅极纵横比以改善间隔物刻蚀之后的间隙填充的方法
公开(公告)号：US06376309B2
公开(公告)日：2002-04-23
申请号：US09811288
申请日：2001-03-16
申请人： John JianShi Wang , Kent Kuohua Chang , Hao Fang , Lu You
发明人： John JianShi Wang , Kent Kuohua Chang , Hao Fang , Lu You
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/76837 , H01L27/115
摘要： The present invention provides a method for reducing the gate aspect ratio of a flash memory device. The method includes forming a tunnel oxide layer on a substrate; forming a polysilicon layer on the tunnel oxide layer; forming an insulating layer on the polysilicon layer; forming a control gate layer on the polysilicon layer; etching at least the tunnel oxide layer, the insulating layer, and the control gate layer to form at least two stack structures; forming a plurality of spacers at sides of the at least two stack structures; and filling at least one gap between the at least two stack structures with an oxide, where the control gate layer provides a gate aspect ratio which allows for a maximum step coverage by the oxide. In a preferred embodiment, the method uses nickel silicide instead of the conventional tungsten silicide in the control gate layers of the cells of the device. Nickel silicide has higher conductivity than conventional silicides, thus a thinner layer of nickel silicide may be used without sacrificing performance. Nickel silicide also has a lower barrier height for holes, thus maintaining a low contact resistance. With a thinner nickel silicide layer, the gate aspect ratio of the cells are lowered, allowing for a maximum step coverage by the gap-filling oxide. The reliability of the device is thus improved.
摘要翻译：本发明提供一种降低闪速存储器件的栅极纵横比的方法。该方法包括在衬底上形成隧道氧化物层; 在隧道氧化层上形成多晶硅层; 在所述多晶硅层上形成绝缘层; 在所述多晶硅层上形成控制栅极层; 至少蚀刻隧道氧化物层，绝缘层和控制栅极层以形成至少两个堆叠结构; 在所述至少两个堆叠结构的侧面处形成多个间隔物; 以及用所述氧化物填充所述至少两个堆叠结构之间的至少一个间隙，其中所述控制栅极层提供允许所述氧化物的最大阶跃覆盖的栅极纵横比。在优选实施例中，该方法在装置的电池的控制栅极层中使用硅化镍代替常规的硅化钨。硅化镍具有比常规硅化物更高的导电性，因此可以使用更薄的硅化镍层而不牺牲性能。硅化镍也具有较低的孔的阻挡高度，因此保持低的接触电阻。利用更薄的硅化镍层，电池的栅极纵横比降低，允许通过间隙填充氧化物的最大阶梯覆盖。因此提高了装置的可靠性。

25. 发明授权

US06259115B1 Dummy patterning for semiconductor manufacturing processes 有权
标题翻译：用于半导体制造工艺的虚拟图案
公开(公告)号：US06259115B1
公开(公告)日：2001-07-10
申请号：US09262214
申请日：1999-03-04
申请人： Lu You , Simon S. Chan , Kai Yang
发明人： Lu You , Simon S. Chan , Kai Yang
IPC分类号： H01L2156
CPC分类号： H01L21/7684 , H01L21/3212 , H01L21/76819
摘要： A method is provided for inserting dummy conductive channels along with the interconnected conductive channels. The dummy channels have an approximately even metal weight distribution to provide better plating uniformity, minimize CMP dishing, improve process heating uniformity, improve spin-on process properties, and increase etch and lithography uniformity.
摘要翻译：提供了一种用于将伪导电通道与互连的导电通道一起插入的方法。虚拟通道具有大致均匀的金属重量分布，以提供更好的电镀均匀性，使CMP凹陷最小化，改善工艺加热均匀性，提高旋涂工艺性能，并增加蚀刻和光刻均匀性。

26. 发明授权

US06171949B2 Low energy passivation of conductive material in damascene process for semiconductors 有权
标题翻译：半导体镶嵌工艺中导电材料的低能钝化
公开(公告)号：US06171949B2
公开(公告)日：2001-01-09
申请号：US09329155
申请日：1999-06-09
申请人： Lu You , Shekhar Pramanick
发明人： Lu You , Shekhar Pramanick
IPC分类号： H01L214763
CPC分类号： H01L21/76838 , H01L21/3143 , H01L21/318
摘要： A method for manufacturing an integrated circuit using damascene processes is provided in which conductive material surfaces subject to chemical-mechanical polishing are passivated after polishing with a dry, low energy, ion implantation passivating process to prevent oxidation and to eliminate a high dielectric constant protective layer. In particular, copper conductive material is subject to nitrogen implantation at or below 100 KeV to produce a protective copper nitride.
摘要翻译：提供一种使用镶嵌工艺制造集成电路的方法，其中进行化学机械抛光的导电材料表面在用干燥，低能量的离子注入钝化工艺抛光后被钝化，以防止氧化并消除高介电常数保护层。特别地，铜导电材料在100KeV以下进行氮注入以产生保护性的氮化铜。

27. 发明授权

US06136729A Method for improving semiconductor dielectrics 有权
标题翻译：改善半导体电介质的方法
公开(公告)号：US06136729A
公开(公告)日：2000-10-24
申请号：US133042
申请日：1998-08-12
申请人： Dawn M. Hopper , Richard J. Huang , Lu You
发明人： Dawn M. Hopper , Richard J. Huang , Lu You
IPC分类号： H01L21/312 , H01L21/314 , H01L21/316 , H01L21/31
CPC分类号： H01L21/02134 , H01L21/02282 , H01L21/3124 , H01L21/316
摘要： An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric materials on a wafer in which the hydrophobic nature of the dielectric materials is improved by relative low temperature heating in a vacuum or inert atmosphere, slowly increasing the wafer temperature to the hard bake temperature at a predetermined ramp rate, and heating the wafer at the hard bake temperature for a predetermine amount of time. As a result, the dielectric material can repel wet etch chemicals and minimize the formation of holes in the dielectric materials due to etching by wet etch chemicals.
摘要翻译：通过在晶片上使用硅基低电介质材料制造超大规模集成电路，其中通过在真空或惰性气氛中的相对低温加热来提高电介质材料的疏水性，缓慢地将晶片温度提高到硬烘烤温度以预定的斜率进行，并且在硬烘烤温度下将晶片加热预定的时间量。结果，电介质材料可以排斥湿蚀刻化学品，并且由于通过湿蚀刻化学品的蚀刻使介电材料中的孔的形成最小化。

28. 发明授权

US08629535B2 Mask for forming integrated circuit 有权
标题翻译：用于形成集成电路的掩模
公开(公告)号：US08629535B2
公开(公告)日：2014-01-14
申请号：US13241810
申请日：2011-09-23
申请人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
发明人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
IPC分类号： H01L23/58
CPC分类号： H01L21/28123 , H01L21/0332 , H01L21/28035 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
摘要翻译：形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。掩模材料包括无定形碳。该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。根据掩模在导电材料层中形成特征。

29. 发明授权

US07534732B1 Semiconductor devices with copper interconnects and composite silicon nitride capping layers 有权
标题翻译：具有铜互连的半导体器件和复合氮化硅覆盖层
公开(公告)号：US07534732B1
公开(公告)日：2009-05-19
申请号：US11356311
申请日：2006-02-17
申请人： Minh Van Ngo , Erik Wilson , Hieu Pham , Robert Huertas , Lu You , Hirokazu Tokuno , Alexander Nickel , Minh Tran
发明人： Minh Van Ngo , Erik Wilson , Hieu Pham , Robert Huertas , Lu You , Hirokazu Tokuno , Alexander Nickel , Minh Tran
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/31
CPC分类号： H01L21/0217 , C23C16/345 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/3185 , H01L21/76832 , H01L21/76834 , H01L27/11521 , H01L27/11568
摘要： Cu interconnects are formed with composite capping layers for reduced electromigration, improved adhesion between Cu and the capping layer, and reduced charge loss in associated non-volatile transistors. Embodiments include depositing a first relatively thin silicon nitride layer having a relatively high concentration of Si—H bonds on the upper surface of a layer of Cu for improved adhesion and reduced electromigration, and depositing a second relatively thick silicon nitride layer having a relatively low concentration of Si—H bonds on the first silicon nitride layer for reduced charge loss.
摘要翻译： Cu互连形成有用于减少电迁移的复合覆盖层，Cu和覆盖层之间改善的粘附性，以及相关联的非易失性晶体管中的减少的电荷损失。实施例包括在Cu层的上表面上沉积具有较高浓度的Si-H键的第一相对较薄的氮化硅层，以改善粘附性和减少电迁移，以及沉积具有较低浓度的第二较厚的氮化硅层的Si-H键在第一氮化硅层上以减少电荷损失。

30. 发明授权

US07183198B2 Method for forming a hardmask employing multiple independently formed layers of a capping material to reduce pinholes 有权
标题翻译：用于形成使用多个独立形成的封盖材料层以减少针孔的硬掩模的方法
公开(公告)号：US07183198B2
公开(公告)日：2007-02-27
申请号：US10962907
申请日：2004-10-12
申请人： Pei-Yuan Gao , Lu You , Richard J. Huang
发明人： Pei-Yuan Gao , Lu You , Richard J. Huang
IPC分类号： H01L21/4763
CPC分类号： H01L21/0332 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that are present in the lowermost PECVD layer are closed by upper PECVD layers and therefore do not extend through all of the PECVD layers. As a result the upper surface of the uppermost PECVD layer has a lower pinhole density than the lower PECVD layer. This reduces photoresist poisoning by dopant in the amorphous carbon layer, and etching of the amorphous carbon layer by photoresist stripping chemistry.
摘要翻译：双层BARC /硬掩模结构包括非晶碳层和形成在无定形碳层上的诸如SiON的PECVD材料的两个或更多个不同且独立形成的层。通过独立地形成多层PECVD材料，存在于最低PECVD层中的至少一些针孔由上PECVD层封闭，因此不延伸穿过所有PECVD层。结果，最上面的PECVD层的上表面具有比下PECVD层更低的针孔密度。这减少了无定形碳层中的掺杂剂的光致抗蚀剂中毒，以及通过光刻胶剥离化学法蚀刻无定形碳层。

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