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1. 发明授权

US06518646B1 Semiconductor device with variable composition low-k inter-layer dielectric and method of making 有权
标题翻译：具有可变组成的低k层间电介质的半导体器件及其制造方法
公开(公告)号：US06518646B1
公开(公告)日：2003-02-11
申请号：US09819615
申请日：2001-03-29
申请人： Dawn M. Hopper , Suzette K. Pangrle , Calvin T. Gabriel , Richard J. Huang , Lu You
发明人： Dawn M. Hopper , Suzette K. Pangrle , Calvin T. Gabriel , Richard J. Huang , Lu You
IPC分类号： H01L2358
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76807 , H01L21/76822 , H01L21/76829 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Strong adhesion to doped low-k inter-layer dielectrics is provided by varying the composition of dopant near the surface layers of the inter-layer dielectric. The concentration of dopant is gradually increased from about zero atomic % at the interface between the inter-layer dielectric and semiconductor substrate to improve adhesion of the inter-layer dielectric to the semiconductor substrate. The concentration of dopant at the upper surface of the inter-layer dielectric is gradually decreased to about zero atomic % at the upper surface of the inter-layer dielectric film in order to improve adhesion of additional layers to the inter-layer dielectric.
摘要翻译：通过改变层间电介质的表面层附近掺杂剂的组成，提供了对掺杂低k层间电介质的强粘合性。掺杂剂的浓度在层间电介质和半导体衬底之间的界面处从约零原子％逐渐增加，以提高层间电介质与半导体衬底的粘合性。层间电介质的上表面的掺杂剂浓度在层间电介质膜的上表面逐渐降低至约零原子％，以提高附加层对层间电介质的附着力。

2. 发明授权

US06420278B1 Method for improving the dielectric constant of silicon-based semiconductor materials 失效
标题翻译：改善硅基半导体材料介电常数的方法
公开(公告)号：US06420278B1
公开(公告)日：2002-07-16
申请号：US09096760
申请日：1998-06-12
申请人： Dawn M. Hopper , Richard J. Huang , Lu You
发明人： Dawn M. Hopper , Richard J. Huang , Lu You
IPC分类号： H01L2131
CPC分类号： H01L21/02134 , H01L21/02282 , H01L21/3124
摘要： An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials in which the dielectric constant has been reduced by spinning on the dielectric to silicon wafers, eliminating soft bake steps, and heating the wafers to about 400° C. for about one hour in a vacuum or inert atmosphere.
摘要翻译：通过使用硅基低介电常数材料制造超大规模集成电路，其中介电常数通过在电介质上旋转至硅晶片而减少，消除了软烘烤步骤，并将晶片加热至约400℃ 在真空或惰性气氛中约1小时。

3. 发明授权

US06136729A Method for improving semiconductor dielectrics 有权
标题翻译：改善半导体电介质的方法
公开(公告)号：US06136729A
公开(公告)日：2000-10-24
申请号：US133042
申请日：1998-08-12
申请人： Dawn M. Hopper , Richard J. Huang , Lu You
发明人： Dawn M. Hopper , Richard J. Huang , Lu You
IPC分类号： H01L21/312 , H01L21/314 , H01L21/316 , H01L21/31
CPC分类号： H01L21/02134 , H01L21/02282 , H01L21/3124 , H01L21/316
摘要： An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric materials on a wafer in which the hydrophobic nature of the dielectric materials is improved by relative low temperature heating in a vacuum or inert atmosphere, slowly increasing the wafer temperature to the hard bake temperature at a predetermined ramp rate, and heating the wafer at the hard bake temperature for a predetermine amount of time. As a result, the dielectric material can repel wet etch chemicals and minimize the formation of holes in the dielectric materials due to etching by wet etch chemicals.
摘要翻译：通过在晶片上使用硅基低电介质材料制造超大规模集成电路，其中通过在真空或惰性气氛中的相对低温加热来提高电介质材料的疏水性，缓慢地将晶片温度提高到硬烘烤温度以预定的斜率进行，并且在硬烘烤温度下将晶片加热预定的时间量。结果，电介质材料可以排斥湿蚀刻化学品，并且由于通过湿蚀刻化学品的蚀刻使介电材料中的孔的形成最小化。

4. 发明授权

US06388309B1 Apparatus and method for manufacturing semiconductors using low dielectric constant materials 有权
标题翻译：使用低介电常数材料制造半导体的装置和方法
公开(公告)号：US06388309B1
公开(公告)日：2002-05-14
申请号：US09687180
申请日：2000-10-12
申请人： Lu You , Dawn M. Hopper , Richard J. Huang
发明人： Lu You , Dawn M. Hopper , Richard J. Huang
IPC分类号： H01L2358
CPC分类号： H01L21/02118 , H01L21/02134 , H01L21/02282 , H01L21/02362 , H01L21/312 , H01L21/3124 , Y10S438/913
摘要： An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials which are spin-coated, dried, cured, and capped in-situ in chemical vapor deposition equipment. The low dielectric constant material is spun on, processed in chemical vapor deposition equipment, subject to chemical-mechanical polishing, and then processed by a conventional photolithographic process for depositing conductors. The material is then reprocessed for each successive layer of conductor separated by dielectric.
摘要翻译：通过使用硅基低介电常数材料制造超大规模集成电路，其在化学气相沉积设备中原位旋涂，干燥，固化和封盖。将低介电常数材料旋转，在化学气相沉积设备中进行处理，经受化学机械抛光，然后通过用于沉积导体的常规光刻工艺进行处理。然后对由电介质隔开的导体的每个连续层重新处理该材料。

5. 发明授权

US06197703B1 Apparatus and method for manufacturing semiconductors using low dielectric constant materials 有权
标题翻译：使用低介电常数材料制造半导体的装置和方法
公开(公告)号：US06197703B1
公开(公告)日：2001-03-06
申请号：US09135077
申请日：1998-08-17
申请人： Lu You , Dawn M. Hopper , Richard J. Huang
发明人： Lu You , Dawn M. Hopper , Richard J. Huang
IPC分类号： H01L2131
CPC分类号： H01L21/02118 , H01L21/02134 , H01L21/02282 , H01L21/02362 , H01L21/312 , H01L21/3124 , Y10S438/913
摘要： An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials which are spin-coated, dried, cured, and capped in-situ in chemical vapor deposition equipment. The low dielectric constant material is spun on, processed in chemical vapor deposition equipment, subject to chemical-mechanical polishing, and then processed by a conventional photolithographic process for depositing conductors. The material is then reprocessed for each successive layer of conductor separated by dielectric.
摘要翻译：通过使用硅基低介电常数材料制造超大规模集成电路，其在化学气相沉积设备中原位旋涂，干燥，固化和封盖。将低介电常数材料旋转，在化学气相沉积设备中进行处理，经受化学机械抛光，然后通过用于沉积导体的常规光刻工艺进行处理。然后对由电介质隔开的导体的每个连续层重新处理该材料。

6. 发明授权

US06429121B1 Method of fabricating dual damascene with silicon carbide via mask/ARC 有权
标题翻译：通过掩模/ ARC制造具有碳化硅的双镶嵌方法
公开(公告)号：US06429121B1
公开(公告)日：2002-08-06
申请号：US09778102
申请日：2001-02-07
申请人： Dawn M. Hopper , Ramkumar Subramanian , Richard J. Huang
发明人： Dawn M. Hopper , Ramkumar Subramanian , Richard J. Huang
IPC分类号： H01L214763
CPC分类号： H01L21/7681 , H01L21/31144 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A silicon carbide via mask/ARC is formed in implementing trench first-via last dual damascene techniques with an attendant improvement in dimensional accuracy and increased efficiency. Embodiments include forming a silicon carbide mask having an extinction coefficient (k) of about −0.2 to about −0.5 on a first dielectric layer overlying a metal feature, depositing a second dielectric layer, etching a trench in the second dielectric layer stopping on the silicon carbide via mask and then etching a via in the first dielectric layer. Embodiments further include Cu and Cu alloy dual damascene methodology.
摘要翻译：在实现沟槽第一通孔最后的双镶嵌技术中形成碳化硅通孔掩模/ ARC，伴随着尺寸精度的提高和效率的提高。实施例包括在覆盖金属特征的第一介电层上形成具有约-0.2至约-0.5的消光系数（k）的碳化硅掩模，沉积第二介电层，蚀刻停止在硅上的第二介电层中的沟槽碳化物通孔掩模，然后在第一介电层中蚀刻通孔。实施例还包括Cu和Cu合金双镶嵌方法。

7. 发明申请

US20120007221A1 MASK FOR FORMING INTEGRATED CIRCUIT 有权
标题翻译：形成集成电路的掩模
公开(公告)号：US20120007221A1
公开(公告)日：2012-01-12
申请号：US13241810
申请日：2011-09-23
申请人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
发明人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
IPC分类号： H01L29/66 , C23F1/00
CPC分类号： H01L21/28123 , H01L21/0332 , H01L21/28035 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
摘要翻译：形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。掩模材料包括无定形碳。该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。根据掩模在导电材料层中形成特征。

8. 发明授权

US07521304B1 Method for forming integrated circuit 失效
标题翻译：集成电路形成方法
公开(公告)号：US07521304B1
公开(公告)日：2009-04-21
申请号：US10230775
申请日：2002-08-29
申请人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
发明人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L21/0332 , H01L21/28035 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
摘要翻译：形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。掩模材料包括无定形碳。该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。根据掩模在导电材料层中形成特征。

9. 发明授权

US06317642B1 Apparatus and methods for uniform scan dispensing of spin-on materials 有权
标题翻译：用于均匀扫描分配旋涂材料的装置和方法
公开(公告)号：US06317642B1
公开(公告)日：2001-11-13
申请号：US09191438
申请日：1998-11-12
申请人： Lu You , Dawn Hopper , Christof Streck , John Pellerin , Richard J. Huang
发明人： Lu You , Dawn Hopper , Christof Streck , John Pellerin , Richard J. Huang
IPC分类号： G06F1900
CPC分类号： H01L21/6715 , B05D1/005
摘要： This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions containing thin film precursor via a moveable dispensing device and the careful regulation of the pattern of deposition of the precursor solution onto the wafer. The invention also comprises the careful regulation of deposition variables including dispensation time, wafer rpm, stop time and rates of wafer rotation. In one embodiment, the precursor solution is dispensed from the outer edge of the wafer toward the center. In alternative embodiments, processors regulate the movement of the dispensing arm and the precursor pump to provide an evenly dispensed layer of precursor solution. The invention also describes improved methods for evaporating solvents and curing thin films. The methods of this invention enable the production of spin-on thin films, which have more even film thickness and uniformity. The semiconductor thin films produced by the methods of this invention are useful for the manufacture of semiconductor devices comprising interlevel dielectric materials.
摘要翻译：本发明描述了用于半导体薄膜的旋涂沉积的改进的装置和方法。改进的装置提供沉积室内的受控温度，压力和气体组成。改进的方法包括通过可移动的分配装置分配含有薄膜前体的溶液，以及仔细调节前体溶液沉积在晶片上的图案。本发明还包括仔细调节沉积变量，包括分配时间，晶片转速，停止时间和晶片旋转速率。在一个实施方案中，前体溶液从晶片的外边缘向中心分配。在替代实施例中，处理器调节分配臂和前驱泵的运动，以提供均匀分配的前体溶液层。本发明还描述了用于蒸发溶剂和固化薄膜的改进方法。本发明的方法能够生产具有更均匀的膜厚度和均匀性的旋涂薄膜。通过本发明的方法生产的半导体薄膜可用于制造包括层间电介质材料的半导体器件。

10. 发明授权

US06235453B1 Low-k photoresist removal process 有权
标题翻译：低k光刻胶去除工艺
公开(公告)号：US06235453B1
公开(公告)日：2001-05-22
申请号：US09349055
申请日：1999-07-07
申请人： Lu You , Steven C. Avanzino , Jacques Bertrand , Richard J. Huang
发明人： Lu You , Steven C. Avanzino , Jacques Bertrand , Richard J. Huang
IPC分类号： G03F726
CPC分类号： G03F7/427 , G03F7/42 , H01L21/02052 , H01L21/31138
摘要： An integrated circuit and a method of removing photoresist is described. The process described uses a low oxygen gas or non-oxygen gas plasma that removes the photoresist and provides a protective surface layer over the low-k dielectric material. The low-k dielectric material is part of a dielectric stack. After exposure to the gas plasmas the integrated circuit is subjected to solvent.
摘要翻译：描述了集成电路和去除光致抗蚀剂的方法。所描述的方法使用低氧气体或非氧气体等离子体，其去除光致抗蚀剂并在低k电介质材料上提供保护性表面层。低k电介质材料是电介质叠层的一部分。暴露于气体等离子体后，集成电路经受溶剂。

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