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21. 发明授权

US07366034B2 Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US07366034B2
公开(公告)日：2008-04-29
申请号：US11797842
申请日：2007-05-08
申请人： Kenji Kozakai , Takeshi Nakamura , Tatsuya Ishii , Motoyasu Tsunoda , Shinya Iguchi , Junichi Maruyama
发明人： Kenji Kozakai , Takeshi Nakamura , Tatsuya Ishii , Motoyasu Tsunoda , Shinya Iguchi , Junichi Maruyama
IPC分类号： G11C7/10
CPC分类号： G06F12/0246 , G06F11/1068 , G06F12/06 , G06F2212/1036 , G11C16/04 , G11C16/10 , G11C16/349 , G11C29/44 , G11C29/76 , G11C2029/0409
摘要： For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate. The nonvolatile memory is provided with a replacing function to replace a group of memory cells including defective memory cells which are incapable of normal writing or erasion with a group of memory cells including no defective memory cell, a numbers of rewrites averaging function to grasp the number of data rewrites in each group of memory cells and to so perform replacement of memory cell groups that there may arise no substantial difference in the number of rewrites among a plurality of memory cell groups, and an error correcting function to detect and correct any error in data stored in the memory array, wherein first address translation information deriving from the replacing function and second address translation information deriving from the numbers of rewrites averaging function are stored in respectively prescribed areas in the memory array, and the first address translation information and second address translation information concerning the same memory cell group are stored in a plurality of sets in a time series.
摘要翻译：对于允许电子写入和擦除要存储的信息（例如闪存）的非易失性存储器，系统开发者的负载将被减少，并且即使这样的系统的重要数据也可以避免由于管理和地址转换信息被破坏，系统无法运行的异常状态。非易失性存储器设置有替换功能，以替换包括不能正常写入或擦除的缺陷存储器单元的存储器单元组，所述存储器单元不包括不存在缺陷存储器单元的存储单元组，重写次数用于掌握数量的每个存储器单元组中的数据重写，并且因此执行存储单元组的替换，使得多个存储单元组之间的重写次数可能没有显着差异，以及用于检测和校正任何错误的错误校正功能存储在存储器阵列中的数据，其中从替换功能导出的第一地址转换信息和从重写平均函数导出的第二地址转换信息被存储在存储器阵列中的分别规定的区域中，并且第一地址转换信息和第二地址关于相同存储单元组的翻译信息是sto 以时间序列的多个集合中的红色。

22. 发明申请

US20080002480A1 Nonvolatile memory apparatus 审中-公开
标题翻译：非易失存储器
公开(公告)号：US20080002480A1
公开(公告)日：2008-01-03
申请号：US11896912
申请日：2007-09-06
申请人： Tsutomu Nakajima , Satoshi Noda , Kenji Kozakai , Atsushi Tokairin
发明人： Tsutomu Nakajima , Satoshi Noda , Kenji Kozakai , Atsushi Tokairin
IPC分类号： G11C7/10
CPC分类号： G11C29/84 , G11C29/82
摘要： A nonvolatile memory apparatus which need not compare an access address with a faulty address every time for rescuing from any fault is to be provided. The apparatus has memory arrays, data registers for inputting and outputting data to and from the memory arrays, and control circuits. The control circuits, after transferring a plurality of sets of data from the memory arrays to the data registers in response to an instruction to read data, take out rescuing data out of the plurality of sets of data transferred to the data registers, and perform processing to replace with the taken-out rescuing data corresponding faulty addresses on the data register to enable the data on the data register to be supplied to the outside. When any faulty data in the read data are to be replaced with rescuing data on any data register to which data have been transferred from any memory array, read access addresses need not be checked whether or not they are faulty every time an access address is supplied from outside.
摘要翻译：提供不需要每次对任何故障进行抢救的访问地址与故障地址进行比较的非易失性存储装置。该装置具有存储器阵列，用于向存储器阵列输入数据和从存储器阵列输出数据的数据寄存器以及控制电路。控制电路在响应于读取数据的指令将多组数据从存储器阵列传送到数据寄存器之后，从传送到数据寄存器的多组数据中取出拯救数据，并执行处理取代数据寄存器上相应的故障地址的取出救援数据，使数据寄存器上的数据能够提供给外部。当数据从任何存储器阵列传送到任何数据寄存器上时，读取数据中的任何有故障的数据将被替换为数据寄存器中的数据，每次提供访问地址时，不需要检查读取访问地址是否有故障从外面。

23. 发明授权

US07305596B2 Nonvolatile memory and nonvolatile memory apparatus 有权
标题翻译：非易失性存储器和非易失性存储器件
公开(公告)号：US07305596B2
公开(公告)日：2007-12-04
申请号：US11182781
申请日：2005-07-18
申请人： Satoshi Noda , Kenji Kozakai , Toru Matsushita , Yusuke Jono
发明人： Satoshi Noda , Kenji Kozakai , Toru Matsushita , Yusuke Jono
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C11/5621 , G11C16/3454
摘要： To provide a technique which enables a load on a controller to be reduced by rapidly detecting n-bit errors during writing/erasing on a chip in ECC in a nonvolatile memory. A flash memory of the present invention, which is a nonvolatile memory that includes plural electrically erasable and writable nonvolatile memory cells and performs write-and-verify processing in a write operation on the nonvolatile memory cells, includes an ECC determination circuit that counts the number of bits of write error detected in the write-and-verify processing, and outputs the information, and a status register for holding pass/fail information of the write operation and the information about the number of bits of write error outputted from the ECC determination circuit.
摘要翻译：提供一种能够通过在非易失性存储器中的ECC中的芯片上的写入/擦除期间快速检测n位错误来降低控制器上的负载的技术。作为非易失性存储器的本发明的闪速存储器，其是包括多个电可擦写可写非易失性存储单元的非易失性存储器，并且在对非易失性存储单元的写入操作中进行写入验证处理包括：ECC确定电路，在写入和验证处理中检测到的写入错误的位，并且输出该信息，以及用于保持写入操作的通过/失败信息的状态寄存器以及关于从ECC确定输出的写入错误的位数的信息电路。

24. 发明申请

US20060026489A1 Nonvolatile memory and nonvolatile memory apparatus 有权
标题翻译：非易失性存储器和非易失性存储器件
公开(公告)号：US20060026489A1
公开(公告)日：2006-02-02
申请号：US11182781
申请日：2005-07-18
申请人： Satoshi Noda , Kenji Kozakai , Toru Matsushita , Yusuke Jono
发明人： Satoshi Noda , Kenji Kozakai , Toru Matsushita , Yusuke Jono
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C11/5621 , G11C16/3454
摘要： To provide a technique which enables a load on a controller to be reduced by rapidly detecting n-bit errors during writing/erasing on a chip in ECC in a nonvolatile memory. A flash memory of the present invention, which is a nonvolatile memory that includes plural electrically erasable and writable nonvolatile memory cells and performs write-and-verify processing in a write operation on the nonvolatile memory cells, includes an ECC determination circuit that counts the number of bits of write error detected in the write-and-verify processing, and outputs the information, and a status register for holding pass/fail information of the write operation and the information about the number of bits of write error outputted from the ECC determination circuit.
摘要翻译：提供一种能够通过在非易失性存储器中的ECC中的芯片上的写入/擦除期间快速检测n位错误来降低控制器上的负载的技术。作为非易失性存储器的本发明的闪速存储器，其是包括多个电可擦写可写非易失性存储单元的非易失性存储器，并且在对非易失性存储单元的写入操作中进行写入验证处理包括：ECC确定电路，在写入和验证处理中检测到的写入错误的位，并且输出该信息，以及用于保持写入操作的通过/失败信息的状态寄存器和关于从ECC确定输出的写入错误的位数的信息电路。

25. 发明授权

US5847995A Nonvolatile semiconductor memory device having a plurality of blocks provided on a plurality of electrically isolated wells 失效
标题翻译：具有设置在多个电隔离的井上的多个块的非易失性半导体存储器件
公开(公告)号：US5847995A
公开(公告)日：1998-12-08
申请号：US852354
申请日：1997-05-07
申请人： Shinichi Kobayashi , Shinji Kawai , Tadashi Omae , Makoto Oi , Akinori Matsuo , Masashi Wada , Kenji Kozakai
发明人： Shinichi Kobayashi , Shinji Kawai , Tadashi Omae , Makoto Oi , Akinori Matsuo , Masashi Wada , Kenji Kozakai
IPC分类号： G11C17/00 , G11C16/06 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/78
摘要： The inventive DINOR flash memory includes a plurality of blocks, a spare block and a spare word line block, which are formed on a plurality of electrically isolated P-type wells. When a word line-to-well short-circuit takes place in a certain block and another block is selected, the block causing the word line-to-well short-circuit is brought into a non-selected state. Thus, no leakage takes place in the block causing the word line-to-well short-circuit, to exert no bad influence on the selected block.
摘要翻译：本发明的DINOR闪速存储器包括形成在多个电隔离P型阱上的多个块，备用块和备用字线块。当在某个块中发生字线对阱短路并且选择另一个块时，导致字线对阱短路的块被带入非选择状态。因此，在导致字线到阱短路的块中不发生泄漏，对所选择的块不会产生不良影响。

26. 发明授权

US07697334B2 Nonvolatile semiconductor memory device and writing method thereof 失效
标题翻译：非易失性半导体存储器件及其写入方法
公开(公告)号：US07697334B2
公开(公告)日：2010-04-13
申请号：US11892738
申请日：2007-08-27
申请人： Tsutomu Nakajima , Kenji Kozakai , Koji Sakui
发明人： Tsutomu Nakajima , Kenji Kozakai , Koji Sakui
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3454 , G11C2211/5621
摘要： Disclosed herein is a nonvolatile semiconductor memory device including: a first selection transistor configured to be connected to a bit line; a second selection transistor configured to be connected to a common source line; a memory cell configured to be connected in series between the first and second selection transistors; and writing means for carrying out writing for a selected memory cell. In the nonvolatile semiconductor memory device, the writing means applies a potential yielding a writing-blocked state via a bit line to a memory cell for which writing is not to be carried out, of a memory cell selected for writing, and the writing means carries out writing for a writing-target memory cell in a state in which a bit line has a bit line potential state dependent upon a threshold value state of the writing-target memory cell.
摘要翻译：这里公开了一种非易失性半导体存储器件，包括：第一选择晶体管，被配置为连接到位线; 第二选择晶体管，被配置为连接到公共源极线; 存储单元，被配置为串联连接在第一和第二选择晶体管之间; 以及用于对所选择的存储单元执行写入的写入装置。在非易失性半导体存储器件中，写入装置将选择写入的存储单元通过位线施加产生写入阻塞状态的电位到写入不被执行的存储单元，并且写入装置携带在位线具有取决于写入 - 目标存储单元的阈值状态的位线电位状态的状态下的写入 - 目标存储单元的写入。

27. 发明授权

US07542355B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US07542355B2
公开(公告)日：2009-06-02
申请号：US11902721
申请日：2007-09-25
申请人： Kenji Kozakai , Tsutomu Nakajima , Koji Sakui
发明人： Kenji Kozakai , Tsutomu Nakajima , Koji Sakui
IPC分类号： G11C7/10
CPC分类号： G11C8/12 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C16/0483 , G11C16/10 , G11C16/32
摘要： Disclosed herein is a semiconductor storage device including: a memory core having memory cells to be accessed; and an interface circuit having terminals operable to input and output a chip enable signal adapted to select a chip, at least one control signal adapted to control the chip operation, a clock signal adapted to control the chip I/O operation timing and a series of data including a command, address and data; wherein the interface circuit includes at least one input holding unit adapted to hold the control signal, and the interface circuit processes the control signal after loading it temporarily into the first input holding unit.
摘要翻译：这里公开了一种半导体存储装置，包括：具有要存取的存储单元的存储器核; 以及接口电路，其具有可操作以输入和输出适于选择芯片的芯片使能信号的终端，适于控制芯片操作的至少一个控制信号，适于控制芯片I / O操作定时的时钟信号，以及一系列数据包括命令，地址和数据; 其中所述接口电路包括适于保持所述控制信号的至少一个输入保持单元，并且所述接口电路在将其暂时加载到所述第一输入保持单元之后对所述控制信号进行处理。

28. 发明授权

US07525852B2 Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US07525852B2
公开(公告)日：2009-04-28
申请号：US12048208
申请日：2008-03-13
申请人： Kenji Kozakai , Takeshi Nakamura , Tatsuya Ishii , Motoyasu Tsunoda , Shinya Iguchi , Junichi Maruyama
发明人： Kenji Kozakai , Takeshi Nakamura , Tatsuya Ishii , Motoyasu Tsunoda , Shinya Iguchi , Junichi Maruyama
IPC分类号： G11C5/14
CPC分类号： G06F12/0246 , G06F11/1068 , G06F12/06 , G06F2212/1036 , G11C16/04 , G11C16/10 , G11C16/349 , G11C29/44 , G11C29/76 , G11C2029/0409
摘要： For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate. The nonvolatile memory is provided with a replacing function to replace a group of memory cells including defective memory cells which are incapable of normal writing or erasion with a group of memory cells including no defective memory cell, a numbers of rewrites averaging function to grasp the number of data rewrites in each group of memory cells and to so perform replacement of memory cell groups that there may arise no substantial difference in the number of rewrites among a plurality of memory cell groups, and an error correcting function to detect and correct any error in data stored in the memory array, wherein first address translation information deriving from the replacing function and second address translation information deriving from the numbers of rewrites averaging function are stored in respectively prescribed areas in the memory array, and the first address translation information and second address translation information concerning the same memory cell group are stored in a plurality of sets in a time series.
摘要翻译：对于允许电子写入和擦除要存储的信息（例如闪存）的非易失性存储器，系统开发者的负载将被减少，并且即使这样的系统的重要数据也可以避免由于管理和地址转换信息被破坏，系统无法运行的异常状态。非易失性存储器设置有替换功能，以替换包括不能正常写入或擦除的缺陷存储器单元的存储器单元组，所述存储器单元不包括不存在缺陷存储器单元的存储单元组，重写次数用于掌握数量的每个存储器单元组中的数据重写，并且因此执行存储单元组的替换，使得多个存储单元组之间的重写次数可能没有显着差异，以及用于检测和校正任何错误的错误校正功能存储在存储器阵列中的数据，其中从替换功能导出的第一地址转换信息和从重写平均函数导出的第二地址转换信息被存储在存储器阵列中的分别规定的区域中，并且第一地址转换信息和第二地址关于相同存储单元组的翻译信息是sto 以时间序列的多个集合中的红色。

29. 发明申请

US20080084742A1 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US20080084742A1
公开(公告)日：2008-04-10
申请号：US11902721
申请日：2007-09-25
申请人： Kenji Kozakai , Tsutomu Nakajima , Koji Sakui
发明人： Kenji Kozakai , Tsutomu Nakajima , Koji Sakui
IPC分类号： G11C16/04 , G11C8/00
CPC分类号： G11C8/12 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C16/0483 , G11C16/10 , G11C16/32
摘要： Disclosed herein is a semiconductor storage device including: a memory core having memory cells to be accessed; and an interface circuit having terminals operable to input and output a chip enable signal adapted to select a chip, at least one control signal adapted to control the chip operation, a clock signal adapted to control the chip I/O operation timing and a series of data including a command, address and data; wherein the interface circuit includes at least one input holding unit adapted to hold the control signal, and the interface circuit processes the control signal after loading it temporarily into the first input holding unit.
摘要翻译：这里公开了一种半导体存储装置，包括：具有要存取的存储单元的存储器核; 以及接口电路，其具有可操作以输入和输出适于选择芯片的芯片使能信号的终端，适于控制芯片操作的至少一个控制信号，适于控制芯片I / O操作定时的时钟信号，以及一系列数据包括命令，地址和数据; 其中所述接口电路包括适于保持所述控制信号的至少一个输入保持单元，并且所述接口电路在将其暂时加载到所述第一输入保持单元之后对所述控制信号进行处理。

30. 发明申请

US20070206418A1 Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US20070206418A1
公开(公告)日：2007-09-06
申请号：US11797842
申请日：2007-05-08
申请人： Kenji Kozakai , Takeshi Nakamura , Tatsuya Ishii , Motoyasu Tsunoda , Shinya Iguchi , Junichi Maruyama
发明人： Kenji Kozakai , Takeshi Nakamura , Tatsuya Ishii , Motoyasu Tsunoda , Shinya Iguchi , Junichi Maruyama
IPC分类号： G11C29/00
CPC分类号： G06F12/0246 , G06F11/1068 , G06F12/06 , G06F2212/1036 , G11C16/04 , G11C16/10 , G11C16/349 , G11C29/44 , G11C29/76 , G11C2029/0409
摘要： For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate. The nonvolatile memory is provided with a replacing function to replace a group of memory cells including defective memory cells which are incapable of normal writing or erasion with a group of memory cells including no defective memory cell, a numbers of rewrites averaging function to grasp the number of data rewrites in each group of memory cells and to so perform replacement of memory cell groups that there may arise no substantial difference in the number of rewrites among a plurality of memory cell groups, and an error correcting function to detect and correct any error in data stored in the memory array, wherein first address translation information deriving from the replacing function and second address translation information deriving from the numbers of rewrites averaging function are stored in respectively prescribed areas in the memory array, and the first address translation information and second address translation information concerning the same memory cell group are stored in a plurality of sets in a time series.
摘要翻译：对于允许电子写入和擦除要存储的信息（例如闪存）的非易失性存储器，系统开发者的负载将被减少，并且即使这样的系统的重要数据也可以避免由于管理和地址转换信息被破坏，系统无法运行的异常状态。非易失性存储器设置有替换功能，以替换包括不能正常写入或擦除的缺陷存储器单元的存储器单元组，所述存储器单元不包括不存在缺陷存储器单元的存储单元组，重写次数用于掌握数量的每个存储器单元组中的数据重写，并且因此执行存储单元组的替换，使得多个存储单元组之间的重写次数可能没有显着差异，以及用于检测和校正任何错误的错误校正功能存储在存储器阵列中的数据，其中从替换功能导出的第一地址转换信息和从重写平均函数导出的第二地址转换信息被存储在存储器阵列中的分别规定的区域中，并且第一地址转换信息和第二地址关于相同存储单元组的翻译信息是sto 以时间序列的多个集合中的红色。

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