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1. 发明授权

US07697334B2 Nonvolatile semiconductor memory device and writing method thereof 失效
标题翻译：非易失性半导体存储器件及其写入方法
公开(公告)号：US07697334B2
公开(公告)日：2010-04-13
申请号：US11892738
申请日：2007-08-27
申请人： Tsutomu Nakajima , Kenji Kozakai , Koji Sakui
发明人： Tsutomu Nakajima , Kenji Kozakai , Koji Sakui
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3454 , G11C2211/5621
摘要： Disclosed herein is a nonvolatile semiconductor memory device including: a first selection transistor configured to be connected to a bit line; a second selection transistor configured to be connected to a common source line; a memory cell configured to be connected in series between the first and second selection transistors; and writing means for carrying out writing for a selected memory cell. In the nonvolatile semiconductor memory device, the writing means applies a potential yielding a writing-blocked state via a bit line to a memory cell for which writing is not to be carried out, of a memory cell selected for writing, and the writing means carries out writing for a writing-target memory cell in a state in which a bit line has a bit line potential state dependent upon a threshold value state of the writing-target memory cell.
摘要翻译：这里公开了一种非易失性半导体存储器件，包括：第一选择晶体管，被配置为连接到位线; 第二选择晶体管，被配置为连接到公共源极线; 存储单元，被配置为串联连接在第一和第二选择晶体管之间; 以及用于对所选择的存储单元执行写入的写入装置。在非易失性半导体存储器件中，写入装置将选择写入的存储单元通过位线施加产生写入阻塞状态的电位到写入不被执行的存储单元，并且写入装置携带在位线具有取决于写入 - 目标存储单元的阈值状态的位线电位状态的状态下的写入 - 目标存储单元的写入。

2. 发明授权

US07542355B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US07542355B2
公开(公告)日：2009-06-02
申请号：US11902721
申请日：2007-09-25
申请人： Kenji Kozakai , Tsutomu Nakajima , Koji Sakui
发明人： Kenji Kozakai , Tsutomu Nakajima , Koji Sakui
IPC分类号： G11C7/10
CPC分类号： G11C8/12 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C16/0483 , G11C16/10 , G11C16/32
摘要： Disclosed herein is a semiconductor storage device including: a memory core having memory cells to be accessed; and an interface circuit having terminals operable to input and output a chip enable signal adapted to select a chip, at least one control signal adapted to control the chip operation, a clock signal adapted to control the chip I/O operation timing and a series of data including a command, address and data; wherein the interface circuit includes at least one input holding unit adapted to hold the control signal, and the interface circuit processes the control signal after loading it temporarily into the first input holding unit.
摘要翻译：这里公开了一种半导体存储装置，包括：具有要存取的存储单元的存储器核; 以及接口电路，其具有可操作以输入和输出适于选择芯片的芯片使能信号的终端，适于控制芯片操作的至少一个控制信号，适于控制芯片I / O操作定时的时钟信号，以及一系列数据包括命令，地址和数据; 其中所述接口电路包括适于保持所述控制信号的至少一个输入保持单元，并且所述接口电路在将其暂时加载到所述第一输入保持单元之后对所述控制信号进行处理。

3. 发明申请

US20080084742A1 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US20080084742A1
公开(公告)日：2008-04-10
申请号：US11902721
申请日：2007-09-25
申请人： Kenji Kozakai , Tsutomu Nakajima , Koji Sakui
发明人： Kenji Kozakai , Tsutomu Nakajima , Koji Sakui
IPC分类号： G11C16/04 , G11C8/00
CPC分类号： G11C8/12 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C16/0483 , G11C16/10 , G11C16/32
摘要： Disclosed herein is a semiconductor storage device including: a memory core having memory cells to be accessed; and an interface circuit having terminals operable to input and output a chip enable signal adapted to select a chip, at least one control signal adapted to control the chip operation, a clock signal adapted to control the chip I/O operation timing and a series of data including a command, address and data; wherein the interface circuit includes at least one input holding unit adapted to hold the control signal, and the interface circuit processes the control signal after loading it temporarily into the first input holding unit.
摘要翻译：这里公开了一种半导体存储装置，包括：具有要存取的存储单元的存储器核; 以及接口电路，其具有可操作以输入和输出适于选择芯片的芯片使能信号的终端，适于控制芯片操作的至少一个控制信号，适于控制芯片I / O操作定时的时钟信号，以及一系列数据包括命令，地址和数据; 其中所述接口电路包括适于保持所述控制信号的至少一个输入保持单元，并且所述接口电路在将其暂时加载到所述第一输入保持单元之后对所述控制信号进行处理。

4. 发明申请

US20080055999A1 Nonvolatile semiconductor memory device and writing method thereof 失效
标题翻译：非易失性半导体存储器件及其写入方法
公开(公告)号：US20080055999A1
公开(公告)日：2008-03-06
申请号：US11892738
申请日：2007-08-27
申请人： Tsutomu Nakajima , Kenji Kozakai , Koji Sakui
发明人： Tsutomu Nakajima , Kenji Kozakai , Koji Sakui
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3454 , G11C2211/5621
摘要： Disclosed herein is a nonvolatile semiconductor memory device including: a first selection transistor configured to be connected to a bit line; a second selection transistor configured to be connected to a common source line; a memory cell configured to be connected in series between the first and second selection transistors; and writing means for carrying out writing for a selected memory cell. In the nonvolatile semiconductor memory device, the writing means applies a potential yielding a writing-blocked state via a bit line to a memory cell for which writing is not to be carried out, of a memory cell selected for writing, and the writing means carries out writing for a writing-target memory cell in a state in which a bit line has a bit line potential state dependent upon a threshold value state of the writing-target memory cell.
摘要翻译：这里公开了一种非易失性半导体存储器件，包括：第一选择晶体管，被配置为连接到位线; 第二选择晶体管，被配置为连接到公共源极线; 存储单元，被配置为串联连接在第一和第二选择晶体管之间; 以及用于对所选择的存储单元执行写入的写入装置。在非易失性半导体存储器件中，写入装置将选择写入的存储单元通过位线施加产生写入阻塞状态的电位到不进行写入的存储单元，并且写入装置携带在位线具有取决于写入 - 目标存储单元的阈值状态的位线电位状态的状态下的写入 - 目标存储单元的写入。

5. 发明申请

US20080002480A1 Nonvolatile memory apparatus 审中-公开
标题翻译：非易失存储器
公开(公告)号：US20080002480A1
公开(公告)日：2008-01-03
申请号：US11896912
申请日：2007-09-06
申请人： Tsutomu Nakajima , Satoshi Noda , Kenji Kozakai , Atsushi Tokairin
发明人： Tsutomu Nakajima , Satoshi Noda , Kenji Kozakai , Atsushi Tokairin
IPC分类号： G11C7/10
CPC分类号： G11C29/84 , G11C29/82
摘要： A nonvolatile memory apparatus which need not compare an access address with a faulty address every time for rescuing from any fault is to be provided. The apparatus has memory arrays, data registers for inputting and outputting data to and from the memory arrays, and control circuits. The control circuits, after transferring a plurality of sets of data from the memory arrays to the data registers in response to an instruction to read data, take out rescuing data out of the plurality of sets of data transferred to the data registers, and perform processing to replace with the taken-out rescuing data corresponding faulty addresses on the data register to enable the data on the data register to be supplied to the outside. When any faulty data in the read data are to be replaced with rescuing data on any data register to which data have been transferred from any memory array, read access addresses need not be checked whether or not they are faulty every time an access address is supplied from outside.
摘要翻译：提供不需要每次对任何故障进行抢救的访问地址与故障地址进行比较的非易失性存储装置。该装置具有存储器阵列，用于向存储器阵列输入数据和从存储器阵列输出数据的数据寄存器以及控制电路。控制电路在响应于读取数据的指令将多组数据从存储器阵列传送到数据寄存器之后，从传送到数据寄存器的多组数据中取出拯救数据，并执行处理取代数据寄存器上相应的故障地址的取出救援数据，使数据寄存器上的数据能够提供给外部。当数据从任何存储器阵列传送到任何数据寄存器上时，读取数据中的任何有故障的数据将被替换为数据寄存器中的数据，每次提供访问地址时，不需要检查读取访问地址是否有故障从外面。

6. 发明申请

US20060002199A1 Nonvolatile memory apparatus 有权
标题翻译：非易失存储器
公开(公告)号：US20060002199A1
公开(公告)日：2006-01-05
申请号：US11159303
申请日：2005-06-23
申请人： Tsutomu Nakajima , Satoshi Noda , Kenji Kozakai , Atsushi Tokairin
发明人： Tsutomu Nakajima , Satoshi Noda , Kenji Kozakai , Atsushi Tokairin
IPC分类号： G11C7/00
CPC分类号： G11C29/84 , G11C29/82
摘要： A nonvolatile memory apparatus which need not compare an access address with a faulty address every time for rescuing from any fault is to be provided. The apparatus has memory arrays, data registers for inputting and outputting data to and from the memory arrays, and control circuits. The control circuits, after transferring a plurality of sets of data from the memory arrays to the data registers in response to an instruction to read data, take out rescuing data out of the plurality of sets of data transferred to the data registers, and perform processing to replace with the taken-out rescuing data corresponding faulty addresses on the data register to enable the data on the data register to be supplied to the outside. When any faulty data in the read data are to be replaced with rescuing data on any data register to which data have been transferred from any memory array, read access addresses need not be checked whether or not they are faulty every time an access address is supplied from outside.
摘要翻译：提供不需要每次对任何故障进行抢救的访问地址与故障地址进行比较的非易失性存储装置。该装置具有存储器阵列，用于向存储器阵列输入数据和从存储器阵列输出数据的数据寄存器以及控制电路。控制电路在响应于读取数据的指令将多组数据从存储器阵列传送到数据寄存器之后，从传送到数据寄存器的多组数据中取出拯救数据，并执行处理取代数据寄存器上相应的故障地址的取出救援数据，使数据寄存器上的数据能够提供给外部。当数据从任何存储器阵列传送到任何数据寄存器上时，读取数据中的任何有故障的数据将被替换为劫持数据时，每次提供访问地址时，都不需要检查读取访问地址是否有故障从外面。

7. 发明授权

US07283408B2 Nonvolatile memory apparatus enabling data to be replaced prior to supplying read data and prior to supplying write data 有权
标题翻译：在提供读取数据之前和在提供写入数据之前使数据能被替换的非易失性存储装置
公开(公告)号：US07283408B2
公开(公告)日：2007-10-16
申请号：US11159303
申请日：2005-06-23
申请人： Tsutomu Nakajima , Satoshi Noda , Kenji Kozakai , Atsushi Tokairin
发明人： Tsutomu Nakajima , Satoshi Noda , Kenji Kozakai , Atsushi Tokairin
IPC分类号： G11C11/34
CPC分类号： G11C29/84 , G11C29/82
摘要： A nonvolatile memory apparatus which need not compare an access address with a faulty address every time for rescuing from any fault is to be provided. The apparatus has memory arrays, data registers for inputting and outputting data to and from the memory arrays, and control circuits. The control circuits, after transferring a plurality of sets of data from the memory arrays to the data registers in response to an instruction to read data, take out rescuing data out of the plurality of sets of data transferred to the data registers, and perform processing to replace with the taken-out rescuing data corresponding faulty addresses on the data register to enable the data on the data register to be supplied to the outside. When any faulty data in the read data are to be replaced with rescuing data on any data register to which data have been transferred from any memory array, read access addresses need not be checked whether or not they are faulty every time an access address is supplied from outside.
摘要翻译：提供不需要每次对任何故障进行抢救的访问地址与故障地址进行比较的非易失性存储装置。该装置具有存储器阵列，用于向存储器阵列输入数据和从存储器阵列输出数据的数据寄存器以及控制电路。控制电路在响应于读取数据的指令将多组数据从存储器阵列传送到数据寄存器之后，从传送到数据寄存器的多组数据中取出拯救数据，并执行处理取代数据寄存器上相应的故障地址的取出救援数据，使数据寄存器上的数据能够提供给外部。当数据从任何存储器阵列传送到任何数据寄存器上时，读取数据中的任何有故障的数据将被替换为数据寄存器中的数据，每次提供访问地址时，不需要检查读取访问地址是否有故障从外面。

8. 发明授权

US07515450B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07515450B2
公开(公告)日：2009-04-07
申请号：US11802168
申请日：2007-05-21
申请人： Tsutomu Nakajima , Keiichi Yoshida
发明人： Tsutomu Nakajima , Keiichi Yoshida
IPC分类号： G11C5/02
CPC分类号： G11C11/412 , G11C11/5642 , G11C16/26
摘要： A flash memory 1 based on the multilevel storage technology for storing the information of two or more bits is provided with four banks 2a to 2d. For example, in the left side of the bank 2a, a data latch 6a is provided along one short side of the bank 2a, while in the right side thereof, a data latch 6b is provided along the other short side of the bank 2a. At the lower side of the data latches 6a, 6b, arithmetic circuits 7a, 7b are provided. The data latches 6a, 6b are respectively formed of SRAMs. A sense latch 5a is divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latch 5a is connected with the data latches 6a, 6b via the signal lines respectively allocated along both short sides of the bank 2a.
摘要翻译：基于用于存储两个或更多位的信息的多级存储技术的闪速存储器1具有四个存储体2a至2d。例如，在存储体2a的左侧，沿着存储体2a的一个短边设置有数据锁存器6a，而在右侧，沿着存储体2a的另一个短边设置数据锁存器6b。在数据锁存器6a，6b的下侧设有运算电路7a，7b。数据锁存器6a，6b分别由SRAM形成。感测闩锁5a相对于感测闩锁行的中心在左右方向上分为一半。分频检测锁存器5a经由分别沿着存储体2a的两个短边分配的信号线与数据锁存器6a，6b相连。

9. 发明申请

US20080246963A1 PARTICLE COUNTING METHOD 有权
标题翻译：粒子计数法
公开(公告)号：US20080246963A1
公开(公告)日：2008-10-09
申请号：US12062871
申请日：2008-04-04
申请人： Tsutomu Nakajima
发明人： Tsutomu Nakajima
IPC分类号： G01N15/02
CPC分类号： G01N15/0205
摘要： A particle counting method is provided whereby a liquid sample is radiated by a laser light, scattered light produced by causing the laser light to hit a particle in the liquid sample is detected by a photoelectric conversion element, and a sample value which is the output of the photoelectric conversion element is sequentially compared to a threshold preset for each particle size range, thereby counting the number of particles for each particle size range, the method comprising: a timer start-up step for starting a timer of a predetermined time when the sample value becomes smaller than a threshold of a minimum particle size for the first time and for sequentially holding the maximum value of the sample value; and a timer extension step for restarting the timer to sequentially hold the maximum value of the sample value when the sample value at the time-out of the timer start-up step is larger than the threshold of the minimum particle size.
摘要翻译：提供一种粒子计数方法，通过激光照射液体样品，通过光电转换元件检测使得激光撞击液体样品中的颗粒而产生的散射光，并将作为输出的样品值将光电转换元件顺序地与针对每个粒度范围预设的阈值进行比较，从而对每个粒度范围的粒子数进行计数，该方法包括：定时器启动步骤，用于在样本值变得小于第一次的最小粒径的阈值，并且顺序地保持样本值的最大值; 以及定时器延长步骤，用于当所述定时器启动步骤超时时的所述采样值大于所述最小粒度的阈值时，重新启动所述定时器以顺序保持所述采样值的最大值。

10. 发明申请

US20070118739A1 Certificate issuance server and certification system for certifying operating environment 审中-公开
标题翻译：证书颁发服务器和认证系统，用于认证操作环境
公开(公告)号：US20070118739A1
公开(公告)日：2007-05-24
申请号：US10580952
申请日：2004-12-22
申请人： Masataka Togashi , Tsugihiko Ono , Tsutomu Nakajima
发明人： Masataka Togashi , Tsugihiko Ono , Tsutomu Nakajima
IPC分类号： H04L9/00
CPC分类号： G06Q10/10 , H04L9/3263 , H04L9/3297 , H04L2209/56 , H04L2209/60 , H04L2209/805
摘要： It is an object to provide a certification system designed for security patrol, for example, that certifies a patrolled time and a patrolled site in security patrol rounds. It is another object to certify the time when an image was taken and the site where the image was taken, for example, by attaching information about certified time and certified site to the image. The certification system includes a GPS satellite 10 that supplies location information on the earth, a weather satellite 20 that supplies weather information on the earth, information processing equipment 30 that is carried in security patrol rounds, a certificate issuing server 40 that certifies time information and location information, an information storage server 50 that stores certified time information and certified location information as well as an image with the certified time information and certified location information attached thereto, a verification unit 60 that verifies the time when the image was taken and the site where the image was taken, and a network 70 that interconnects the information processing equipment 30, the certificate issuing server 40, the information storage server 50, and the verification unit 60.
摘要翻译：目的是提供一个为安全巡逻而设计的认证系统，例如，在安全巡逻中证明巡逻时间和巡逻地点。另一个对象是证明拍摄图像的时间和拍摄图像的位置，例如，通过将关于认证时间和认证的站点的信息附加到图像上。该认证系统包括提供地球上的位置信息的GPS卫星10，在地球上提供天气信息的气象卫星20，安全巡逻中携带的信息处理设备30，证明时间信息的证书发行服务器40以及位置信息，存储认证时间信息和认证位置信息的信息存储服务器50以及附有经认证的时间信息和认证位置信息的图像，验证图像拍摄时间和验证单元60的图像拍摄图像的位置以及将信息处理设备30，证书发行服务器40，信息存储服务器50和验证单元60互连的网络70。

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