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21. 发明授权

US08809115B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08809115B2
公开(公告)日：2014-08-19
申请号：US13207449
申请日：2011-08-11
申请人： Kengo Akimoto , Masashi Tsubuku
发明人： Kengo Akimoto , Masashi Tsubuku
IPC分类号： H01L21/00 , H01L29/786 , H01L21/324 , H01L21/447 , H01L21/02 , H01L27/12
CPC分类号： H01L29/66742 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/324 , H01L21/447 , H01L27/1225 , H01L27/127 , H01L29/7869
摘要： To provide a method for manufacturing a thin film transistor in which contact resistance between an oxide semiconductor layer and source and drain electrode layers is small, the surfaces of the source and drain electrode layers are subjected to sputtering treatment with plasma and an oxide semiconductor layer containing In, Ga, and Zn is formed successively over the source and drain electrode layers without exposure of the source and drain electrode layers to air.
摘要翻译：为了提供一种制造薄膜晶体管的方法，其中氧化物半导体层和源极和漏极电极层之间的接触电阻很小，源极和漏极电极层的表面用等离子体和含有氧化物半导体层的氧化物半导体层进行溅射处理 In，Ga和Zn依次形成在源极和漏极电极层上，而不会将源极和漏极电极层暴露于空气。

22. 发明授权

US08481377B2 Method for manufacturing a semiconductor device with impurity doped oxide semiconductor 有权
标题翻译：制造具有杂质掺杂氧化物半导体的半导体器件的方法
公开(公告)号：US08481377B2
公开(公告)日：2013-07-09
申请号：US13026518
申请日：2011-02-14
申请人： Kengo Akimoto , Ryosuke Watanabe , Masashi Tsubuku , Shunpei Yamazaki
发明人： Kengo Akimoto , Ryosuke Watanabe , Masashi Tsubuku , Shunpei Yamazaki
IPC分类号： H01L21/338
CPC分类号： H01L29/7869 , H01L29/41733 , H01L29/66969 , H01L29/78618
摘要： It is an object to provide a semiconductor device including an oxide semiconductor, in which miniaturization of a transistor is achieved and the concentration of an electric field is relieved. The width of a gate electrode is reduced and a space between a source electrode layer and a drain electrode layer is shortened. By adding a rare gas in a self-alignment manner with the use of a gate electrode as a mask, a low-resistance region in contact with a channel formation region can be provided in an oxide semiconductor layer. Accordingly, even when the width of the gate electrode, that is, the line width of a gate wiring is small, the low-resistance region can be provided with high positional accuracy, so that miniaturization of a transistor can be realized.
摘要翻译：本发明的目的是提供一种包括氧化物半导体的半导体器件，其中实现了晶体管的小型化和电场的集中。栅电极的宽度减小，源电极层和漏电极层之间的间隔缩短。通过使用栅电极作为掩模以自对准的方式添加稀有气体，可以在氧化物半导体层中提供与沟道形成区域接触的低电阻区域。因此，即使栅电极的宽度，即栅极配线的线宽小，也能够提供高电位区域的高位置精度，能够实现晶体管的小型化。

23. 发明授权

US08319216B2 Semiconductor device and method for manufacturing the semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08319216B2
公开(公告)日：2012-11-27
申请号：US12612711
申请日：2009-11-05
申请人： Kengo Akimoto , Masashi Tsubuku
发明人： Kengo Akimoto , Masashi Tsubuku
IPC分类号： H01L29/10
CPC分类号： H01L29/7869 , H01L27/1225 , H01L29/42384 , H01L29/66969
摘要： It is disclosed that a semiconductor device includes an oxide semiconductor layer provided over a gate insulating layer, a source electrode layer, and a drain electrode layer, in which a thickness of the gate insulating layer located in a region between the source electrode layer and the drain electrode layer is smaller than a thickness of the gate insulating layer provided between the gate electrode layer and at least one of the source electrode layer and the drain electrode layer.
摘要翻译：公开了半导体器件包括设置在栅极绝缘层，源极电极层和漏极电极层上的氧化物半导体层，其中栅极绝缘层的厚度位于源极电极层和源极电极层之间的区域中漏极电极层的厚度小于设置在栅电极层与源极电极层和漏极电极层中的至少一个之间的栅极绝缘层的厚度。

24. 发明授权

US08218099B2 Liquid crystal display device and method for manufacturing the same 有权
标题翻译：液晶显示装置及其制造方法
公开(公告)号：US08218099B2
公开(公告)日：2012-07-10
申请号：US12871162
申请日：2010-08-30
申请人： Shunpei Yamazaki , Masayuki Sakakura , Junichiro Sakata , Masashi Tsubuku , Kengo Akimoto , Miyuki Hosoba , Yoshiaki Oikawa
发明人： Shunpei Yamazaki , Masayuki Sakakura , Junichiro Sakata , Masashi Tsubuku , Kengo Akimoto , Miyuki Hosoba , Yoshiaki Oikawa
IPC分类号： G02F1/136
CPC分类号： H01L27/1225
摘要： An object is to provide an active matrix liquid crystal display device in which plural kinds of circuits are formed over one substrate and plural kinds of thin film transistors are provided corresponding to characteristics of the plural kinds of circuits. An inverted-coplanar thin film transistor including an oxide semiconductor layer which is over and overlaps with a source electrode layer and a drain electrode layer is used for a pixel thin film transistor. A channel-protective thin film transistor is used for a driver-circuit thin film transistor is used. In addition, main parts of the pixel thin film transistor are formed using a light-transmitting material, so that the aperture ratio is increased.
摘要翻译：本发明提供一种有源矩阵液晶显示装置，其中在一个基板上形成多种电路，并且根据多种电路的特性设置多种薄膜晶体管。包括与源电极层和漏电极层重叠的氧化物半导体层的倒共面薄膜晶体管用于像素薄膜晶体管。使用通道保护薄膜晶体管用于驱动电路薄膜晶体管。此外，使用透光材料形成像素薄膜晶体管的主要部分，使得开口率增加。

25. 发明授权

US08021916B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08021916B2
公开(公告)日：2011-09-20
申请号：US12549603
申请日：2009-08-28
申请人： Kengo Akimoto , Masashi Tsubuku
发明人： Kengo Akimoto , Masashi Tsubuku
IPC分类号： H01L21/00
CPC分类号： H01L29/66742 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/324 , H01L21/447 , H01L27/1225 , H01L27/127 , H01L29/7869
摘要： To provide a method for manufacturing a thin film transistor in which contact resistance between an oxide semiconductor layer and source and drain electrode layers is small, the surfaces of the source and drain electrode layers are subjected to sputtering treatment with plasma and an oxide semiconductor layer containing In, Ga, and Zn is formed successively over the source and drain electrode layers without exposure of the source and drain electrode layers to air.
摘要翻译：为了提供一种制造薄膜晶体管的方法，其中氧化物半导体层和源极和漏极电极层之间的接触电阻很小，源极和漏极电极层的表面用等离子体和含有氧化物半导体层的氧化物半导体层进行溅射处理 In，Ga和Zn依次形成在源极和漏极电极层上，而不会将源极和漏极电极层暴露于空气。

26. 发明授权

US09799773B2 Transistor and semiconductor device 有权
公开(公告)号：US09799773B2
公开(公告)日：2017-10-24
申请号：US13358556
申请日：2012-01-26
申请人： Hiromichi Godo , Satoshi Kobayashi , Masashi Tsubuku
发明人： Hiromichi Godo , Satoshi Kobayashi , Masashi Tsubuku
IPC分类号： H01L29/78 , H01L29/786 , H01L29/423
CPC分类号： H01L29/7869 , H01L29/42384
摘要： A transistor which withstands a high voltage and controls large electric power can be provided. A transistor is provided which includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer which is over the gate insulating layer and overlaps with the gate electrode, and a source electrode and a drain electrode which are in contact with the oxide semiconductor layer and whose end portions overlap with the gate electrode. The gate insulating layer includes a first region overlapping with the end portion of the drain electrode and a second region adjacent to the first region. The first region has smaller capacitance than the second region.

27. 发明授权

US09437743B2 Thin film element, semiconductor device, and method for manufacturing the same 有权
标题翻译：薄膜元件，半导体器件及其制造方法
公开(公告)号：US09437743B2
公开(公告)日：2016-09-06
申请号：US13237191
申请日：2011-09-20
申请人： Takafumi Mizoguchi , Kojiro Shiraishi , Masashi Tsubuku
发明人： Takafumi Mizoguchi , Kojiro Shiraishi , Masashi Tsubuku
IPC分类号： H01L29/786 , H01L21/764 , H01L27/12
CPC分类号： H01L29/78606 , H01L21/764 , H01L27/1225 , H01L27/1288 , H01L29/24 , H01L29/7869 , H01L29/78696
摘要： An object is to provide a method for manufacturing a semiconductor device without exposing a specific layer to moisture or the like at all. A thin film element is manufactured in such a manner that a first film, a second film, and a third film are stacked in this order; a resist mask is formed over the third film; a mask layer is formed by etching the third film with the use of the resist mask; the resist mask is removed; a second layer and a first layer are formed by performing dry etching on the second film and the first film with the use of the mask layer; a fourth film is formed to cover at least the second layer and the first layer; and sidewall layers are formed to cover at least the entire side surfaces of the first layer by performing etch back on the fourth film.
摘要翻译：本发明的目的是提供一种制造半导体器件的方法，而不会将特定层暴露于湿气等。制造薄膜元件，使得第一膜，第二膜和第三膜按此顺序堆叠; 在第三膜上形成抗蚀剂掩模; 通过使用抗蚀剂掩模蚀刻第三膜来形成掩模层; 去除抗蚀剂掩模; 通过使用掩模层对第二膜和第一膜进行干蚀刻来形成第二层和第一层; 形成第四膜至少覆盖第二层和第一层; 并且通过在第四膜上进行回蚀而形成侧壁层以至少覆盖第一层的整个侧表面。

28. 发明授权

US09082858B2 Transistor including an oxide semiconductor and display device using the same 有权
标题翻译：包括氧化物半导体的晶体管和使用其的显示装置
公开(公告)号：US09082858B2
公开(公告)日：2015-07-14
申请号：US13026511
申请日：2011-02-14
申请人： Masashi Tsubuku , Kosei Noda
发明人： Masashi Tsubuku , Kosei Noda
IPC分类号： H01L29/12 , H01L27/15 , H01L29/786 , H01L27/12
CPC分类号： H01L29/7869 , H01L27/1225 , H01L27/156
摘要： The band tail state and defects in the band gap are reduced as much as possible, whereby optical absorption of energy which is in the vicinity of the band gap or less than or equal to the band gap is reduced. In that case, not by merely optimizing conditions of manufacturing an oxide semiconductor film, but by making an oxide semiconductor to be a substantially intrinsic semiconductor or extremely close to an intrinsic semiconductor, defects on which irradiation light acts are reduced and the effect of light irradiation is reduced essentially. That is, even in the case where light with a wavelength of 350 nm is delivered at 1×1013 photons/cm2·sec, a channel region of a transistor is formed using an oxide semiconductor, in which the absolute value of the amount of the variation in the threshold voltage is less than or equal to 0.65 V.
摘要翻译：频带尾部状态和带隙中的缺陷尽可能地减小，由此减小了在带隙附近或小于或等于带隙的能量的光吸收。在这种情况下，不是仅通过优化氧化物半导体膜的制造条件，而是通过使氧化物半导体成为本质上的本征半导体，或者非常接近本征半导体，减少照射光的作用的缺陷和光照射基本上减少了。也就是说，即使在以1×1013个光子/ cm 2·sec传递波长为350nm的光的情况下，也可以使用氧化物半导体形成晶体管的沟道区域，其中，阈值电压的变化小于或等于0.65 V.

29. 发明授权

US08625085B2 Defect evaluation method for semiconductor 有权
标题翻译：半导体缺陷评估方法
公开(公告)号：US08625085B2
公开(公告)日：2014-01-07
申请号：US13407943
申请日：2012-02-29
申请人： Ryosuke Watanabe , Masashi Tsubuku , Takayuki Inoue
发明人： Ryosuke Watanabe , Masashi Tsubuku , Takayuki Inoue
IPC分类号： G01N21/00
CPC分类号： H01L22/14 , H01L22/12
摘要： Even in the case of a sample exhibiting low photoresponse, such as a wide bandgap semiconductor, a measurement method which enables highly accurate CPM measurement is provided. When CPM measurement is performed, photoexcited carriers which are generated by light irradiation of a sample exhibiting low photoresponse such as a wide bandgap semiconductor are instantly removed by application of positive bias voltage to a third electrode which is provided in the sample in addition to two electrodes used for measurement. When the photoexcited carriers are removed, even in the case of the sample exhibiting low photoresponse, the controllability of a photocurrent value is improved and CPM measurement can be performed accurately.
摘要翻译：即使在具有低光响应的样品（例如宽带隙半导体）的情况下，也提供了能够进行高度精确的CPM测量的测量方法。当进行CPM测量时，通过向除了两个电极之外的样品中提供的第三电极施加正偏置电压，立即除去通过光照射出具有低光响应的样品（例如宽带隙半导体）产生的光激发载流子用于测量。当除去光激发载体时，即使在样品表现出较低的光响应的情况下，光电流值的可控性得到改善，也可以精确地进行CPM测量。

30. 发明授权

US08400187B2 Logic circuit and semiconductor device 有权
标题翻译：逻辑电路和半导体器件
公开(公告)号：US08400187B2
公开(公告)日：2013-03-19
申请号：US12901057
申请日：2010-10-08
申请人： Shunpei Yamazaki , Jun Koyama , Masashi Tsubuku , Kosei Noda
发明人： Shunpei Yamazaki , Jun Koyama , Masashi Tsubuku , Kosei Noda
IPC分类号： H01L25/00 , H03K19/094 , H03B1/00
CPC分类号： H01L29/7869 , H01L22/34 , H01L27/0207 , H01L27/1225 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.
摘要翻译：逻辑电路包括具有使用氧化物半导体形成的沟道形成区域的薄膜晶体管，以及通过关闭薄膜晶体管而使端子中的一个成为浮置状态的电容器。氧化物半导体的氢浓度为5×1019（原子/ cm3）以下，因此在不产生电场的状态下基本上用作绝缘体。因此，可以减小薄膜晶体管的截止电流，从而通过薄膜晶体管抑制存储在电容器中的电荷的泄漏。因此，可以防止逻辑电路的故障。此外，可以通过减小薄膜晶体管的截止电流来降低在逻辑电路中流动的过量的电流，导致逻辑电路的低功耗。

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