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1. 发明授权

US08625085B2 Defect evaluation method for semiconductor 有权
标题翻译：半导体缺陷评估方法
公开(公告)号：US08625085B2
公开(公告)日：2014-01-07
申请号：US13407943
申请日：2012-02-29
申请人： Ryosuke Watanabe , Masashi Tsubuku , Takayuki Inoue
发明人： Ryosuke Watanabe , Masashi Tsubuku , Takayuki Inoue
IPC分类号： G01N21/00
CPC分类号： H01L22/14 , H01L22/12
摘要： Even in the case of a sample exhibiting low photoresponse, such as a wide bandgap semiconductor, a measurement method which enables highly accurate CPM measurement is provided. When CPM measurement is performed, photoexcited carriers which are generated by light irradiation of a sample exhibiting low photoresponse such as a wide bandgap semiconductor are instantly removed by application of positive bias voltage to a third electrode which is provided in the sample in addition to two electrodes used for measurement. When the photoexcited carriers are removed, even in the case of the sample exhibiting low photoresponse, the controllability of a photocurrent value is improved and CPM measurement can be performed accurately.
摘要翻译：即使在具有低光响应的样品（例如宽带隙半导体）的情况下，也提供了能够进行高度精确的CPM测量的测量方法。当进行CPM测量时，通过向除了两个电极之外的样品中提供的第三电极施加正偏置电压，立即除去通过光照射出具有低光响应的样品（例如宽带隙半导体）产生的光激发载流子用于测量。当除去光激发载体时，即使在样品表现出较低的光响应的情况下，光电流值的可控性得到改善，也可以精确地进行CPM测量。

2. 发明授权

US08481377B2 Method for manufacturing a semiconductor device with impurity doped oxide semiconductor 有权
标题翻译：制造具有杂质掺杂氧化物半导体的半导体器件的方法
公开(公告)号：US08481377B2
公开(公告)日：2013-07-09
申请号：US13026518
申请日：2011-02-14
申请人： Kengo Akimoto , Ryosuke Watanabe , Masashi Tsubuku , Shunpei Yamazaki
发明人： Kengo Akimoto , Ryosuke Watanabe , Masashi Tsubuku , Shunpei Yamazaki
IPC分类号： H01L21/338
CPC分类号： H01L29/7869 , H01L29/41733 , H01L29/66969 , H01L29/78618
摘要： It is an object to provide a semiconductor device including an oxide semiconductor, in which miniaturization of a transistor is achieved and the concentration of an electric field is relieved. The width of a gate electrode is reduced and a space between a source electrode layer and a drain electrode layer is shortened. By adding a rare gas in a self-alignment manner with the use of a gate electrode as a mask, a low-resistance region in contact with a channel formation region can be provided in an oxide semiconductor layer. Accordingly, even when the width of the gate electrode, that is, the line width of a gate wiring is small, the low-resistance region can be provided with high positional accuracy, so that miniaturization of a transistor can be realized.
摘要翻译：本发明的目的是提供一种包括氧化物半导体的半导体器件，其中实现了晶体管的小型化和电场的集中。栅电极的宽度减小，源电极层和漏电极层之间的间隔缩短。通过使用栅电极作为掩模以自对准的方式添加稀有气体，可以在氧化物半导体层中提供与沟道形成区域接触的低电阻区域。因此，即使栅电极的宽度，即栅极配线的线宽小，也能够提供高电位区域的高位置精度，能够实现晶体管的小型化。

3. 发明授权

US08492758B2 Oxide semiconductor film and semiconductor device 有权
公开(公告)号：US08492758B2
公开(公告)日：2013-07-23
申请号：US12887646
申请日：2010-09-22
申请人： Shunpei Yamazaki , Masayuki Sakakura , Ryosuke Watanabe , Junichiro Sakata , Kengo Akimoto , Akiharu Miyanaga , Takuya Hirohashi , Hideyuki Kishida
发明人： Shunpei Yamazaki , Masayuki Sakakura , Ryosuke Watanabe , Junichiro Sakata , Kengo Akimoto , Akiharu Miyanaga , Takuya Hirohashi , Hideyuki Kishida
IPC分类号： H01L29/12
CPC分类号： H01L29/78696 , H01L21/2636 , H01L27/1225 , H01L29/04 , H01L29/045 , H01L29/12 , H01L29/24 , H01L29/41733 , H01L29/66969 , H01L29/7869
摘要： It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.

4. 发明授权

US07776656B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07776656B2
公开(公告)日：2010-08-17
申请号：US11491037
申请日：2006-07-24
申请人： Ryosuke Watanabe , Daiki Yamada
发明人： Ryosuke Watanabe , Daiki Yamada
IPC分类号： H01L21/00
CPC分类号： G06K19/07749 , H01L23/49855 , H01L27/12 , H01L27/1266 , H01L27/1292 , H01L27/13 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device which is excellent in chemical and physical strength and circumstance resistance is provided. A first stacked film including a first base material and a first adhesive layer is adhered so as to cover one surface of a stacked body including an integrated circuit, the stacked body is sealed by adhering a second stacked film including a second base material and a second adhesive layer so as to cover the other surface of the stacked body, and the first stacked film and the second stacked film are cut. Then, a side surface of the first stacked film and the second stacked film, which is exposed by the cutting, is irradiated with laser light.
摘要翻译：提供了具有优异的化学和物理强度和环境阻力的半导体器件。将包括第一基材和第一粘合剂层的第一叠层膜粘合以覆盖包括集成电路的层叠体的一个表面，通过将包括第二基材和第二基材的第二叠层膜粘合粘合剂层以覆盖层叠体的另一面，并且切割第一层叠膜和第二层叠膜。然后，用激光照射通过切割曝光的第一层叠膜和第二层叠膜的侧面。

5. 发明申请

US20080042168A1 Laminating System, Ic Sheet, Scroll of Ic Sheet, and Method for Manufacturing Ic Chip 有权
标题翻译：叠片系统，Ic薄片，Ic薄片卷，和Ic芯片制造方法
公开(公告)号：US20080042168A1
公开(公告)日：2008-02-21
申请号：US11631688
申请日：2005-07-28
申请人： Ryosuke Watanabe , Naoto Kusumoto , Osamu Nakamura
发明人： Ryosuke Watanabe , Naoto Kusumoto , Osamu Nakamura
IPC分类号： H01L27/10 , B29C65/00 , B32B37/00
CPC分类号： H01L27/1266 , B32B37/0053 , B32B37/226 , B32B2425/00 , G06K19/077 , G06K19/07718 , H01L24/86 , H01L27/1214 , H01L2224/7965 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01049 , H01L2924/01056 , H01L2924/0106 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/04953 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/00
摘要： Thin film integrated circuits are peeled from a substrate and the peeled thin film integrated circuits are sealed, efficiently in order to improve manufacturing yields. The present invention provides laminating system comprising transporting means for transporting a substrate provided with a plurality of thin film integrated circuits; first peeling means for bonding first surfaces of the thin film integrated circuits to a first sheet member to peel the thin film integrated circuits from the substrate; second peeling means for bonding second surfaces of the thin film integrated circuits to a second sheet member to peel the thin film integrated circuits from the first sheet member; and sealing means for interposing the thin film integrated circuits between the second sheet member and a third sheet member to seal the thin film integrated circuit with the second sheet member and the third sheet member.
摘要翻译：薄膜集成电路从基板剥离，并且剥离的薄膜集成电路被有效地密封以提高制造成品率。本发明提供了一种层叠体系，其包括用于输送设置有多个薄膜集成电路的基板的输送机构; 第一剥离装置，用于将薄膜集成电路的第一表面接合到第一片状部件，以从基板剥离薄膜集成电路; 第二剥离装置，用于将薄膜集成电路的第二表面接合到第二片状部件，以将薄膜集成电路从第一片状部件剥离; 以及密封装置，用于将所述薄膜集成电路插入所述第二片状部件和第三片状部件之间，以与所述第二片状部件和所述第三片状部件密封所述薄膜集成电路。

6. 发明授权

US08309961B2 Semiconductor device, display device, and electronic appliance 有权
标题翻译：半导体装置，显示装置和电子设备
公开(公告)号：US08309961B2
公开(公告)日：2012-11-13
申请号：US12897419
申请日：2010-10-04
申请人： Shunpei Yamazaki , Masayuki Sakakura , Ryosuke Watanabe , Junichiro Sakata , Kengo Akimoto , Akiharu Miyanaga , Takuya Hirohashi , Hideyuki Kishida
发明人： Shunpei Yamazaki , Masayuki Sakakura , Ryosuke Watanabe , Junichiro Sakata , Kengo Akimoto , Akiharu Miyanaga , Takuya Hirohashi , Hideyuki Kishida
IPC分类号： H01L29/04
CPC分类号： H01L29/7869 , H01L27/1225 , H01L29/045 , H01L29/45 , H01L29/78606 , H01L29/78696
摘要： In a channel protected thin film transistor in which a channel formation region is formed using an oxide semiconductor, an oxide semiconductor layer which is dehydrated or dehydrogenated by a heat treatment is used as an active layer, a crystal region including nanocrystals is included in a superficial portion in the channel formation region, and the rest portion is amorphous or is formed of a mixture of amorphousness/non-crystals and microcrystals, where an amorphous region is dotted with microcrystals. By using an oxide semiconductor layer having such a structure, a change to an n-type caused by entry of moisture or elimination of oxygen to or from the superficial portion and generation of a parasitic channel can be prevented and a contact resistance with a source and drain electrodes can be reduced.
摘要翻译：在使用氧化物半导体形成沟道形成区域的沟道保护薄膜晶体管中，使用通过热处理脱水或脱氢的氧化物半导体层作为有源层，包括纳米晶体的晶体区域包含在表面并且其余部分是无定形的或由非晶/非晶体和微晶体的混合物形成，其中非晶区域用微晶点缀。通过使用具有这种结构的氧化物半导体层，可以防止由于进入水分或从表面部分去除氧气或从表面部分排出而引起的n型变化和产生寄生通道，并且与源极接触电阻可以减少漏电极。

7. 发明授权

US08123896B2 Laminating system 有权
标题翻译：复合系统
公开(公告)号：US08123896B2
公开(公告)日：2012-02-28
申请号：US11596582
申请日：2005-05-31
申请人： Ryosuke Watanabe , Hidekazu Takahashi , Takuya Tsurume
发明人： Ryosuke Watanabe , Hidekazu Takahashi , Takuya Tsurume
IPC分类号： B29C65/22 , B29C65/56 , B32B37/06 , B32B37/10 , B32B37/14 , B30B15/34 , B32B37/04 , B32B37/18 , B30B5/02
CPC分类号： H01L21/56 , B32B37/20 , B32B2305/342 , B42D25/45 , B42D2033/46 , G06K19/07718 , G06K19/07749 , G06K19/0775 , H01L21/67126 , H01L21/67132 , H01L21/67144 , H01L21/6835 , H01L27/1214 , H01L27/1266 , H01L2221/68318 , H01L2221/68354 , H01L2221/68363 , H01L2924/0002 , Y10T156/1089 , Y10T156/1093 , Y10T156/1712 , H01L2924/00
摘要： It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it easier to handle the thin film integrated circuit. The invention provides a laminating system in which rollers are used for supplying a substrate for sealing, receiving IC chips, separating, and sealing. The separation, sealing, and reception of a plurality of thin film integrated circuits can be carried out continuously by rotating the rollers; thus, the production efficiency can be extremely improved. Further, the thin film integrated circuits can be easily sealed since a pair of rollers opposite to each other is used.
摘要翻译：本发明的目的是提高密封薄膜集成电路的生产效率并防止损坏和断裂。此外，本发明的另一个目的是防止薄膜集成电路在运输中受损，并且使得更容易处理薄膜集成电路。本发明提供了一种层压系统，其中辊子用于供应用于密封的基板，接收IC芯片，分离和密封。通过旋转辊可以连续地进行多个薄膜集成电路的分离，密封和接收; 从而可以极大地提高生产效率。此外，由于使用了彼此相对的一对辊，所以能够容易地密封薄膜集成电路。

8. 发明申请

US20090269886A1 Manufacturing Method of Semiconductor Device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20090269886A1
公开(公告)日：2009-10-29
申请号：US11989328
申请日：2006-07-21
申请人： Shunpei Yamazaki , Ryosuke Watanabe , Jun Koyama
发明人： Shunpei Yamazaki , Ryosuke Watanabe , Jun Koyama
IPC分类号： H01L21/768 , H01L21/50
CPC分类号： H01L21/6835 , H01L23/552 , H01L23/60 , H01L24/75 , H01L24/83 , H01L27/1248 , H01L27/1266 , H01L27/13 , H01L2221/68354 , H01L2221/68363 , H01L2221/68368 , H01L2223/6677 , H01L2224/16 , H01L2224/2919 , H01L2224/83101 , H01L2224/83192 , H01L2224/838 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01054 , H01L2924/0106 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/12044 , H01L2924/14 , H01L2924/15788 , H01L2924/19041 , H01L2924/19043 , H01L2924/00
摘要： A manufacturing method of a semiconductor device is provided, which includes a process in which a transistor is formed over a first substrate; a process in which a first insulating layer is formed over the transistor; a process in which a first conductive layer connected to a source or a drain of the transistor is formed; a process in which a second substrate provided with an second insulating layer is arranged so that the first insulating layer is attached to the second insulating layer; a process in which the second insulating layer is separated from the second substrate; and a process in which a third substrate provided with a second conductive layer which functions as an antenna is arranged so that the first conductive layer is electrically connected to the second conductive layer.
摘要翻译：提供一种半导体器件的制造方法，其包括在第一衬底上形成晶体管的工艺; 在晶体管上形成第一绝缘层的工艺; 形成与晶体管的源极或漏极连接的第一导电层的工序; 其中设置有第二绝缘层的第二基板被布置成使得第一绝缘层附接到第二绝缘层的工艺; 第二绝缘层与第二基板分离的工序; 并且其中设置有用作天线的第二导电层的第三衬底被布置成使得第一导电层电连接到第二导电层的工艺。

9. 发明授权

US07495272B2 Semiconductor device having photo sensor element and amplifier circuit 有权
标题翻译：具有光电传感元件和放大电路的半导体器件
公开(公告)号：US07495272B2
公开(公告)日：2009-02-24
申请号：US10952914
申请日：2004-09-30
申请人： Junya Maruyama , Toru Takayama , Masafumi Morisue , Ryosuke Watanabe , Eiji Sugiyama , Susumu Okazaki , Kazuo Nishi , Jun Koyama , Takeshi Osada , Takanori Matsuzaki
发明人： Junya Maruyama , Toru Takayama , Masafumi Morisue , Ryosuke Watanabe , Eiji Sugiyama , Susumu Okazaki , Kazuo Nishi , Jun Koyama , Takeshi Osada , Takanori Matsuzaki
IPC分类号： H01L31/113
CPC分类号： H01L27/1266 , H01L27/1214 , H01L27/1218 , H01L27/14609 , H01L27/14665 , H01L2224/16225
摘要： The area occupied by a photo-sensor element may be reduced and multiple elements may be integrated in a limited area so that the sensor element can have higher output and smaller size. Higher output and miniaturization are achieved by uniting a sensor element using an amorphous semiconductor film (typically an amorphous silicon film) and an output amplifier circuit including a TFT with a semiconductor film having a crystal structure (typically a poly-crystalline silicon film) used as an active layer over a plastic film substrate that can resist the temperature in the process for mounting such as a solder reflow process. A sensor element that can resist bending stress can be obtained.
摘要翻译：可以减少由光传感器元件占据的面积，并且可以在有限的区域中集成多个元件，使得传感器元件可以具有更高的输出和更小的尺寸。通过使用非晶半导体膜（通常为非晶硅膜）的传感器元件和包括具有晶体结构的半导体膜（通常为多晶硅膜）的TFT的输出放大器电路来实现更高的输出和小型化，其被用作在塑料膜基材上的能够抵抗诸如焊料回流工艺的安装过程中的温度的有源层。可以获得能够抵抗弯曲应力的传感器元件。

10. 发明授权

US06526364B2 Method and apparatus for measuring roundness 有权
标题翻译：测量圆度的方法和装置
公开(公告)号：US06526364B2
公开(公告)日：2003-02-25
申请号：US09759248
申请日：2001-01-16
申请人： Yoshiyuki Omori , Ryosuke Watanabe , Atsushi Tsuruta , Syuuzou Ueno , Hideki Shindo
发明人： Yoshiyuki Omori , Ryosuke Watanabe , Atsushi Tsuruta , Syuuzou Ueno , Hideki Shindo
IPC分类号： G01B1508
CPC分类号： G01B21/20 , B23Q17/20
摘要： An eccentricity adjusting motor (83) is provided in eccentricity adjusting device (17) that adjusts an eccentricity in a work. A tilt adjusting motor (86) is also provided in tilt adjusting device (18) that adjusts a tilt of the work. A processor (2) computes the eccentricity and tilt of the work, based on which eccentricity/tilt compensating means (105, 106) control the motors (83, 86) to compensate the eccentricity and tilt of the work.
摘要翻译：偏心调整电动机（83）设置在偏心调整装置（17）中，该偏心调整装置调节工件的偏心度。倾斜调节电机（86）也设置在倾斜调节装置（18）中，该调节装置调节工件的倾斜。基于哪个偏心/倾斜补偿装置（105,106）控制电动机（83,86）来补偿工件的偏心率和倾斜度，处理器（2）计算工件的偏心率和倾斜度。

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