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1. 发明授权

US08400187B2 Logic circuit and semiconductor device 有权
标题翻译：逻辑电路和半导体器件
公开(公告)号：US08400187B2
公开(公告)日：2013-03-19
申请号：US12901057
申请日：2010-10-08
申请人： Shunpei Yamazaki , Jun Koyama , Masashi Tsubuku , Kosei Noda
发明人： Shunpei Yamazaki , Jun Koyama , Masashi Tsubuku , Kosei Noda
IPC分类号： H01L25/00 , H03K19/094 , H03B1/00
CPC分类号： H01L29/7869 , H01L22/34 , H01L27/0207 , H01L27/1225 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.
摘要翻译：逻辑电路包括具有使用氧化物半导体形成的沟道形成区域的薄膜晶体管，以及通过关闭薄膜晶体管而使端子中的一个成为浮置状态的电容器。氧化物半导体的氢浓度为5×1019（原子/ cm3）以下，因此在不产生电场的状态下基本上用作绝缘体。因此，可以减小薄膜晶体管的截止电流，从而通过薄膜晶体管抑制存储在电容器中的电荷的泄漏。因此，可以防止逻辑电路的故障。此外，可以通过减小薄膜晶体管的截止电流来降低在逻辑电路中流动的过量的电流，导致逻辑电路的低功耗。

2. 发明授权

US08421069B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08421069B2
公开(公告)日：2013-04-16
申请号：US12904579
申请日：2010-10-14
申请人： Shunpei Yamazaki , Jun Koyama , Hiroyuki Miyake , Kei Takahashi , Kouhei Toyotaka , Masashi Tsubuku , Kosei Noda , Hideaki Kuwabara
发明人： Shunpei Yamazaki , Jun Koyama , Hiroyuki Miyake , Kei Takahashi , Kouhei Toyotaka , Masashi Tsubuku , Kosei Noda , Hideaki Kuwabara
IPC分类号： H01L29/10 , H01L29/12 , H01L29/04 , H01L31/00 , H01L27/15 , H01L29/26 , H01L31/12 , H01L33/00
CPC分类号： H01L29/7869 , H01L21/84 , H01L23/552 , H01L23/60 , H01L23/66 , H01L25/16 , H01L27/0222 , H01L27/10873 , H01L27/12 , H01L27/1225 , H01L28/20 , H01L28/60 , H01L29/78609 , H01L2223/6677 , H01L2924/0002 , H01L2924/00
摘要： An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized.
摘要翻译：目的是减少用于LSI，CPU或存储器的晶体管的漏电流和寄生电容。包括在LSI，CPU或存储器中的半导体集成电路使用使用氧化物半导体形成的晶体管来制造，所述氧化物半导体是通过从作为电子给体（供体）中除去作为电子给体（供体）的杂质而获得的内在或本质上的半导体氧化物半导体，并且具有比硅半导体更大的能隙，并且形成在半导体衬底上。通过形成在半导体衬底上的晶体管，并且包括具有充分降低的氢浓度的高度净化的氧化物半导体层，可以实现其由漏电流引起的功率消耗低的半导体器件。

3. 发明授权

US10061172B2 Liquid crystal display device and electronic apparatus having the same 有权
公开(公告)号：US10061172B2
公开(公告)日：2018-08-28
申请号：US12904634
申请日：2010-10-14
申请人： Shunpei Yamazaki , Jun Koyama , Hiroyuki Miyake , Masashi Tsubuku , Kosei Noda
发明人： Shunpei Yamazaki , Jun Koyama , Hiroyuki Miyake , Masashi Tsubuku , Kosei Noda
IPC分类号： G09G3/36 , G02F1/1368 , H01L27/12 , H01L29/786
CPC分类号： G02F1/1368 , G09G3/3611 , G09G3/3648 , G09G3/3674 , G09G3/3677 , G09G5/18 , G09G2310/0286 , G09G2320/103 , G09G2330/021 , G09G2330/022 , G09G2330/027 , H01L27/1225 , H01L29/7869
摘要： A liquid crystal display device includes: a driver circuit portion; a pixel portion; a signal generation circuit for generating a control signal for driving the driver circuit portion and an image signal which is supplied to the pixel portion; a memory circuit; a comparison circuit for detecting a difference of image signals for a series of frame periods among image signals stored for respective frame periods in the memory circuit; a selection circuit which selects and outputs the image signals for the series of frame periods when the difference is detected in the comparison circuit; and a display control circuit which supplies the control signal and the image signals output from the selection circuit, to the driver circuit portion when the difference is detected in the comparison circuit, and stops supplying the control signal to the driver circuit portion when the difference is not detected in the comparison circuit.

4. 发明授权

US08854286B2 Liquid crystal display device and electronic device including the liquid crystal display device 有权
标题翻译：液晶显示装置和包括液晶显示装置的电子装置
公开(公告)号：US08854286B2
公开(公告)日：2014-10-07
申请号：US12901023
申请日：2010-10-08
申请人： Shunpei Yamazaki , Ryo Arasawa , Jun Koyama , Masashi Tsubuku , Kosei Noda
发明人： Shunpei Yamazaki , Ryo Arasawa , Jun Koyama , Masashi Tsubuku , Kosei Noda
IPC分类号： G09G3/36 , H01L27/12 , H01L29/786
CPC分类号： G09G3/3614 , G02F1/133553 , G02F1/13439 , G02F1/1368 , G02F2201/123 , G02F2202/10 , G09G3/3648 , G09G3/3677 , G09G2300/08 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , H01L21/02164 , H01L21/02266 , H01L21/02565 , H01L21/02631 , H01L21/467 , H01L21/477 , H01L27/1225 , H01L27/1255 , H01L29/24 , H01L29/42356 , H01L29/45 , H01L29/66969 , H01L29/78648 , H01L29/7869
摘要： In a liquid crystal display device including a plurality of pixels in a display portion and configured to performed display in a plurality of frame periods, each of the frame periods includes a writing period and a holding period, and after an image signal is input to each of the plurality of pixels in the writing period, a transistor included in each of the plurality of pixels is turned off and the image signal is held for at least 30 seconds in the holding period. The pixel includes a semiconductor layer including an oxide semiconductor layer, and the oxide semiconductor layer has a carrier concentration of less than 1×1014/cm3.
摘要翻译：在包括显示部分中的多个像素并且被配置为在多个帧周期中进行显示的液晶显示装置中，每个帧周期包括写入周期和保持周期，并且在将图像信号输入到每个在所述写入周期中的所述多个像素中，包括在所述多个像素中的每一个中的晶体管被截止，并且所述图像信号在所述保持周期中保持至少30秒。像素包括具有氧化物半导体层的半导体层，氧化物半导体层的载流子浓度小于1×10 14 / cm 3。

5. 发明授权

US08242837B2 Analog circuit and semiconductor device 有权
标题翻译：模拟电路和半导体器件
公开(公告)号：US08242837B2
公开(公告)日：2012-08-14
申请号：US12907559
申请日：2010-10-19
申请人： Shunpei Yamazaki , Jun Koyama , Atsushi Hirose , Masashi Tsubuku , Kosei Noda
发明人： Shunpei Yamazaki , Jun Koyama , Atsushi Hirose , Masashi Tsubuku , Kosei Noda
IPC分类号： H01L25/00
CPC分类号： H01L27/1225 , H01L21/823412 , H01L27/124 , H01L27/1255 , H01L27/156 , H01L27/3213 , H01L29/24 , H01L29/36 , H01L29/7869 , H01L29/78693 , H01L33/025 , H01L2924/0002 , H04M1/0266 , H04R1/02 , H01L2924/00
摘要： An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.
摘要翻译：目的是获得使用其中使用氧化物半导体层的薄膜晶体管，在检测信号和宽动态范围中具有高灵敏度的半导体器件。使用具有作为沟道形成层的功能的氧化物半导体的薄膜晶体管形成模拟电路，其氢浓度为5×1019个原子/ cm3以下，并且在该状态下基本上起绝缘体的作用其中不产生电场。因此，可以获得在检测信号中具有高灵敏度和宽动态范围的半导体器件。

6. 发明授权

US08952726B2 Logic circuit and semiconductor device 有权
标题翻译：逻辑电路和半导体器件
公开(公告)号：US08952726B2
公开(公告)日：2015-02-10
申请号：US12902670
申请日：2010-10-12
申请人： Shunpei Yamazaki , Jun Koyama , Masashi Tsubuku , Kosei Noda
发明人： Shunpei Yamazaki , Jun Koyama , Masashi Tsubuku , Kosei Noda
IPC分类号： H03K19/00 , H03K19/0175 , H01L29/04 , H01L29/10 , H01L31/00 , H01L27/12 , G09G3/20 , G09G3/32 , H01L29/786
CPC分类号： H01L27/1255 , G09G3/20 , G09G3/2092 , G09G3/3233 , G09G3/3291 , G09G3/36 , G09G3/3648 , G09G2300/0439 , G09G2300/08 , G09G2300/0842 , G09G2310/0267 , G09G2310/0275 , G09G2310/0286 , G09G2310/08 , G11C19/184 , G11C19/28 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L29/7869 , H03K17/161 , H03K19/00315 , H03K19/096
摘要： To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.
摘要翻译：为了减小晶体管的漏电流，可以抑制逻辑电路的故障。逻辑电路包括晶体管，其包括具有沟道形成层的功能的氧化物半导体层，并且其中截止电流在沟道宽度中为每微米1×10-13A或更小。作为时钟信号的第一信号，第二信号和第三信号被输入作为输入信号。作为输出信号输出第四信号和第五信号，其电压状态根据输入的第一至第三信号而被设定。

7. 发明申请

US20110101331A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110101331A1
公开(公告)日：2011-05-05
申请号：US12904579
申请日：2010-10-14
申请人： Shunpei Yamazaki , Jun Koyama , Hiroyuki Miyake , Kei Takahashi , Kouhei Toyotaka , Masashi Tsubuku , Kosei Noda , Hideaki Kuwabara
发明人： Shunpei Yamazaki , Jun Koyama , Hiroyuki Miyake , Kei Takahashi , Kouhei Toyotaka , Masashi Tsubuku , Kosei Noda , Hideaki Kuwabara
IPC分类号： H01L29/78
CPC分类号： H01L29/7869 , H01L21/84 , H01L23/552 , H01L23/60 , H01L23/66 , H01L25/16 , H01L27/0222 , H01L27/10873 , H01L27/12 , H01L27/1225 , H01L28/20 , H01L28/60 , H01L29/78609 , H01L2223/6677 , H01L2924/0002 , H01L2924/00
摘要： An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized.
摘要翻译：目的是减少用于LSI，CPU或存储器的晶体管的泄漏电流和寄生电容。包括在LSI，CPU或存储器中的半导体集成电路使用使用氧化物半导体形成的晶体管来制造，所述氧化物半导体是通过从作为电子给体（供体）中除去作为电子给体（供体）的杂质而获得的内在或本质上的半导体氧化物半导体，并且具有比硅半导体更大的能隙，并且形成在半导体衬底上。通过形成在半导体衬底上的晶体管，并且包括具有充分降低的氢浓度的高度净化的氧化物半导体层，可以实现其由漏电流引起的功率消耗低的半导体器件。

8. 发明申请

US20110089414A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110089414A1
公开(公告)日：2011-04-21
申请号：US12904565
申请日：2010-10-14
申请人： Shunpei Yamazaki , Jun Koyama , Hiroyuki Miyake , Kei Takahashi , Kouhei Toyotaka , Masashi Tsubuku , Kosei Noda , Hideaki Kuwabara
发明人： Shunpei Yamazaki , Jun Koyama , Hiroyuki Miyake , Kei Takahashi , Kouhei Toyotaka , Masashi Tsubuku , Kosei Noda , Hideaki Kuwabara
IPC分类号： H01L29/12
CPC分类号： H01L29/26 , G06K19/07758 , G11C7/00 , G11C19/28 , H01L21/8236 , H01L23/66 , H01L27/0883 , H01L27/1225 , H01L29/24 , H01L29/66969 , H01L29/78609 , H01L29/7869 , H01L29/78696 , H01L2223/6677 , H02M3/07
摘要： An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.
摘要翻译：目的是减少用于LSI，CPU或存储器的晶体管的泄漏电流和寄生电容。使用薄膜晶体管制造诸如LSI，CPU或存储器的半导体集成电路，其中使用氧化物半导体形成沟道形成区域，该氧化物半导体通过去除作为电子给体的杂质而成为本征或本质上的半导体（供体），并且具有比硅半导体更大的能隙。通过使用具有充分降低的氢浓度的高度净化的氧化物半导体层的薄膜晶体管，可以实现由于漏电流而具有低功耗的半导体器件。

9. 发明授权

US08766608B2 Voltage regulator circuit and semiconductor device, including transistor using oxide semiconductor 有权
标题翻译：电压调节器电路和半导体器件，包括使用氧化物半导体的晶体管
公开(公告)号：US08766608B2
公开(公告)日：2014-07-01
申请号：US12909629
申请日：2010-10-21
申请人： Shunpei Yamazaki , Jun Koyama , Kei Takahashi , Masashi Tsubuku , Kosei Noda
发明人： Shunpei Yamazaki , Jun Koyama , Kei Takahashi , Masashi Tsubuku , Kosei Noda
IPC分类号： G05F1/00 , H01L27/14
CPC分类号： H01L27/1225 , H01L27/1255 , H01L29/7869 , H02M3/07 , H02M3/158
摘要： A voltage regulator circuit includes a transistor and a capacitor. The transistor includes a gate, a source, and a drain, a first signal is inputted to one of the source and the drain, a second signal which is a clock signal is inputted to the gate, an oxide semiconductor layer is used for a channel formation layer, and an off-state current is less than or equal to 10 aA/μm. The capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a high power source voltage and a low power source voltage are alternately applied to the second electrode.
摘要翻译：电压调节器电路包括晶体管和电容器。晶体管包括栅极，源极和漏极，第一信号被输入到源极和漏极中的一个，作为时钟信号的第二信号被输入到栅极，氧化物半导体层被用于沟道形成层，截止电流小于或等于10AA /μm。电容器包括第一电极和第二电极，第一电极电连接到晶体管的源极和漏极中的另一个，并且高电源电压和低电源电压交替施加到第二电极。

10. 发明授权

US08421068B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08421068B2
公开(公告)日：2013-04-16
申请号：US12904565
申请日：2010-10-14
申请人： Shunpei Yamazaki , Jun Koyama , Hiroyuki Miyake , Kei Takahashi , Kouhei Toyotaka , Masashi Tsubuku , Kosei Noda , Hideaki Kuwabara
发明人： Shunpei Yamazaki , Jun Koyama , Hiroyuki Miyake , Kei Takahashi , Kouhei Toyotaka , Masashi Tsubuku , Kosei Noda , Hideaki Kuwabara
IPC分类号： H01L29/10 , H01L29/12 , H01L29/04 , H01L31/00 , H01L27/15 , H01L29/26 , H01L31/12 , H01L33/00
CPC分类号： H01L29/26 , G06K19/07758 , G11C7/00 , G11C19/28 , H01L21/8236 , H01L23/66 , H01L27/0883 , H01L27/1225 , H01L29/24 , H01L29/66969 , H01L29/78609 , H01L29/7869 , H01L29/78696 , H01L2223/6677 , H02M3/07
摘要： An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.
摘要翻译：目的是减少用于LSI，CPU或存储器的晶体管的漏电流和寄生电容。使用薄膜晶体管制造诸如LSI，CPU或存储器的半导体集成电路，其中使用氧化物半导体形成沟道形成区域，该氧化物半导体通过去除作为电子给体的杂质而成为本征或本质上的半导体（供体），并且具有比硅半导体更大的能隙。通过使用具有充分降低的氢浓度的高度净化的氧化物半导体层的薄膜晶体管，可以实现由于漏电流而具有低功耗的半导体器件。

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