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21. 发明授权

US06801449B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06801449B2
公开(公告)日：2004-10-05
申请号：US10781905
申请日：2004-02-20
申请人： Hiroyuki Kobayashi , Mototsugu Hamada
发明人： Hiroyuki Kobayashi , Mototsugu Hamada
IPC分类号： G11C1100
CPC分类号： G11C11/412 , H01L27/1104
摘要： A semiconductor memory device according to an aspect of the present invention includes memory cells each having a data storage section which stores data and a transfer gate section which has a MOSFET of a first conductive type for writing the data to the data storage section and reading the data from the data storage section, wherein a potential corresponding to the data stored in the data storage section is applied as a substrate bias of the MOSFET.
摘要翻译：根据本发明的一个方面的半导体存储器件包括存储单元，每个存储器单元具有存储数据的数据存储部分和传输门极部分，该转移栅极部分具有第一导电类型的MOSFET，用于将数据写入数据存储部分并读取来自数据存储部分的数据，其中应用与存储在数据存储部分中的数据相对应的电位作为MOSFET的衬底偏置。

22. 发明授权

US06714439B2 Semiconductor memory device 失效
公开(公告)号：US06714439B2
公开(公告)日：2004-03-30
申请号：US10154967
申请日：2002-05-28
申请人： Hiroyuki Kobayashi , Mototsugu Hamada
发明人： Hiroyuki Kobayashi , Mototsugu Hamada
IPC分类号： G11C1100
CPC分类号： G11C11/412 , H01L27/1104
摘要： A semiconductor memory device according to an aspect of the present invention includes memory cells each having a data storage section which stores data and a transfer gate section which has a MOSFET of a first conductive type for writing the data to the data storage section and reading the data from the data storage section, wherein a potential corresponding to the data stored in the data storage section is applied as a substrate bias of the MOSFET.

23. 发明授权

US07808017B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07808017B2
公开(公告)日：2010-10-05
申请号：US12697653
申请日：2010-02-01
申请人： Mototsugu Hamada
发明人： Mototsugu Hamada
IPC分类号： H01L27/118
CPC分类号： H01L27/092 , H01L27/0207 , H01L27/11807 , H01L2027/11831
摘要： A semiconductor integrated circuit having a first p-type MOS transistor; a first n-type MOS transistor; a second p-type MOS transistors; a and second n-type MOS transistors having fourth gate electrodes disposed so as to be adjacent to the second diffused regions of the first n-type MOS transistor. The semiconductor integrated circuit further having an absolute value of a threshold voltage of the second p-type MOS transistor being higher than an absolute value of a threshold voltage of the first p-type MOS transistor, and an absolute value of a threshold voltage of the second n-type MOS transistor being higher than an absolute value of a threshold voltage of the first n-type MOS transistor.
摘要翻译：一种具有第一p型MOS晶体管的半导体集成电路; 第一n型MOS晶体管; 第二p型MOS晶体管; 一个和第二个n型MOS晶体管，其具有与第一n型MOS晶体管的第二扩散区相邻设置的第四栅电极。半导体集成电路还具有第二p型MOS晶体管的阈值电压的绝对值高于第一p型MOS晶体管的阈值电压的绝对值，以及阈值电压的绝对值第二n型MOS晶体管高于第一n型MOS晶体管的阈值电压的绝对值。

24. 发明授权

US07675355B2 Semiconductor device that degrades leak current of a transistor 失效
标题翻译：降低晶体管漏电流的半导体器件
公开(公告)号：US07675355B2
公开(公告)日：2010-03-09
申请号：US11758394
申请日：2007-06-05
申请人： Mitsuyuki Ashida , Mototsugu Hamada
发明人： Mitsuyuki Ashida , Mototsugu Hamada
IPC分类号： H03M1/12
CPC分类号： H03K19/0013
摘要： A semiconductor device, has a main transistor that is a first-conductivity-type MOS transistor and has the drain connected to a first potential; a first switch circuit that is connected between the source of said main transistor and a second potential; a dummy transistor that is a first-conductivity-type MOS transistor whose source serves also as the source of said main transistor; and a second switch circuit that is connected between the drain of said dummy transistor and said first potential or said second potential.
摘要翻译：半导体器件具有作为第一导电型MOS晶体管的主晶体管，并且漏极连接到第一电位; 连接在所述主晶体管的源极和第二电位之间的第一开关电路; 作为第一导电型MOS晶体管的虚设晶体管，其源极也用作所述主晶体管的源极; 以及连接在所述虚拟晶体管的漏极与所述第一电位或所述第二电位之间的第二开关电路。

25. 发明申请

US20070285152A1 POWER SUPPLY VOLTAGE CONTROLLING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：电源电压控制电路和半导体集成电路
公开(公告)号：US20070285152A1
公开(公告)日：2007-12-13
申请号：US11758343
申请日：2007-06-05
申请人： Tetsuya FUJITA , Mototsugu Hamada
发明人： Tetsuya FUJITA , Mototsugu Hamada
IPC分类号： G05F1/10
CPC分类号： G05F1/56
摘要： A power supply voltage controlling circuit that controls an output voltage at an output terminal to a desired set voltage, has a voltage regulator circuit that is connected to a first power supply and a second power supply that outputs a higher voltage than said first power supply, supplies a current to said output terminal from at least any of said first power supply and said second power supply, and compares the output voltage at said output terminal with a first reference voltage to adjust said output voltage to approach said first reference voltage; and a controller circuit that supplies said first reference voltage to said voltage regulator circuit and controls said voltage regulator circuit by outputting, to said voltage regulator circuit, at least any of a first enable signal for enabling said first power supply to supply a current to said output terminal and a second enable signal for enabling said second power supply to supply a current to said output terminal.
摘要翻译：将输出端子处的输出电压控制为期望设定电压的电源电压控制电路具有连接到第一电源的电压调节器电路和输出比所述第一电源高的电压的第二电源，从所述第一电源和所述第二电源中的至少一个向所述输出端提供电流，并将所述输出端的输出电压与第一参考电压进行比较，以调整所述输出电压以接近所述第一参考电压; 以及控制器电路，其将所述第一参考电压提供给所述电压调节器电路，并且通过向所述稳压器电路输出至少任一第一使能信号来控制所述电压调节器电路，以使所述第一电源能够向所述电压调节器电路提供电流输出端子和第二使能信号，用于使所述第二电源能够向所述输出端子提供电流。

26. 发明申请

US20070236276A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND SOURCE VOLTAGE/SUBSTRATE BIAS CONTROL CIRCUIT 失效
标题翻译：半导体集成电路和源极电压/基极偏置控制电路
公开(公告)号：US20070236276A1
公开(公告)日：2007-10-11
申请号：US11764605
申请日：2007-06-18
申请人： Tetsuya FUJITA , Mototsugu Hamada , Hiroyuki Hara
发明人： Tetsuya FUJITA , Mototsugu Hamada , Hiroyuki Hara
IPC分类号： H01L29/94
CPC分类号： G05F3/205
摘要： This disclosure concerns a semiconductor integrated circuit that includes a semiconductor substrate, a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other, a plurality of MOS transistors formed in the well regions and a substrate bias generator that applies substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.
摘要翻译：本公开涉及一种半导体集成电路，其包括半导体衬底，形成在半导体衬底的一个表面上并彼此电隔离的多个阱区，形成在阱区中的多个MOS晶体管和衬底偏置发生器，其应用基于实际测量的阈值电压下的MOS晶体管的工艺衍生方差，使各个MOS晶体管的阈值电压与正常阈值电压一致，从而将衬底偏置到各个阱区。

27. 发明授权

US07236035B2 Semiconductor device adapted to minimize clock skew 有权
标题翻译：半导体器件适合于最小化时钟偏移
公开(公告)号：US07236035B2
公开(公告)日：2007-06-26
申请号：US10990537
申请日：2004-11-18
申请人： Shinichiro Shiratake , Yukihito Oowaki , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara
发明人： Shinichiro Shiratake , Yukihito Oowaki , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A first logic circuit has its supply voltage controlled. A second logic circuit operates in response to an external clock signal. An adjustment circuit includes a first delay circuit supplied with the external clock signal, and a detection circuit which detects a skew between timing of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit section. The adjustment circuit adjusts the delay time of the first delay circuit according to the result of the detection by the detection circuit and applies an output signal of the first delay circuit to the first logic circuit as a third clock signal.
摘要翻译：第一个逻辑电路的电源电压被控制。第二逻辑电路响应于外部时钟信号而工作。调整电路包括提供有外部时钟信号的第一延迟电路和检测电路，其检测从第一逻辑电路输出的第一时钟信号的定时与从第二逻辑电路部分输出的第二时钟信号之间的偏差。调整电路根据检测电路的检测结果来调整第一延迟电路的延迟时间，并将第一延迟电路的输出信号作为第三时钟信号施加到第一逻辑电路。

28. 发明申请

US20070024337A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20070024337A1
公开(公告)日：2007-02-01
申请号：US11476106
申请日：2006-06-28
申请人： Chen Teh , Mototsugu Hamada
发明人： Chen Teh , Mototsugu Hamada
IPC分类号： H03K3/017
CPC分类号： H03K3/012 , H03K3/356139
摘要： The semiconductor integrated circuit device is a semiconductor integrated circuit device having a pulse generator and a latch circuit. The pulse generator has a first charge/discharge path and a second charge/discharge path and a charge unit for pre-charging first nodes. The first charge/discharge path and the second charge/discharge path include: two first switching units, connected to the first nodes, and configured to control, according to an input signal, conduction and non-conduction of the first charge/discharge path and the second charge/discharge path; and a second switching unit, disposed between a second node and a reference voltage node, and configured to be turned on in a period prior to capturing the input signal to allow an electric charge accumulated at the second node to be discharged to the reference voltage node, and at the same time, configured to be turned on in a period of capturing the input signal to allow the first node to discharge.
摘要翻译：半导体集成电路器件是具有脉冲发生器和锁存电路的半导体集成电路器件。脉冲发生器具有第一充电/放电路径和第二充电/放电路径以及用于对第一节点进行预充电的充电单元。第一充电/放电路径和第二充电/放电路径包括：两个第一开关单元，连接到第一节点，并且被配置为根据输入信号来控制第一充电/放电路径的导通和非导通，以及第二充电/放电路径; 以及第二开关单元，设置在第二节点和参考电压节点之间，并且被配置为在捕获输入信号之前的周期中导通，以允许在第二节点处累积的电荷被放电到参考电压节点并且同时被配置为在捕获输入信号的时段中导通以允许第一节点放电。

29. 发明申请

US20060198198A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20060198198A1
公开(公告)日：2006-09-07
申请号：US11342617
申请日：2006-01-31
申请人： Tetsuya Fujita , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara , Shinichiro Shiratake
发明人： Tetsuya Fujita , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara , Shinichiro Shiratake
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C5/147
摘要： According to the present invention, there is provided a semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change rate on the basis of the voltage select signal; and a circuit portion which receives the power supply voltage and performs processing, wherein said circuit portion keeps operating while said power supply voltage controller is outputting the power supply voltage generated at the arbitrary voltage change rate.
摘要翻译：根据本发明，提供了一种半导体集成电路，包括：功率控制器，其输出用于选择至少两种类型的电压中的一种的电压选择信号; 电源电压控制器，其基于所述电压选择信号生成并输出任意电压变化率的电源电压; 以及电路部分，其接收电源电压并执行处理，其中所述电路部分在所述电源电压控制器输出以任意电压变化率产生的电源电压的情况下保持操作。

30. 发明授权

US06204707B1 Flip-flop circuit with clock signal control function and clock control circuit 有权
标题翻译：触发电路具有时钟信号控制功能和时钟控制电路
公开(公告)号：US06204707B1
公开(公告)日：2001-03-20
申请号：US09383880
申请日：1999-08-26
申请人： Mototsugu Hamada , Tadahiro Kuroda
发明人： Mototsugu Hamada , Tadahiro Kuroda
IPC分类号： H03K3037
CPC分类号： H03K3/0375 , H03K3/012
摘要： A flip-flop circuit 10 is provided with a discord detecting circuit DDC and a clock control circuit CCC. The discord detecting circuit DDC detects the discord of a data input signal DIS of the flip-flop circuit 10 with a data output signal DOS thereof. When the data input signal DIS discords with the data output signal DOS, the clock control circuit CCC supplies a short pulse to the flip-flop circuit 10 as an internal clock signal ICLK in synchronism with the rising of an external clock signal ECLK. On the other hand, when the data input signal DIS coincides with the data output signal DOS, the clock control circuit CCC supplies a low level signal to the flip-flop circuit 10 as the internal clock signal ICLK. Thus, it is possible to suppress electric power consumption required to supply a clock signal, and to prevent errors from being caused in a flip-flop operation.
摘要翻译：触发电路10具有不对称检测电路DDC和时钟控制电路CCC。不对称检测电路DDC利用其数据输出信号DOS检测触发器电路10的数据输入信号DIS的不一致。当数据输入信号DIS与数据输出信号DOS不一致时，时钟控制电路CCC与外部时钟信号ECLK的上升同步地作为内部时钟信号ICLK向触发器电路10提供短脉冲。另一方面，当数据输入信号DIS与数据输出信号DOS一致时，时钟控制电路CCC将作为内部时钟信号ICLK的低电平信号提供给触发器电路10。因此，可以抑制提供时钟信号所需的电力消耗，并且防止在触发器操作中引起错误。

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