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21. 发明申请

US20090001338A1 Seek-and-scan probe memory devices with nanostructures for improved bit size and resistance contrast when reading and writing to phase-change media 审中-公开
标题翻译：具有纳米结构的寻道扫描探针存储器件，用于在读取和写入相变介质时改善位大小和电阻对比度
公开(公告)号：US20090001338A1
公开(公告)日：2009-01-01
申请号：US11824382
申请日：2007-06-29
申请人： Nathan Franklin , Qing Ma , Valluri R. Rao , Mike Brown , Yang Jiao
发明人： Nathan Franklin , Qing Ma , Valluri R. Rao , Mike Brown , Yang Jiao
IPC分类号： H01L47/00
CPC分类号： G11B9/04 , B82Y10/00 , G11B9/149
摘要： A seek-and-scan probe memory device comprising a patterned capping layer over a phase-change media, where the patterned capping layer defines the bit locations on the phase-change media. The patterned capping layer may be formed from self-assembled structures. In other embodiments, nanostructures are formed on the bottom electrode below the phase-change media to focus an applied electric field from the probe, so as to increase bit density and contrast. The nanostructures may be a regular or random array of nanostructures, formed by using a self-assembling material. The nanostructures may be conductive or non-conductive. Other embodiments are described and claimed.
摘要翻译：寻找和扫描探针存储器件，其包括在相变介质上的图案化覆盖层，其中图案化覆盖层限定相变介质上的位置。图案化封盖层可以由自组装结构形成。在其他实施例中，在相变介质下方的底部电极上形成纳米结构，以将来自探针的施加的电场聚焦，以增加位密度和对比度。纳米结构可以是通过使用自组装材料形成的纳米结构的规则或随机阵列。纳米结构可以是导电的或不导电的。描述和要求保护其他实施例。

22. 发明授权

US06222246B1 Flip-chip having an on-chip decoupling capacitor 有权
标题翻译：倒装芯片具有片上去耦电容
公开(公告)号：US06222246B1
公开(公告)日：2001-04-24
申请号：US09227594
申请日：1999-01-08
申请人： Tak M. Mak , Paul Winer , Valluri R. Rao , Richard H. Livengood
发明人： Tak M. Mak , Paul Winer , Valluri R. Rao , Richard H. Livengood
IPC分类号： H05K702
CPC分类号： H01L23/642 , H01L23/50 , H01L25/16 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05184 , H01L2224/05568 , H01L2224/05569 , H01L2224/0557 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/01079 , H01L2924/15311 , H01L2924/19041 , H01L2924/19104 , H01L2924/19106 , H01L2924/30107 , H05K1/0231 , H05K2201/1053 , H05K2201/10545 , H05K2201/10636 , H05K2201/10734 , Y02P70/611 , H01L2224/05599
摘要： A flip-chip having a decoupling capacitor electrically coupled to the backside thereof. The flip-chip includes a semiconductor substrate having first and second opposing surfaces with circuit elements formed within the first surface. A plurality of raised bump contacts are located on the first surface and connected to the circuit elements. A plurality of electrical interconnects are also located on or within the second surface and connected to the circuit elements. The electrodes of a decoupling capacitor are electrically coupled to the plurality of electrical interconnects.
摘要翻译：具有电耦合到其背面的去耦电容器的倒装芯片。倒装芯片包括具有形成在第一表面内的电路元件的第一和第二相对表面的半导体衬底。多个突出的凸起触头位于第一表面上并连接到电路元件。多个电互连也位于第二表面上或第二表面内并连接到电路元件。去耦电容器的电极电耦合到多个电互连。

23. 发明授权

US5872360A Method and apparatus using an infrared laser based optical probe for measuring electric fields directly from active regions in an integrated circuit 失效
标题翻译：使用基于红外激光的光学探针的方法和装置，用于直接从集成电路中的有源区测量电场
公开(公告)号：US5872360A
公开(公告)日：1999-02-16
申请号：US766149
申请日：1996-12-12
申请人： Mario J. Paniccia , Valluri R. Rao
发明人： Mario J. Paniccia , Valluri R. Rao
IPC分类号： G01R31/309 , G01R31/28
CPC分类号： G01R31/309
摘要： A method and an apparatus for detecting an electric field in the active regions of an integrated circuit disposed in a semiconductor. In one embodiment, a laser beam is operated at a wavelength near the band gap of a semiconductor such as silicon. The laser beam is focused onto a P-N junction, such as for example the drain of an MOS transistor, through the back side of the semiconductor substrate. As a result of photo-absorption, the laser beam is partially absorbed in the P-N junction. When an external electric field is impressed on the P-N junction, such as when for example the drain of the transistor switches, the degree of photo-absorption will be modulated in accordance with the modulation in the electric field due to the phenomenon of electro-absorption. Electro-absorption also leads to electro-refraction which leads to a modulation in the reflection coefficient for the light reflected from the P-N junction/oxide interface. The laser beam passes through the P-N junction region, reflects off the oxide interface and metal behind the junction, and returns back through the P-N junction and back out of the silicon surface. Any amplitude modulation in this reflected laser beam is detected with an optical detection system, and is attributed to a corresponding modulation in the electric field in the P-N junction due to the combined effects of electro-absorption and electro-refraction.
摘要翻译：一种用于检测设置在半导体中的集成电路的有源区域中的电场的方法和装置。在一个实施例中，激光束以接近诸如硅之类的半导体的带隙的波长工作。激光束通过半导体衬底的背面聚焦到P-N结，例如MOS晶体管的漏极。作为光吸收的结果，激光束被部分地吸收在P-N结中。当在PN结上施加外部电场时，例如当例如晶体管开关的漏极时，由于电吸收的现象，将根据电场中的调制来调制光吸收的程度。电吸收也导致电折射，这导致从P-N结/氧化物界面反射的光的反射系数的调制。激光束穿过P-N结区域，从结点后面的氧化物界面和金属反射出来，并通过P-N结返回并返回硅表面。这种反射激光束中的任何幅度调制都用光学检测系统检测，并且归因于由于电吸收和电折射的组合效应而在P-N结中的电场中的相应调制。

24. 发明授权

US10070524B2 Method of making glass core substrate for integrated circuit devices 有权
公开(公告)号：US10070524B2
公开(公告)日：2018-09-04
申请号：US13442092
申请日：2012-04-09
申请人： Qing Ma , Quan A. Tran , Robert L. Sankman , Johanna M. Swan , Valluri R. Rao
发明人： Qing Ma , Quan A. Tran , Robert L. Sankman , Johanna M. Swan , Valluri R. Rao
IPC分类号： H01R43/00 , H05K1/11 , H01L21/48 , H01L23/367 , H01L23/498 , H05K3/46 , H01L23/15 , H05K3/00
CPC分类号： H05K1/112 , H01L21/4803 , H01L21/486 , H01L23/15 , H01L23/3675 , H01L23/49822 , H01L23/49827 , H01L2224/16225 , H01L2224/16227 , H01L2224/32245 , H01L2224/73253 , H01L2924/00014 , H01L2924/10253 , H05K3/0014 , H05K3/4605 , H05K3/4644 , H05K2201/096 , H05K2201/09827 , H05K2201/10287 , H05K2201/10371 , H05K2201/10674 , H05K2203/0108 , H05K2203/0228 , H05K2203/025 , Y10T29/49117 , Y10T29/49126 , Y10T29/49155 , H01L2924/00 , H01L2224/0401
摘要： A glass core substrate for an integrated circuit (IC) device may be formed to include a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.

25. 发明授权

US08816906B2 Chip packages including through-silicon via dice with vertically inegrated phased-array antennas and low-frequency and power delivery substrates 有权
标题翻译：芯片封装包括通过骰子的穿硅，垂直集成的相控阵天线和低频和功率输送基板
公开(公告)号：US08816906B2
公开(公告)日：2014-08-26
申请号：US13101883
申请日：2011-05-05
申请人： Telesphor Kamgaing , Valluri R. Rao , Yorgos Palaskas
发明人： Telesphor Kamgaing , Valluri R. Rao , Yorgos Palaskas
IPC分类号： H01Q3/00
CPC分类号： H01Q3/30 , H01L23/66 , H01L25/0657 , H01L25/16 , H01L25/18 , H01L2223/6677 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2924/15321 , H01Q1/2283 , H01Q9/0414 , H01Q21/065 , H01Q23/00 , Y10T29/49004 , Y10T29/49018
摘要： An apparatus includes a die with through-silicon vias and radio frequency integrated circuit capabilities and it is vertically integrated with a phased-array antenna substrate. The through-silicon via and a radio frequency integrated circuit is coupled to a plurality of antenna elements disposed on the phased-array antenna substrate where each of the plurality of antenna elements is coupled to the through-silicon vias and radio frequency integrated circuit through a plurality of through-silicon vias. A process of assembling the through-silicon vias and radio frequency integrated circuit to the phased-array antenna substrate includes testing the apparatus.
摘要翻译：一种装置包括具有通硅通孔和射频集成电路能力的管芯，并且其与相控阵天线基板垂直集成。穿硅通孔和射频集成电路耦合到布置在相控阵天线基板上的多个天线元件，其中多个天线元件中的每一个天线元件通过一个通孔硅通孔和射频集成电路多个通硅通孔。将穿硅通孔和射频集成电路组装到相控阵天线基板的过程包括测试该装置。

26. 发明授权

US08338813B2 Bit-erasing architecture for seek-scan probe (SSP) memory storage 有权
标题翻译：扫描探针（SSP）存储器的位擦除架构
公开(公告)号：US08338813B2
公开(公告)日：2012-12-25
申请号：US12631265
申请日：2009-12-04
申请人： Qing Ma , Valluri R. Rao , Tsung-Kuan Allen Chou
发明人： Qing Ma , Valluri R. Rao , Tsung-Kuan Allen Chou
IPC分类号： H01L47/00
CPC分类号： B82Y10/00 , G11B9/04 , G11B9/1436 , G11B9/1472
摘要： An apparatus comprising a substrate, a heater formed on the substrate, and a phase-change layer formed on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer. A process comprising forming a heater on a substrate and forming a phase-change layer on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer.
摘要翻译：一种包括基板，形成在基板上的加热器和形成在加热器上的相变层的装置。加热器包括加热器层和电耦合到加热器层的第一和第二电极。一种方法，包括在基底上形成加热器并在加热器上形成相变层。加热器包括加热器层和电耦合到加热器层的第一和第二电极。

27. 发明申请

US20120192413A1 GLASS CORE SUBSTRATE FOR INTEGRATED CIRCUIT DEVICES AND METHODS OF MAKING THE SAME 审中-公开
标题翻译：用于集成电路装置的玻璃核心基板及其制造方法
公开(公告)号：US20120192413A1
公开(公告)日：2012-08-02
申请号：US13442092
申请日：2012-04-09
申请人： Qing Ma , Quan A. Tran , Robert L. Sankman , Johanna M. Swan , Valluri R. Rao
发明人： Qing Ma , Quan A. Tran , Robert L. Sankman , Johanna M. Swan , Valluri R. Rao
IPC分类号： H01R43/00
CPC分类号： H05K1/112 , H01L21/4803 , H01L21/486 , H01L23/15 , H01L23/3675 , H01L23/49822 , H01L23/49827 , H01L2224/16225 , H01L2224/16227 , H01L2224/32245 , H01L2224/73253 , H01L2924/00014 , H01L2924/10253 , H05K3/0014 , H05K3/4605 , H05K3/4644 , H05K2201/096 , H05K2201/09827 , H05K2201/10287 , H05K2201/10371 , H05K2201/10674 , H05K2203/0108 , H05K2203/0228 , H05K2203/025 , Y10T29/49117 , Y10T29/49126 , Y10T29/49155 , H01L2924/00 , H01L2224/0401
摘要： Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.
摘要翻译：公开了用于集成电路（IC）装置的玻璃芯基板的实施例。玻璃芯基板包括在玻璃芯的相对侧上的玻璃芯和堆积结构。导电端子可以形成在玻璃芯基板的两侧。 IC芯片可以与衬底的一侧上的端子耦合，而相对侧上的端子可以与诸如电路板的下一级组件耦合。玻璃芯可以包括其中已经形成导体的单片玻璃，或者玻璃芯可以包括已经连接在一起的两个或更多个玻璃部分，每个部分具有导体。导体延伸穿过玻璃芯，并且一个或多个导体可以与设置在玻璃芯上的积聚结构电耦合。描述和要求保护其他实施例。

28. 发明授权

US08068405B2 Ferroelectric memory and method in which polarity of domain of ferroelectric memory is determined using ratio of currents 有权
标题翻译：铁电存储器和其中使用电流比确定铁电存储器的极性的方法
公开(公告)号：US08068405B2
公开(公告)日：2011-11-29
申请号：US11772194
申请日：2007-06-30
申请人： Qing Ma , Valluri R. Rao , Li-Peng Wang , Nathan Franklin
发明人： Qing Ma , Valluri R. Rao , Li-Peng Wang , Nathan Franklin
IPC分类号： G11B9/02
CPC分类号： G11C11/22
摘要： Methods and arrangements for data storage are discussed. Embodiments include applying a first voltage between a tip and an electrode, thereby forming a polarized domain in a ferroelectric material between 1 nanometer (nm) and 50 nm in thickness. The embodiments may also include applying another voltage through the tip, thereby generating a current responsive to an orientation of the polarized domain. The embodiments may also include measuring the current and determining the orientation of the polarized domain, based upon the measuring.
摘要翻译：讨论了数据存储的方法和布置。实施例包括在尖端和电极之间施加第一电压，从而在厚度在1nm（nm）到50nm之间的铁电材料中形成极化畴。实施例还可以包括通过尖端施加另一电压，从而产生响应于偏振域的取向的电流。实施例还可以包括基于测量来测量电流并确定极化畴的取向。

29. 发明申请

US20110147055A1 Glass core substrate for integrated circuit devices and methods of making the same 有权
标题翻译：用于集成电路器件的玻璃核心衬底及其制造方法
公开(公告)号：US20110147055A1
公开(公告)日：2011-06-23
申请号：US12653710
申请日：2009-12-17
申请人： Qing Ma , Quan A. Tran , Robert L. Sankman , Johanna M. Swan , Valluri R. Rao
发明人： Qing Ma , Quan A. Tran , Robert L. Sankman , Johanna M. Swan , Valluri R. Rao
IPC分类号： H05K1/03 , H05K3/10 , H05K3/36
CPC分类号： H05K1/112 , H01L21/4803 , H01L21/486 , H01L23/15 , H01L23/3675 , H01L23/49822 , H01L23/49827 , H01L2224/16225 , H01L2224/16227 , H01L2224/32245 , H01L2224/73253 , H01L2924/00014 , H01L2924/10253 , H05K3/0014 , H05K3/4605 , H05K3/4644 , H05K2201/096 , H05K2201/09827 , H05K2201/10287 , H05K2201/10371 , H05K2201/10674 , H05K2203/0108 , H05K2203/0228 , H05K2203/025 , Y10T29/49117 , Y10T29/49126 , Y10T29/49155 , H01L2924/00 , H01L2224/0401
摘要： Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.
摘要翻译：公开了用于集成电路（IC）装置的玻璃芯基板的实施例。玻璃芯基板包括在玻璃芯的相对侧上的玻璃芯和堆积结构。导电端子可以形成在玻璃芯基板的两侧。 IC芯片可以与衬底的一侧上的端子耦合，而相对侧上的端子可以与诸如电路板的下一级组件耦合。玻璃芯可以包括其中已经形成导体的单片玻璃，或者玻璃芯可以包括已经连接在一起的两个或更多个玻璃部分，每个部分具有导体。导体延伸穿过玻璃芯，并且一个或多个导体可以与设置在玻璃芯上的积聚结构电耦合。描述和要求保护其他实施例。

30. 发明申请

US20100080051A1 BIT-ERASING ARCHITECTURE FOR SEEK-SCAN PROBE (SSP) MEMORY STORAGE 有权
标题翻译： SEEK-SCAN PROBE（SSP）存储器的BIT-ERASING ARCHITECTURE
公开(公告)号：US20100080051A1
公开(公告)日：2010-04-01
申请号：US12631265
申请日：2009-12-04
申请人： Qing Ma , Valluri R. Rao , Tsung-Kuan Allen Chou
发明人： Qing Ma , Valluri R. Rao , Tsung-Kuan Allen Chou
IPC分类号： G11C11/56 , H01L45/00
CPC分类号： B82Y10/00 , G11B9/04 , G11B9/1436 , G11B9/1472
摘要： An apparatus comprising a substrate, a heater formed on the substrate, and a phase-change layer formed on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer. A process comprising forming a heater on a substrate and forming a phase-change layer on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer.
摘要翻译：一种包括基板，形成在基板上的加热器和形成在加热器上的相变层的装置。加热器包括加热器层和电耦合到加热器层的第一和第二电极。一种方法，包括在基底上形成加热器并在加热器上形成相变层。加热器包括加热器层和电耦合到加热器层的第一和第二电极。

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