专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20070204087A1 Two-level interrupt service routine 有权
标题翻译：两级中断服务程序
公开(公告)号：US20070204087A1
公开(公告)日：2007-08-30
申请号：US11361402
申请日：2006-02-24
申请人： Michael Birenbach , Gregory Brookshire , James Dieffenderfer , Stephen Geist , Richard Moore , Thomas Sartorius , Rodney Smith
发明人： Michael Birenbach , Gregory Brookshire , James Dieffenderfer , Stephen Geist , Richard Moore , Thomas Sartorius , Rodney Smith
IPC分类号： G06F13/26
CPC分类号： G06F9/4812
摘要： A processor provides two-level interrupt servicing. In one embodiment, the processor comprises a storage device and an interrupt handler. The storage device is configured to store an interrupt identifier corresponding to an interrupt request. The interrupt handler is configured to recognize the interrupt request, initiate a common interrupt service routine responsive to recognizing the interrupt request and subsequently initiate an interrupt service routine corresponding to the stored interrupt identifier.
摘要翻译：处理器提供两级中断服务。在一个实施例中，处理器包括存储设备和中断处理程序。存储装置被配置为存储对应于中断请求的中断标识符。中断处理程序被配置为识别中断请求，响应于识别中断请求并且随后发起与存储的中断标识符相对应的中断服务程序，启动公共中断服务程序。

22. 发明申请

US20070174592A1 Early conditional selection of an operand 有权
标题翻译：早期有条件地选择操作数
公开(公告)号：US20070174592A1
公开(公告)日：2007-07-26
申请号：US11336357
申请日：2006-01-20
申请人： James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Thomas Sartorius
发明人： James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Thomas Sartorius
IPC分类号： G06F15/00 , G06F9/44 , G06F7/38
CPC分类号： G06F9/30072 , G06F9/30036 , G06F9/30094 , G06F9/3016 , G06F9/30167
摘要： Delays due to waiting for operands that will not be used by a select operand instruction, are alleviated based on an early recognition that such operand data is not required in order to complete the processing of the select operand instruction. At appropriate points prior to execution, determinations are made regarding a selection criterion or criteria specified by the select operand instruction, conditions that affect the selection criteria, and the availability of operands. A hold circuit uses the determinations to control the activation and release of a hold signal that controls processor pipeline stalls. A stall required to wait for operand data is skipped or a stall is terminated early, if the selected operand is available even though the other operand, that will not be used, is not available. A stall due to waiting for operands is maintained until the selection criteria is met and the selected operand is fetched and made available.
摘要翻译：由于等待操作数不被选择操作数指令使用的延迟，基于早期识别，为了完成选择操作数指令的处理而不需要这种操作数数据，可以减轻延迟。在执行之前的适当点，确定关于由选择操作数指令指定的选择标准或标准，影响选择标准的条件以及操作数的可用性。保持电路使用该确定来控制控制处理器流水线停顿的保持信号的激活和释放。如果所选择的操作数可用，即使不使用另一个操作数不可用，则跳过等待操作数数据所需的档位或提前终止档位。维持由于等待操作数而导致的停顿，直到满足选择标准并且所选择的操作数被获取并可用。

23. 发明申请

US20070067574A1 Method and apparatus for managing cache partitioning 有权
标题翻译：用于管理缓存分区的方法和装置
公开(公告)号：US20070067574A1
公开(公告)日：2007-03-22
申请号：US11233575
申请日：2005-09-21
申请人： Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius , Rodney Smith , Robert Clancy , Victor Augsburg
发明人： Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius , Rodney Smith , Robert Clancy , Victor Augsburg
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： A method of managing cache partitions provides a first pointer for higher priority writes and a second pointer for lower priority writes, and uses the first pointer to delimit the lower priority writes. For example, locked writes have greater priority than unlocked writes, and a first pointer may be used for locked writes, and a second pointer may be used for unlocked writes. The first pointer is advanced responsive to making locked writes, and its advancement thus defines a locked region and an unlocked region. The second pointer is advanced responsive to making unlocked writes. The second pointer also is advanced (or retreated) as needed to prevent it from pointing to locations already traversed by the first pointer. Thus, the pointer delimits the unlocked region and allows the locked region to grow at the expense of the unlocked region.
摘要翻译：管理高速缓存分区的方法提供用于较高优先级写入的第一指针和用于较低优先级写入的第二指针，并且使用第一指针来划分较低优先级的写入。例如，锁定的写入具有比解锁的写入更高的优先级，并且第一指针可以用于锁定的写入，并且第二指针可以用于解锁的写入。响应于锁定写入，第一指针是高级的，并且其进步因此定义了锁定区域和解锁区域。响应于解锁写入，第二个指针是高级的。第二个指针也根据需要进行高级（或撤销），以防止它指向已经被第一个指针所遍历的位置。因此，指针限定未锁定区域，并允许锁定区域以解锁区域为代价而增长。

24. 发明申请

US20070050594A1 TLB lock indicator 有权
标题翻译： TLB锁定指示灯
公开(公告)号：US20070050594A1
公开(公告)日：2007-03-01
申请号：US11210526
申请日：2005-08-23
申请人： Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
发明人： Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/126 , G06F2212/681
摘要： A processor includes a hierarchical Translation Lookaside Buffer (TLB) comprising a Level-1 TLB and a small, high-speed Level-0 TLB. Entries in the L0 TLB replicate entries in the L1 TLB. The processor first accesses the L0 TLB in an address translation, and access the L1 TLB if a virtual address misses in the L0 TLB. When the virtual address hits in the L1 TLB, the virtual address, physical address, and page attributes are written to the L0 TLB, replacing an existing entry if the L0 TLB is full. The entry may be locked against replacement in the L0 TLB in response to an L0 Lock (L0L) indicator in the L1 TLB entry. Similarly, in a hardware-managed L1 TLB, entries may be locked against replacement in response to an L1 Lock (L1L) indicator in the corresponding page table entry.
摘要翻译：处理器包括包括Level-1 TLB和小的高速Level-0 TLB的分级翻译后备缓冲器（TLB）。 L0 TLB中的条目复制L1 TLB中的条目。处理器首先在地址转换中访问L0 TLB，如果在L0 TLB中虚拟地址丢失，则访问L1 TLB。当虚拟地址在L1 TLB中时，虚拟地址，物理地址和页面属性被写入L0 TLB，如果L0 TLB已满，则替换现有条目。响应于L1 TLB条目中的L0锁定（L0L）指示灯，该条目可能被锁定在L0 TLB中。类似地，在硬件管理的L1 TLB中，可以响应于相应页表条目中的L1锁定（L1L）指示符来锁定条目以替代。

25. 发明申请

US20070038826A1 Method and system for providing an energy efficient register file 有权
标题翻译：提供能量效率寄存器文件的方法和系统
公开(公告)号：US20070038826A1
公开(公告)日：2007-02-15
申请号：US11201542
申请日：2005-08-10
申请人： James Dieffenderfer , Thomas Sartorius , Jeffrey Bridges , Michael McIlvaine , Gregory Burda
发明人： James Dieffenderfer , Thomas Sartorius , Jeffrey Bridges , Michael McIlvaine , Gregory Burda
IPC分类号： G06F12/14 , G06F12/00
CPC分类号： G06F9/30105 , G06F9/30141
摘要： A register file is disclosed. The register file includes a plurality of registers and a decoder. The decoder may be configured to receive an address for any one of the registers, and disable a read operation to the addressed register if data in the addressed register is invalid.
摘要翻译：公开了一种寄存器文件。寄存器文件包括多个寄存器和解码器。解码器可以被配置为接收任何一个寄存器的地址，并且如果寻址的寄存器中的数据无效，则禁止对寻址的寄存器的读取操作。

26. 发明申请

US20070028050A1 Instruction cache having fixed number of variable length instructions 有权
标题翻译：指令缓存具有固定数量的可变长度指令
公开(公告)号：US20070028050A1
公开(公告)日：2007-02-01
申请号：US11193547
申请日：2005-07-29
申请人： Jeffrey Bridges , James Dieffenderfer , Rodney Smith , Thomas Sartorius
发明人： Jeffrey Bridges , James Dieffenderfer , Rodney Smith , Thomas Sartorius
IPC分类号： G06F12/00
CPC分类号： G06F9/30149 , G06F9/3816 , G06F9/382
摘要： A fixed number of variable-length instructions are stored in each line of an instruction cache. The variable-length instructions are aligned along predetermined boundaries. Since the length of each instruction in the line, and hence the span of memory the instructions occupy, is not known, the address of the next following instruction is calculated and stored with the cache line. Ascertaining the instruction boundaries, aligning the instructions, and calculating the next fetch address are performed in a predecoder prior to placing the instructions in the cache.
摘要翻译：固定数量的可变长度指令存储在指令高速缓存的每一行中。可变长度指令沿预定边界排列。由于行中的每条指令的长度以及指令占用的存储器的跨度是未知的，所以下一个跟随指令的地址被计算并与高速缓存行一起存储。在将指令置于高速缓存之前，确定指令边界，对准指令并计算下一个提取地址在预解码器中执行。

27. 发明申请

US20060282829A1 Method and apparatus for managing instruction flushing in a microprocessor's instruction pipeline 有权
标题翻译：用于在微处理器指令管线中管理指令冲洗的方法和装置
公开(公告)号：US20060282829A1
公开(公告)日：2006-12-14
申请号：US11149773
申请日：2005-06-10
申请人： Michael Mcllvaine , James Dieffenderfer , Thomas Sartorius
发明人： Michael Mcllvaine , James Dieffenderfer , Thomas Sartorius
IPC分类号： G06F9/44
CPC分类号： G06F9/3861 , G06F9/30072 , G06F9/3867 , G06F12/0855 , G06F12/0862 , G06F2212/6028
摘要： In one or more embodiments, a processor includes one or more circuits to flush instructions from an instruction pipeline on a selective basis responsive to detecting a branch misprediction, such that those instructions marked as being dependent on the branch instruction associated with the branch misprediction are flushed. Thus, the one or more circuits may be configured to mark instructions fetched into the processor's instruction pipeline(s) to indicate their branch prediction dependencies, directly or indirectly detect incorrect branch predictions, and directly or indirectly flush instructions in the instruction pipeline(s) that are marked as being dependent on an incorrect branch prediction.
摘要翻译：在一个或多个实施例中，处理器包括一个或多个电路，用于响应于检测到分支错误预测而选择性地刷新来自指令流水线的指令，使得标记为依赖于与分支错误预测相关联的分支指令的那些指令被刷新。因此，一个或多个电路可以被配置为标记被提取到处理器的指令流水线中以指示其分支预测依赖性的指令，直接或间接地检测不正确的分支预测，以及直接或间接地刷新指令流水线中的指令，被标记为依赖于不正确的分支预测。

28. 发明申请

US20060218358A1 Enforcing strongly-ordered requests in a weakly-ordered processing system 有权
标题翻译：在弱有序的处理系统中执行强有序的请求
公开(公告)号：US20060218358A1
公开(公告)日：2006-09-28
申请号：US11253307
申请日：2005-10-19
申请人： Richard Hofmann , Thomas Sartorius , Thomas Speier , Jaya Subramaniam Ganasan , James Dieffenderfer , James Sullivan
发明人： Richard Hofmann , Thomas Sartorius , Thomas Speier , Jaya Subramaniam Ganasan , James Dieffenderfer , James Sullivan
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F13/1621
摘要： The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.
摘要翻译：本公开涉及一种用于在弱有序处理系统中强制执行强有序存储器访问请求的弱有序处理系统和方法。处理系统包括多个存储器件和多个处理器。每个处理器被配置为生成对一个或多个存储器设备的存储器访问请求，其中每个存储器访问请求具有可以被断言以指示强有序请求的属性。处理系统还包括被配置为将处理器与存储器设备接口的总线互连，总线互连还被配置为基于属性来强制对存储器访问请求的排序限制。

29. 发明申请

US20060200655A1 Forward looking branch target address caching 审中-公开
标题翻译：前瞻性分支目标地址缓存
公开(公告)号：US20060200655A1
公开(公告)日：2006-09-07
申请号：US11073283
申请日：2005-03-04
申请人： Rodney Smith , Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
发明人： Rodney Smith , Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
IPC分类号： G06F9/00
CPC分类号： G06F12/1063 , G06F9/321 , G06F9/3806 , G06F9/3844 , G06F12/0862 , G06F12/0875 , G06F2212/6028
摘要： A pipelined processor comprises an instruction cache (iCache), a branch target address cache (BTAC), and processing stages, including a stage to fetch from the iCache and the BTAC. To compensate for the number of cycles needed to fetch a branch target address from the BTAC, the fetch from the BTAC leads the fetch of a branch instruction from the iCache by an amount related to the cycles needed to fetch from the BTAC. Disclosed examples either decrement a write address of the BTAC or increment a fetch address of the BTAC, by an amount essentially corresponding to one less than the cycles needed for a BTAC fetch.
摘要翻译：流水线处理器包括指令高速缓存（iCache），分支目标地址缓存（BTAC）和处理阶段，包括从iCache和BTAC获取的阶段。为了补偿从BTAC获取分支目标地址所需的周期数，从BTAC的提取导致从iCache获取分支指令与从BTAC获取所需的周期相关的量。所公开的示例可以减少BTAC的写入地址或增加BTAC的获取地址，其量基本上对应于比BTAC提取所需的周期少一个量。

30. 发明申请

US20060174090A1 Power efficient instruction prefetch mechanism 有权
公开(公告)号：US20060174090A1
公开(公告)日：2006-08-03
申请号：US11050932
申请日：2005-02-03
申请人： Thomas Sartorius , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Rodney Smith
发明人： Thomas Sartorius , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Rodney Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/3844 , G06F9/3804
摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式