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21. 发明授权

US06403393B1 Device having integrated optical and copper conductors and method of fabricating same 失效
标题翻译：具有集成光和铜导体的装置及其制造方法
公开(公告)号：US06403393B1
公开(公告)日：2002-06-11
申请号：US09388163
申请日：1999-09-01
申请人： James W. Adkisson , Paul W. Pastel , Anthony K. Stamper
发明人： James W. Adkisson , Paul W. Pastel , Anthony K. Stamper
IPC分类号： G02B600
CPC分类号： G02B6/132 , G02B6/122 , G02B6/13 , G02B2006/121
摘要： A method is provided for making optical waveguide structures in a semiconductor device wherein a rectangular cross-section low index of refraction material is encapsulated in a trench by a high index of refraction material. The waveguide structures may be made in a device containing copper conductors in trenches by forming new trenches to hold the optical waveguide. Copper conductor containing trenches may also be made in an electronic component containing waveguide structures and a further method is provided for forming an optical waveguide structure by replacing a copper containing trench with the waveguide structure in an electronic component having a plurality of copper containing trenches. All the methods use conventional techniques so that the fabrication of a semiconductor device containing both optical waveguide structures and copper conductor structures can be made both efficiently and economically.
摘要翻译：提供了一种用于在半导体器件中制造光波导结构的方法，其中通过高折射率材料将矩形横截面的低折射率材料折射率封装在沟槽中。波导结构可以通过形成新的沟槽来保持光波导，在包含沟槽中的铜导体的器件中制成。包含沟槽的铜导体也可以制成包含波导结构的电子部件，并且提供了另外的方法，用于通过在具有多个含铜沟槽的电子部件中用波导结构替换含铜沟槽来形成光波导结构。所有这些方法都使用常规技术，从而可以有效地和经济地制造含有光波导结构和铜导体结构的半导体器件。

22. 发明授权

US07494748B2 Method for correction of defects in lithography masks 失效
标题翻译：光刻掩模中缺陷校正方法
公开(公告)号：US07494748B2
公开(公告)日：2009-02-24
申请号：US10904308
申请日：2004-11-03
申请人： James W. Adkisson , Eric M. Coker , Christopher K. Magg , Jed H. Rankin , Anthony K. Stamper
发明人： James W. Adkisson , Eric M. Coker , Christopher K. Magg , Jed H. Rankin , Anthony K. Stamper
IPC分类号： G03F1/00
CPC分类号： G03F1/72 , G03F1/70
摘要： A method for correction of defects in lithography masks includes determining the existence of mask defects on an original mask, and identifying a stitchable zone around each of the mask defects found on the original mask. Each of the identified stitchable zones on the original mask is blocked out such that circuitry within the stitchable zones is not printed out during exposure of the original mask. A repair mask is formed, the repair mask including corrected circuit patterns from each of the identified stitchable zones.
摘要翻译：用于校正光刻掩模中的缺陷的方法包括确定原始掩模上的掩模缺陷的存在，以及识别在原始掩模上发现的每个掩模缺陷周围的可缝合区域。原始掩模上的每个识别的可缝合区域被阻挡，使得在原始掩模曝光期间不能打印出可缝合区域内的电路。形成修复掩模，修复掩模包括来自每个识别的可缝合区域的校正电路图案。

23. 发明申请

US20090085152A1 THREE DIMENSIONAL VERTICAL E-FUSE STRUCTURES AND METHODS OF MANUFACTURING THE SAME 失效
标题翻译：三维垂直电子熔断器结构及其制造方法
公开(公告)号：US20090085152A1
公开(公告)日：2009-04-02
申请号：US11865079
申请日：2007-10-01
申请人： Kerry Bernstein , Timothy J. Dalton , Jeffrey P. Gambino , Mark D. Jaffe , Stephen E. Luce , Anthony K. Stamper
发明人： Kerry Bernstein , Timothy J. Dalton , Jeffrey P. Gambino , Mark D. Jaffe , Stephen E. Luce , Anthony K. Stamper
IPC分类号： H01L23/62 , H01L21/44
CPC分类号： H01L23/5256 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.
摘要翻译：本文提供三维垂直电子熔丝结构及其制造方法。形成熔丝结构的方法包括提供包括绝缘体层并在绝缘体层中形成开口的衬底。该方法还包括沿着开口的侧壁形成导电层并用绝缘体材料填充开口。垂直e熔丝结构包括第一接触层和第二接触层。该结构还包括衬里在通孔内并与第一接触层和第二接触层电接触的导电材料。当施加电流时，导电材料具有增加的电阻。

24. 发明授权

US06261895B1 Polysilicon capacitor having large capacitance and low resistance and process for forming the capacitor 失效
标题翻译：具有大电容和低电阻的多晶硅电容器和用于形成电容器的工艺
公开(公告)号：US06261895B1
公开(公告)日：2001-07-17
申请号：US09225043
申请日：1999-01-04
申请人： James W. Adkisson , John A. Bracchitta , Jed H. Rankin , Anthony K. Stamper
发明人： James W. Adkisson , John A. Bracchitta , Jed H. Rankin , Anthony K. Stamper
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/3144 , H01L28/91
摘要： A process for forming capacitors in a semiconductor device. In one embodiment, a first insulating layer is deposited on the semiconductor device; a trench is formed in the insulating layer; a first low resistance metal layer is formed covering the interior surface of the trench; a first polysilicon layer is formed over the first low resistance metal layer; a first dielectric layer is formed over the first polysilicon layer; a second polysilicon layer is formed over the first dielectric layer; a second low resistance metal layer is formed over the second polysilicon layer; a third polysilicon layer is formed over the second low resistance metal layer; a second dielectric layer is formed over the third polysilicon layer; a fourth polysilicon layer is formed over the second dielectric layer; a third low resistance metal layer is formed over the fourth polysilicon layer until the trench is filled; the semiconductor device is planarized until the first, second and third low resistance metal layers are exposed above the trench; finally, capacitor leads are formed to the first, second, and third low resistance metal layers.
摘要翻译：一种用于在半导体器件中形成电容器的工艺。在一个实施例中，第一绝缘层沉积在半导体器件上; 在绝缘层中形成沟槽; 形成覆盖沟槽内表面的第一低电阻金属层; 在第一低电阻金属层上形成第一多晶硅层; 第一介电层形成在第一多晶硅层上; 在第一介电层上形成第二多晶硅层; 在第二多晶硅层上形成第二低电阻金属层; 在第二低电阻金属层上形成第三多晶硅层; 在所述第三多晶硅层上形成第二电介质层; 在第二介电层上形成第四多晶硅层; 第四低电阻金属层形成在第四多晶硅层上，直到沟槽被填充; 半导体器件被平坦化，直到第一，第二和第三低电阻金属层暴露在沟槽上方; 最后，对第一，第二和第三低电阻金属层形成电容器引线。

25. 发明授权

US08232190B2 Three dimensional vertical E-fuse structures and methods of manufacturing the same 失效
标题翻译：三维垂直E熔丝结构及其制造方法
公开(公告)号：US08232190B2
公开(公告)日：2012-07-31
申请号：US11865079
申请日：2007-10-01
申请人： Kerry Bernstein , Timothy J. Dalton , Jeffrey P. Gambino , Mark D. Jaffe , Stephen E. Luce , Anthony K. Stamper
发明人： Kerry Bernstein , Timothy J. Dalton , Jeffrey P. Gambino , Mark D. Jaffe , Stephen E. Luce , Anthony K. Stamper
IPC分类号： H01L21/44
CPC分类号： H01L23/5256 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.
摘要翻译：本文提供三维垂直电子熔丝结构及其制造方法。形成熔丝结构的方法包括提供包括绝缘体层并在绝缘体层中形成开口的衬底。该方法还包括沿着开口的侧壁形成导电层并用绝缘体材料填充开口。垂直e熔丝结构包括第一接触层和第二接触层。该结构还包括衬里在通孔内并与第一接触层和第二接触层电接触的导电材料。当施加电流时，导电材料具有增加的电阻。

26. 发明授权

US08973250B2 Methods of manufacturing a micro-electro-mechanical system (MEMS) structure 有权
标题翻译：制造微电子机械系统（MEMS）结构的方法
公开(公告)号：US08973250B2
公开(公告)日：2015-03-10
申请号：US13164323
申请日：2011-06-20
申请人： Christopher V. Jahnes , Anthony K. Stamper
发明人： Christopher V. Jahnes , Anthony K. Stamper
IPC分类号： H04R31/00 , B81B3/00 , B81C1/00 , B81B7/00 , H01L41/113 , H01L41/09
CPC分类号： B81B3/001 , B81B3/0021 , B81B3/0059 , B81B3/0072 , B81B7/0006 , B81B7/008 , B81B2201/016 , B81B2203/0163 , B81C1/00015 , B81C1/0015 , B81C1/00476 , G06F17/5045 , H01L41/094 , H01L41/1134 , H01L41/1138 , Y10T29/49002 , Y10T29/49005 , Y10T29/4908 , Y10T29/49121
摘要： Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are provided. The method of forming a MEMS structure includes forming a wiring layer on a substrate comprising actuator electrodes and a contact electrode. The method further includes forming a MEMS beam above the wiring layer. The method further includes forming at least one spring attached to at least one end of the MEMS beam. The method further includes forming an array of mini-bumps between the wiring layer and the MEMS beam.
摘要翻译：提供微机电系统（MEMS）结构，制造方法和设计结构。形成MEMS结构的方法包括在包括致动器电极和接触电极的基板上形成布线层。该方法还包括在布线层上方形成MEMS光束。该方法还包括形成至少一个连接到MEMS梁的至少一端的弹簧。该方法还包括在布线层和MEMS光束之间形成微小凸块的阵列。

27. 发明授权

US08865497B2 Planar cavity MEMS and related structures, methods of manufacture and design structures 有权
标题翻译：平面腔MEMS及相关结构，制造方法和设计结构
公开(公告)号：US08865497B2
公开(公告)日：2014-10-21
申请号：US12973422
申请日：2010-12-20
申请人： George A. Dunbar, III , Zhong-Xiang He , Jeffrey C. Maling , William J. Murphy , Anthony K. Stamper
发明人： George A. Dunbar, III , Zhong-Xiang He , Jeffrey C. Maling , William J. Murphy , Anthony K. Stamper
IPC分类号： H01L29/84 , B81C1/00 , B81B3/00 , G06F17/50 , H01H57/00
CPC分类号： B81B3/0072 , B81B3/0021 , B81B2201/01 , B81B2201/014 , B81B2203/0118 , B81B2203/0315 , B81B2203/04 , B81C1/0015 , B81C1/00365 , B81C1/00476 , B81C1/00619 , B81C1/00626 , B81C1/00666 , B81C2201/0109 , B81C2201/013 , B81C2201/0167 , B81C2201/017 , B81C2203/0136 , B81C2203/0172 , G06F17/5068 , G06F17/5072 , H01H1/0036 , H01H57/00 , H01H59/0009 , H01H2057/006 , H01L41/1136 , H01L2924/0002 , Y10S438/937 , Y10T29/42 , Y10T29/435 , Y10T29/49002 , Y10T29/49105 , Y10T29/49121 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/5313 , H01L2924/00
摘要： A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a lower wiring layer on a substrate. The method further includes forming a plurality of discrete wires from the lower wiring layer. The method further includes forming an electrode beam over the plurality of discrete wires. The at least one of the forming of the electrode beam and the plurality of discrete wires are formed with a layout which minimizes hillocks and triple points in subsequent silicon deposition.
摘要翻译：形成至少一个微机电系统（MEMS）的方法包括在基板上形成下布线层。该方法还包括从下布线层形成多条分立布线。该方法还包括在多个离散导线上形成电极束。形成电极束和多个离散导线中的至少一个形成有最小化后续硅沉积中的小丘和三点的布局。

28. 发明授权

US08829518B2 Test structure and calibration method 有权
标题翻译：测试结构和校准方法
公开(公告)号：US08829518B2
公开(公告)日：2014-09-09
申请号：US13231516
申请日：2011-09-13
申请人： Jeffrey C. Maling , Anthony K. Stamper , Eric J. White
发明人： Jeffrey C. Maling , Anthony K. Stamper , Eric J. White
IPC分类号： H01L29/10
CPC分类号： B81C99/004
摘要： A test structure for measuring a Micro-Electro-Mechanical System (MEMS) cavity height structure and calibration method. The method includes forming a sacrificial cavity material over a plurality of electrodes and forming an opening into the sacrificial cavity material. The method further includes forming a transparent or substantially transparent material in the opening to form a transparent or substantially transparent window. The method further includes tuning a thickness of the sacrificial cavity material based on measurements obtained through the transparent or substantially transparent window.
摘要翻译：用于测量微机电系统（MEMS）腔体高度结构和校准方法的测试结构。该方法包括在多个电极上形成牺牲腔材料并在牺牲腔材料中形成开口。该方法还包括在开口中形成透明或基本上透明的材料以形成透明或基本上透明的窗口。该方法还包括基于通过透明或基本上透明的窗口获得的测量值调整牺牲腔材料的厚度。

29. 发明授权

US08791545B2 Interconnect structures and design structures for a radiofrequency integrated circuit 有权
标题翻译：射频集成电路的互连结构和设计结构
公开(公告)号：US08791545B2
公开(公告)日：2014-07-29
申请号：US13560446
申请日：2012-07-27
申请人： Timothy J. Dalton , Ebenezer E. Eshun , Sarah L. Grunow , Zhong-Xiang He , Anthony K. Stamper
发明人： Timothy J. Dalton , Ebenezer E. Eshun , Sarah L. Grunow , Zhong-Xiang He , Anthony K. Stamper
IPC分类号： H01L21/02
CPC分类号： H01L21/76885 , H01L21/76816 , H01L21/76832 , H01L21/76834 , H01L27/016 , H01L28/20 , H01L28/40
摘要： Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.
摘要翻译：包括诸如薄膜电阻器或金属 - 绝缘体 - 金属（MIM）电容器的无源元件的互连结构，用于制造包括无源元件的互连结构的方法，以及体现在机器可读介质中的设计结构，用于设计，制造或测试诸如射频集成电路的集成电路。电介质层的顶表面相对于电介质层中导电特征的顶表面凹陷。无源元件形成在介电层的凹入的顶表面上，并且包括与导电特征的顶表面共面或低于导电特征的顶表面的导电材料层。

30. 发明授权

US08569888B2 Wiring structure and method of forming the structure 有权
标题翻译：布线结构及形成方法
公开(公告)号：US08569888B2
公开(公告)日：2013-10-29
申请号：US13114079
申请日：2011-05-24
申请人： Fen Chen , Jeffrey P. Gambino , Anthony K. Stamper , Timothy D. Sullivan
发明人： Fen Chen , Jeffrey P. Gambino , Anthony K. Stamper , Timothy D. Sullivan
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76843 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.
摘要翻译：公开了一种具有导电扩散阻挡层的结构的布线结构和方法，所述导电扩散阻挡层具有较厚的上部和较薄的下部。较厚的上部位于布线结构和相邻电介质材料之间的接合处。较厚的上部：（1）最小化金属离子扩散，从而使TDDB; （2）允许在布线结构的顶部实现对于低TDDB最佳的电线宽度与电介质空间宽度比; 和（3）为通孔着陆提供更大的表面积。较薄的下部：（1）允许在布线结构的其余部分中保持不同的导线宽度与电介质空间宽度比，以平衡其他竞争因素; （2）允许更大的导线截面减小电流密度，从而减少EM; 和（3）避免了布线结构电阻率的增加。

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