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21. 发明申请

US20110084865A1 DIGITAL RF CONVERTER AND RF CONVERTING METHOD THEREOF 有权
标题翻译：数字射频转换器及其RF转换方法
公开(公告)号：US20110084865A1
公开(公告)日：2011-04-14
申请号：US12902125
申请日：2010-10-11
申请人： Jang Hong CHOI , Hyun Ho Boo , Hyun Kyu Yu
发明人： Jang Hong CHOI , Hyun Ho Boo , Hyun Kyu Yu
IPC分类号： H03M1/66
CPC分类号： H03M3/504 , H03M3/32
摘要： Provided are a digital radio frequency (RF) converter and an RF converting method thereof. The RF frequency converter includes first and second RF output terminals of a differential form outputting an RF signal; a differential switch selectively connecting first and second nodes into the first and second RF output terminals in response to an oscillating waveform; at least one digital delay device column outputting a plurality of unit bits by sequentially delaying an input bit corresponding to the digital input signal; a front-end processor summing an output of the at least one digital delay device column; a plurality of current sources; and a plurality of first switches corresponding to the plurality of current sources, respectively, and delivering currents of current sources whose number corresponds to the sum value of the front-end processor among the plurality of current sources, to one of the first and second nodes.
摘要翻译：提供一种数字射频（RF）转换器及其RF转换方法。 RF频率转换器包括输出RF信号的差分形式的第一和第二RF输出端; 差分开关响应于振荡波形选择性地将第一和第二节点连接到第一和第二RF输出端子中; 至少一个数字延迟装置列通过顺序地延迟对应于数字输入信号的输入位而输出多个单位位; 前端处理器对所述至少一个数字延迟装置列的输出求和; 多个电流源; 以及分别对应于多个电流源的多个第一开关，并将数量对应于多个电流源中的前端处理器的和值的电流源的电流传送到第一和第二节点之一。

22. 发明授权

US07911248B2 Apparatus for linearization of digitally controlled oscillator 有权
标题翻译：数字控制振荡器线性化装置
公开(公告)号：US07911248B2
公开(公告)日：2011-03-22
申请号：US12629701
申请日：2009-12-02
申请人： Jang Hong Choi , Hyun Kyu Yu
发明人： Jang Hong Choi , Hyun Kyu Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/0991 , H03L7/093
摘要： There is provided an apparatus for the linearization of a digitally controlled oscillator. The apparatus includes a first filter outputting only a low frequency band signal of an input signal to the digitally controlled oscillator; a negative feedback loop causing the signal of an input port of the digitally controlled oscillator to pass through a frequency table and a frequency-to-digital code mapper in sequence and correcting an input of the digitally controlled oscillator by performing negative feedback to an input port of the first filter; and a frequency table generator storing a frequency value of an output signal of the digitally controlled oscillator in the frequency table.
摘要翻译：提供了一种用于数字控制振荡器的线性化的装置。该装置包括仅将输入信号的低频信号输出到数控振荡器的第一滤波器; 使得数字控制振荡器的输入端口的信号顺序通过频率表和频数码复用器的负反馈环路，并通过对输入端口执行负反馈来校正数字控制振荡器的输入的第一个过滤器; 以及频率表生成器，其存储频率表中数字控制振荡器的输出信号的频率值。

23. 发明授权

US07759703B2 Photo-detector array device with ROIC monolithically integrated for laser-radar image signal and manufacturing method thereof 失效
标题翻译：用于激光雷达图像信号的ROIC单片集成的光电检测器阵列器件及其制造方法
公开(公告)号：US07759703B2
公开(公告)日：2010-07-20
申请号：US12143584
申请日：2008-06-20
申请人： Eun Soo Nam , Myoung Sook Oh , Ho Young Kim , Young Jun Chong , Hyun Kyu Yu
发明人： Eun Soo Nam , Myoung Sook Oh , Ho Young Kim , Young Jun Chong , Hyun Kyu Yu
IPC分类号： H01L29/737
CPC分类号： H01L27/14643 , G01S7/4863 , G01S17/89 , H01L27/14681 , H04N5/369
摘要： A photo-detector array device integrated with a read-out integrated circuit (ROIC) monolithically integrated for a laser-radar image signal and a manufacturing method thereof are provided. According to the photo-detector array device, a photodiode and control devices for selecting and outputting a laser-radar image signal are simultaneously formed on an InP substrate, so that it is possible to simplify manufacturing processes and to greatly increasing yield. In addition, after the photodiode and the control devices are simultaneously formed on the InP substrate, the photodiode and the control devices are electrically speared from each other by using a polyimide. Therefore, a PN junction surface of the photodiode is buried, so that a surface leakage current can be reduced and an electrical reliability can be improved. In addition, a structure of the control devices can be simplified, so that image signal reception characteristics can be improved.
摘要翻译：提供了与用于激光雷达图像信号单片集成的读出集成电路（ROIC）集成的光电检测器阵列装置及其制造方法。根据光检测器阵列器件，在InP衬底上同时形成用于选择和输出激光雷达图像信号的光电二极管和控制装置，从而可以简化制造工艺并大大提高产量。此外，在InP衬底上同时形成光电二极管和控制装置之后，通过使用聚酰亚胺将光电二极管和控制装置电分离。因此，埋入光电二极管的PN结表面，从而能够减小表面泄漏电流，提高电气可靠性。此外，可以简化控制装置的结构，从而可以提高图像信号接收特性。

24. 发明申请

US20100134335A1 APPARATUS FOR COMPENSATING FOR ERROR OF TIME-TO-DIGITAL CONVERTER 有权
标题翻译：用于补偿时间到数字转换器错误的装置
公开(公告)号：US20100134335A1
公开(公告)日：2010-06-03
申请号：US12629020
申请日：2009-12-01
申请人： Mi Jeong Park , Byung Hun Min , Ja Yol Lee , Hyun Kyu Yu
发明人： Mi Jeong Park , Byung Hun Min , Ja Yol Lee , Hyun Kyu Yu
IPC分类号： H03M1/06
CPC分类号： G04F10/06 , H03L7/085 , H03L2207/50
摘要： An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N−1)th fragmented delay phases; an adding unit adding each of the first to the (N−1)th fragmented delay phases to the phase error to generate first to (N−1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N−1)th phase errors.
摘要翻译：公开了用于补偿时间 - 数字转换器（TDC）的误差的装置，以从包括TDC的相位检测器和包括TDC误差的相位误差接收延迟相位并补偿TDC误差以具有时间分辨率提高N倍（N是自然数）。该装置包括：分段和乘法单元，将延迟相位分片N次（N是自然数），以产生第一到第（N-1）个分段延迟相位; 加法单元将第一到第（N-1）个分段延迟相位中的每一个相加到相位误差，以产生第一到第（N-1）个相位误差; 以及比较单元从相位误差和第一到第（N-1）个相位误差获取最接近实际相位误差的相位误差补偿值。

25. 发明申请

US20090146197A1 PHOTO-DETECTOR ARRAY DEVICE WITH ROIC MONOLITHICALLY INTEGRATED FOR LASER-RADAR IMAGE SIGNAL AND MANUFACTURING METHOD THEREOF 失效
标题翻译：具有单色集成的激光雷达图像信号的光电检测器阵列器件及其制造方法
公开(公告)号：US20090146197A1
公开(公告)日：2009-06-11
申请号：US12143584
申请日：2008-06-20
申请人： Eun Soo Nam , Myoung Sook Oh , Ho Young Kim , Young Jun Chong , Hyun Kyu Yu
发明人： Eun Soo Nam , Myoung Sook Oh , Ho Young Kim , Young Jun Chong , Hyun Kyu Yu
IPC分类号： H01L31/00 , H01L21/00
CPC分类号： H01L27/14643 , G01S7/4863 , G01S17/89 , H01L27/14681 , H04N5/369
摘要： A photo-detector array device integrated with a read-out integrated circuit (ROIC) monolithically integrated for a laser-radar image signal and a manufacturing method thereof are provided. According to the photo-detector array device, a photodiode and control devices for selecting and outputting a laser-radar image signal are simultaneously formed on an InP substrate, so that it is possible to simplify manufacturing processes and to greatly increasing yield. In addition, after the photodiode and the control devices are simultaneously formed on the InP substrate, the photodiode and the control devices are electrically speared from each other by using a polyimide. Therefore, a PN junction surface of the photodiode is buried, so that a surface leakage current can be reduced and an electrical reliability can be improved. In addition, a structure of the control devices can be simplified, so that image signal reception characteristics can be improved.
摘要翻译：提供了与用于激光雷达图像信号单片集成的读出集成电路（ROIC）集成的光电检测器阵列装置及其制造方法。根据光检测器阵列器件，在InP衬底上同时形成用于选择和输出激光雷达图像信号的光电二极管和控制装置，从而可以简化制造工艺并大大提高产量。此外，在InP衬底上同时形成光电二极管和控制装置之后，通过使用聚酰亚胺将光电二极管和控制装置电分离。因此，埋入光电二极管的PN结表面，从而能够减小表面泄漏电流，提高电气可靠性。此外，可以简化控制装置的结构，从而可以提高图像信号接收特性。

26. 发明授权

US07456063B2 Layout method of power line for semiconductor integrated circuit and semiconductor integrated circuit manufactured by the layout method 有权
标题翻译：半导体集成电路电源线布局方法和半导体集成电路布局方法
公开(公告)号：US07456063B2
公开(公告)日：2008-11-25
申请号：US11523212
申请日：2006-09-19
申请人： Sang Jin Byun , Hyun Kyu Yu
发明人： Sang Jin Byun , Hyun Kyu Yu
IPC分类号： H01L21/8242
CPC分类号： H01L27/0207
摘要： Provided are a layout method of a power line for a semiconductor integrated circuit and a semiconductor integrated circuit manufactured by the layout method. The layout method includes the steps of: forming a decoupling capacitor on a substrate; laying out a first metal layer, connected to the decoupling capacitor through a contact, above a region where the decoupling capacitor is formed so as to cover the decoupling capacitor; and laying out a second metal layer above a region where the first metal layer is formed. Therefore, the metal layers and the decoupling capacitor are laid out in the same region so that a chip area can be prevented from being additionally consumed at the time of laying out the decoupling capacitor, and degradation which may occur due to connection line resistance from the power lines to the decoupling capacitors can be prevented.
摘要翻译：提供了一种用于半导体集成电路的电力线的布局方法和通过布局方法制造的半导体集成电路。布局方法包括以下步骤：在衬底上形成去耦电容器; 在形成去耦电容器的区域上方布置第一金属层，其通过接触件连接到去耦电容器，以覆盖去耦电容器; 并在其上形成第一金属层的区域上方布置第二金属层。因此，金属层和去耦电容器布置在相同的区域中，使得在布置去耦电容器时可以防止芯片面积额外消耗，并且可能由于连接线电阻而导致的劣化可以防止到去耦电容器的电源线。

27. 发明授权

US07391260B2 Variable gain amplifier and variable gain amplifier module 有权
标题翻译：可变增益放大器和可变增益放大器模块
公开(公告)号：US07391260B2
公开(公告)日：2008-06-24
申请号：US11510403
申请日：2006-08-25
申请人： Young Ho Kim , Mun Yang Park , Hyun Kyu Yu
发明人： Young Ho Kim , Mun Yang Park , Hyun Kyu Yu
IPC分类号： H03F1/36 , H03F3/45
CPC分类号： H03G1/007 , H03F1/08 , H03F1/34 , H03F3/45475 , H03F2200/381 , H03F2203/45138 , H03F2203/45522 , H03F2203/45524
摘要： An analog variable gain amplifier (VGA) adjusting a signal level of a mobile communication system is provided. More particularly, design of a VGA using an operational transconductance amplifier (OTA) having a wide linear input/output range is disclosed. The VGA includes two double-differential-pair OTAs and feedback resistors. A first differential input of a first double differential pair OTA receives an input signal from the forward stage, and a second differential input is negatively fed back through a differential output and a passive resistor. An input in which a first block of the connection structure and first and second differential inputs of a second double differential pair OTA are connected receives an output signal of the first block stage. The output is negatively fed back in series through a variable resistor whose resistance varies exponentially with an adjustment voltage from outside. According to the VGA, it is possible to provide a characteristic of linear variation of gain on a logarithmic scale with respect to a control voltage with a simple and inexpensive constitution. In addition, the VGA can be designed for a low pass filter having a conventional OTA used for a core circuit, and has a simple circuit structure. Therefore, the VGA is convenient for high integration and low-power design, and thus is appropriate for a terminal chip and so forth.
摘要翻译：提供了调整移动通信系统的信号电平的模拟可变增益放大器（VGA）。更具体地，公开了使用具有宽线性输入/输出范围的运算跨导放大器（OTA）的VGA的设计。 VGA包括两个双差分对OTA和反馈电阻。第一双差分对OTA的第一差分输入接收来自前级的输入信号，并且第二差分输入通过差分输出和无源电阻负反馈。其中连接结构的第一块和第二双差分对OTA的第一和第二差分输入相连接的输入端接收第一块级的输出信号。输出通过可变电阻串联负反馈，其电阻随外部调整电压呈指数变化。根据VGA，可以以简单且便宜的结构提供相对于控制电压的对数标度的增益的线性变化的特性。此外，VGA可以设计用于具有用于核心电路的常规OTA的低通滤波器，并且具有简单的电路结构。因此，VGA对于高集成度和低功耗设计是方便的，因此适用于终端芯片等。

28. 发明授权

US5840609A Method of manufacturing semiconductor device having stacked gate electrode structure 失效
标题翻译：制造具有层叠栅电极结构的半导体器件的方法
公开(公告)号：US5840609A
公开(公告)日：1998-11-24
申请号：US951564
申请日：1997-10-16
申请人： Yeong Cheol Hyeon , Hyun Kyu Yu
发明人： Yeong Cheol Hyeon , Hyun Kyu Yu
IPC分类号： H01L21/28 , H01L21/3105 , H01L21/336 , H01L29/49 , H01L21/26
CPC分类号： H01L29/6659 , H01L21/31051 , H01L29/4925 , H01L29/66545
摘要： A method for manufacturing a semiconductor device having a stacked gate electrode structure of self-aligned polysilicon-metal, which is capable of minimizing the variation in structural and electrical characteristics of the gate electrode, while utilizing the manufacturing process of forming a conventional silicone semiconductor memory device, is disclosed. According to the method for manufacturing a semiconductor device of the present invention, the conventional technique generally used in the manufacturing process of forming the silicon semiconductor device can be effectively utilized. Further, an excessive etch loss in the oxide layer can be restrained by using the oxide spacer of the self-aligned oxide layer in forming the metal layer at the gate electrode structure. Furthermore, it has an advantageous effect that the stable electrical characteristics of the resulting device can be obtained by using the polysilicon layer as a basic constituting material of the gate electrode thereof.
摘要翻译：一种用于制造具有自对准多晶硅 - 金属堆叠栅电极结构的半导体器件的方法，其能够最小化栅电极的结构和电特性的变化，同时利用形成常规硅氧烷半导体存储器的制造工艺设备。根据本发明的半导体器件的制造方法，可以有效地利用通常用于形成硅半导体器件的制造工艺中的常规技术。此外，通过在栅极电极结构形成金属层时，通过使用自对准氧化物层的氧化物间隔物，可以抑制氧化物层中的过度的蚀刻损失。此外，通过使用多晶硅层作为其栅电极的基本构成材料，可以获得所得到的器件的稳定电特性。

29. 发明申请

US20120105116A1 FREQUENCY SYNTHESIZER 有权
标题翻译：频率合成器
公开(公告)号：US20120105116A1
公开(公告)日：2012-05-03
申请号：US13344513
申请日：2012-01-05
申请人： Byung Hun MIN , Hyun Kyu Yu
发明人： Byung Hun MIN , Hyun Kyu Yu
IPC分类号： H03L7/08
CPC分类号： H03L7/091 , H03L7/085 , H03L7/107 , H03L7/1075 , H03L7/183 , H03L2207/06 , H03L2207/50
摘要： There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; and a phase detection unit outputting a control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency.
摘要翻译：提供了一个频率合成器。频率合成器包括：频率振荡器，其根据控制位调整输出频率; 具有预设的最小分频比的可编程分频器，所述编程分频器以可分分频比划分所述频率振荡器的输出频率; 接收可编程分频器的输出信号的计数器单元和参考频率，以在参考频率的一个周期期间对可编程分频器的输出信号的上升沿进行计数以产生计数值，并且当计数值是1，并且当计数值为2时输出第二命中信号; 以及相位检测单元，输出通过从从计数值和参考频率获得的锁定相位的分数误差中减去可编程分频器的输出信号的分数误差而获得的控制位。

30. 发明授权

US08031009B2 Frequency calibration loop circuit 失效
标题翻译：频率校准回路电路
公开(公告)号：US08031009B2
公开(公告)日：2011-10-04
申请号：US12581105
申请日：2009-10-16
申请人： Byung Hun Min , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
发明人： Byung Hun Min , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03L7/085 , H03L7/095 , H03L7/18 , H03L7/081
CPC分类号： H03L7/181 , H03L2207/50 , Y10S331/02
摘要： A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting an oscillation frequency of an oscillation signal according to a control value; a programmable divider dividing the oscillation signal according to a division ratio to output a divided signal; a counter counting the number of clocks of the divided signal for one cycle of a reference signal to output a count value; and a frequency detector obtaining the control value by subtracting the count value from a reference comparison value, wherein the reference comparison value is obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider.
摘要翻译：一种频率校准环路电路，具有预定的频道字（FCW）指令值，为了获得振荡器中的目标频率输入的比特和可编程分频器的预设最小分频比n（n是常数）包括：振荡器，根据控制值调整振荡信号的振荡频率; 可编程分频器，根据分频比除以振荡信号，输出分频信号; 计数针对参考信号的一个周期的分频信号的时钟数，以输出计数值; 以及频率检测器，通过从参考比较值中减去计数值来获得控制值，其中通过将频率通道字（FCW）指令值除以可编程分频器的最小分频比来获得参考比较值。

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