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21. 发明授权

US5625829A Dockable computer system capable of symmetric multi-processing operations 失效
标题翻译：可对称多处理操作的可移植计算机系统
公开(公告)号：US5625829A
公开(公告)日：1997-04-29
申请号：US276250
申请日：1994-07-18
申请人： Douglas D. Gephardt , Steven L. Belt , Drew J. Dutton
发明人： Douglas D. Gephardt , Steven L. Belt , Drew J. Dutton
IPC分类号： G06F15/173 , G06F1/16 , G06F13/36 , G06F13/364 , G06F13/40 , G06F3/00
CPC分类号： G06F13/364 , G06F1/1632 , G06F13/4036 , G06F13/4081
摘要： A dockable computer system is capable of performing symmetrical multi-processing operations. More particularly, the dockable computer system includes a portable computer and a host station (docking station), each including a resident CPU. The dockable computer system is capable of operating in a docked state in which the portable computer is physically joined with the host station and an undocked state in which the portable computer is physically separate from the host station. In the docked state, the dockable computer system is capable of performing demanding computational tasks such as video conferencing as one of the CPUs in either the portable computer or host station is dedicated to the video conferencing operation. The dockable computer system preferably includes a communication channel for transmitting multi-processing support signals between the portable computer and the host station. Multi-processing support signals include synchronization signals, cache coherency signals, and interrupt distribution signals such as the LOCK signal, PLOCK signal, FLUSH signal, EADS signal, INTR signal or INTACK signal. The communication channel may be a dedicated bus or may be provided through a docking bridge between the portable computer and host station. The dockable computer system advantageously optimizes CPU resources when the dockable computer system is in a docked state.
摘要翻译：可停靠的计算机系统能够执行对称的多处理操作。更具体地，可停靠的计算机系统包括便携式计算机和主机站（对接站），每个都包括驻留的CPU。可停靠的计算机系统能够在对接状态下操作，其中便携式计算机与主机站物理连接，并且其中便携式计算机在物理上与主机站分离的未停靠状态。在对接状态下，可停靠的计算机系统能够执行诸如视频会议的苛刻的计算任务，因为便携式计算机或主机站中的一个CPU专用于视频会议操作。对接计算机系统优选地包括用于在便携式计算机和主机站之间传送多处理支持信号的通信信道。多处理支持信号包括同步信号，高速缓存一致性信号和中断分配信号，例如LOCK信号，PLOCK信号，FLUSH信号，EADS信号，INTR信号或INTACK信号。通信信道可以是专用总线，或者可以通过便携式计算机和主机站之间的对接桥提供。可对接计算机系统有利地优化当可停靠的计算机系统处于对接状态时的CPU资源。

22. 发明授权

US5598537A Apparatus and method for driving a bus to a docking safe state in a dockable computer system including a docking station and a portable computer 失效
标题翻译：一种用于在包括对接站和便携式计算机的可对接计算机系统中将总线驱动到对接安全状态的装置和方法
公开(公告)号：US5598537A
公开(公告)日：1997-01-28
申请号：US280314
申请日：1994-07-26
申请人： Scott Swanstrom , Douglas D. Gephardt
发明人： Scott Swanstrom , Douglas D. Gephardt
IPC分类号： G06F1/18 , G06F1/16 , G06F3/00 , G06F13/364 , G06F13/40 , H05K7/10 , G06F13/00
CPC分类号： G06F1/1632 , G06F13/364 , G06F13/4036 , G06F13/4072 , G06F13/4081
摘要： In a dockable computer system capable of hot docking or warm docking, a docking safe circuit drives the bus of the portable computer and docking station to a docking safe state in response to a DOCK signal. The DOCK signal may be a notice signal indicative of a change of state from the undocked state to the docked state or from the docked state to the undocked state. The notice signal may be provided from software, a user-actuated switch or an infrared signal. Preferably, the docking safe state or dockable state is a state in which: the ground conductors of the buses are referenced to a common ground potential; the buses are "quiet" or non-transitioning; the bidirectional terminals on the bus of the portable computer are set to an output state; the bidirectional terminals of the bus of the docking station are set to an input state; and the signaling levels of the buses have the same voltage potential. Preferably, the present invention is implemented on a peripheral component interconnect (PCI) bus.
摘要翻译：在能够热对接或热对接的可停靠的计算机系统中，对接安全电路响应于DOCK信号将便携式计算机和坞站的总线驱动到对接安全状态。 DOCK信号可以是指示状态从脱离状态到对接状态或从停靠状态到解除停止状态的通知信号。通知信号可以由软件，用户致动的开关或红外信号提供。优选地，对接安全状态或可停靠状态是这样的状态，其中：总线的接地导体参考公共地电位; 公共汽车是“安静的”还是非转型的; 便携式计算机总线上的双向终端设置为输出状态; 对接站的总线的双向端子被设置为输入状态; 并且总线的信号电平具有相同的电压电位。优选地，本发明在外围组件互连（PCI）总线上实现。

23. 发明授权

US5561821A System for performing I/O access and memory access by driving address of DMA configuration registers and memory address stored therein respectively on local bus 失效
标题翻译：通过分别在本地总线上驱动DMA配置寄存器的地址和存储地址来执行I / O访问和存储器访问的系统
公开(公告)号：US5561821A
公开(公告)日：1996-10-01
申请号：US145375
申请日：1993-10-29
申请人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
发明人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
IPC分类号： G06F13/28 , G06F13/36
CPC分类号： G06F13/28
摘要： A direct memory access controller is provided that performs DMA transfers by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines of a local bus. During the I/O access cycle, an address value within a DMA configuration address range is driven on the address lines of the local bus. The DMA configuration address range is the range of address values to which the configuration registers of the DMA controller are mapped for receiving initialization data. Accordingly, other peripheral devices that may be connected to the local bus will not respond to the I/O access cycle. An address disable signal is further not required to disable the address decoders of other I/O peripheral devices not involved in the DMA transfer. Since the memory access cycle and the I/O access cycle of the DMA transfer are identical to those executed by the system microprocessor, subsystems are not required to respond to specialized DMA protocols. Finally, although the DMA controller implements two-cycle DMA transfers, the DMA controller is compatible with conventional peripheral devices which assume one-cycle DMA transfer protocols.
摘要翻译：提供了通过执行存储器访问周期和I / O访问周期来执行DMA传输的直接存储器访问控制器。在存储器访问周期期间，要访问的系统存储器的地址位置在本地总线的寻址行上被驱动。在I / O访问周期中，DMA配置地址范围内的地址值在本地总线的地址线上驱动。 DMA配置地址范围是映射DMA控制器的配置寄存器以接收初始化数据的地址值范围。因此，可能连接到本地总线的其他外围设备将不会响应I / O访问周期。不需要禁止地址禁止信号来禁用DMA传输中不涉及的其他I / O外围设备的地址解码器。由于DMA传输的存储器访问周期和I / O访问周期与系统微处理器执行的存储器访问周期和I / O访问周期相同，因此子系统不需要响应专门的DMA协议。最后，虽然DMA控制器实现了两个周期的DMA传输，但DMA控制器与传统的外围设备兼容，它们采用一个周期的DMA传输协议。

24. 发明授权

US5561819A Computer system selecting byte lane for a peripheral device during I/O addressing technique of disabling non-participating peripherals by driving an address within a range on the local bus in a DMA controller 失效
标题翻译：计算机系统在通过在DMA控制器中驱动本地总线上的范围内的地址来禁用非参与的外设的I / O寻址技术期间选择外围设备的字节通道
公开(公告)号：US5561819A
公开(公告)日：1996-10-01
申请号：US145376
申请日：1993-10-29
申请人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
发明人： Douglas D. Gephardt , Dan S. Mudgett , James R. MacDonald
IPC分类号： G06F13/28 , G06F13/36 , G06F13/40
CPC分类号： G06F13/28 , G06F13/4018
摘要： A direct memory access controller implements a two-cycle approach for performing a desired DMA transfer by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines of a local bus. During the I/O access cycle, an address value within a DMA configuration address range is driven on the address lines of the local bus. The lower two order bits of the address value are encoded to provide byte lane information to a peripheral device during the I.backslash.O access cycle. The peripheral device responsively receives or provides data at the specified byte lane. As a result, peripheral devices that may be connected to the local bus will not respond to the I/O access cycle, while encoded byte lane information is provided to the desired peripheral device without requiring dedicated byte select lines.
摘要翻译：直接存储器访问控制器通过执行存储器访问周期和I / O访问周期来实现用于执行所需DMA传输的两周期方法。在存储器访问周期期间，要访问的系统存储器的地址位置在本地总线的寻址行上被驱动。在I / O访问周期中，DMA配置地址范围内的地址值在本地总线的地址线上驱动。在I + 544 O访问周期期间，编码地址值的较低的两位，以向外围设备提供字节通道信息。外围设备响应地在指定的字节通道处接收或提供数据。结果，可能连接到本地总线的外围设备将不会响应I / O访问周期，而编码字节通道信息被提供给期望的外围设备，而不需要专用字节选择线。

25. 发明授权

US5493684A Power management architecture including a power management messaging bus for conveying an encoded activity signal for optimal flexibility 失效
标题翻译：电源管理架构，包括用于传送编码的活动信号的电源管理消息总线，以获得最佳的灵活性
公开(公告)号：US5493684A
公开(公告)日：1996-02-20
申请号：US223984
申请日：1994-04-06
申请人： Douglas D. Gephardt , James R. MacDonald , Rita M. O'Brien
发明人： Douglas D. Gephardt , James R. MacDonald , Rita M. O'Brien
IPC分类号： G06F1/04 , G06F1/26 , G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/325 , G06F1/3287 , Y02B60/1217 , Y02B60/1282
摘要： An integrated processor is provided that includes a CPU core coupled to a variety of on-chip peripheral devices such as a DMA controller, an interrupt controller, and a timer. The integrated processor further includes a power management message unit coupled to the DMA controller, interrupt controller, and timer for monitoring the internal interrupt and bus request signals of the integrated processor. The power management message unit may also monitor other selected activities of the integrated processor such as activities of a floating-point coprocessing subunit. Based on the detected activities, if any, the power management message unit encodes a message on a power management message bus to thereby provide information regarding the internal events of the integrated processor to an external power management unit. Power management decisions are made by an external power management unit. The power management unit receives the encoded messages on the power management message bus and responsively makes decisions as to the appropriate power management mode to enter. The power management unit includes a clock control unit coupled to an internal clock generator of the integrated processor for controlling the frequencies of a CPU clock signal and a system clock signal. The power management unit further includes a power control unit for controlling the application of power to various external peripheral devices.
摘要翻译：提供了一种集成处理器，其包括耦合到诸如DMA控制器，中断控制器和定时器的各种片上外围设备的CPU核心。集成处理器还包括耦合到DMA控制器，中断控制器和用于监视集成处理器的内部中断和总线请求信号的定时器的电源管理消息单元。功率管理消息单元还可以监视集成处理器的其他选定的活动，例如浮点协处理子单元的活动。基于所检测到的活动（如果有的话），功率管理消息单元对功率管理消息总线上的消息进行编码，从而向外部电源管理单元提供关于集成处理器的内部事件的信息。电源管理决定由外部电源管理单元进行。电源管理单元在电源管理消息总线上接收编码的消息，并且响应于作出关于进入的适当的电源管理模式的决定。功率管理单元包括时钟控制单元，其耦合到集成处理器的内部时钟发生器，用于控制CPU时钟信号和系统时钟信号的频率。电源管理单元还包括用于控制向各种外部外围设备施加电力的电力控制单元。

26. 发明授权

US5060138A Apparatus for use with a computing device for generating a substitute acknowledgement to an input when the computing device is in an operational hiatus 失效
标题翻译：用于与计算设备一起使用的装置，用于在计算设备处于操作中断时向输入生成替代确认
公开(公告)号：US5060138A
公开(公告)日：1991-10-22
申请号：US576695
申请日：1990-08-31
申请人： Douglas D. Gephardt , Peggy Avalos
发明人： Douglas D. Gephardt , Peggy Avalos
IPC分类号： G06F1/04 , G06F13/36 , G11C11/406
CPC分类号： G06F13/36 , Y02B60/1228
摘要： The invention is an apparatus for use with a computing device for generating a substitute acknowledgement to a first input signal when the computing device is in an operational hiatus. The apparatus comprises a logical processing circuit for indicating presence of the first input signal depending upon the state of a second input signal, and a logical circuit for producing an output signal which is representative of a selection of one of the plurality of logical inputs. The selection of logical inputs is determined by the state of the second input signal. The first input signal is a hold request signal and comprises a first logical input to the logical processing circuit. A second logical input is a hold acknowledgement signal which is generated by the computing device in response to the presence of the first input signal when the computing device is not in an operational hiatus.

27. 发明授权

US08249730B2 Systems and methods for shadowing an HDA codec 失效
标题翻译：用于屏蔽HDA编解码器的系统和方法
公开(公告)号：US08249730B2
公开(公告)日：2012-08-21
申请号：US12202360
申请日：2008-09-01
申请人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas , Adam Zaharias
发明人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas , Adam Zaharias
IPC分类号： G06F17/00
CPC分类号： G06F3/162
摘要： Systems and methods for “shadowing” a target codec to provide additional features that are not available in the target codec. In one embodiment, an audio amplification system includes a High Definition Audio (HDA) bus, and an HDA controller, a conventional HDA codec and a shadow HDA codec coupled to the HDA bus. The conventional codec receives audio data and commands from the HDA controller via the bus and processes them to generate an output audio signal. The shadow codec snoops the audio data and commands on the HDA bus that are targeted to the conventional codec. The shadow codec processes the snooped audio data and commands to generate a second audio output. The shadow codec does not communicate with the HDA controller and is transparent to the controller. The shadow codec does not request enumeration from the HDA controller and does not receive an address from the HDA controller.
摘要翻译：用于“遮蔽”目标编解码器以提供目标编解码器中不可用的附加功能的系统和方法。在一个实施例中，音频放大系统包括高清晰度音频（HDA）总线和HDA控制器，传统的HDA编解码器和耦合到HDA总线的影子HDA编解码器。常规编解码器经由总线从HDA控制器接收音频数据和命令，并处理它们以产生输出音频信号。影子编解码器侦听HDA总线上的传统编解码器的音频数据和命令。影子编解码器处理窥探的音频数据和命令以产生第二个音频输出。影子编解码器不与HDA控制器通信，对控制器是透明的。影子编解码器不要求来自HDA控制器的枚举，也不会从HDA控制器接收地址。

28. 发明授权

US08219226B2 Systems and methods for overriding hardwired responses in an HDA codec 失效
标题翻译：用于覆盖HDA编解码器中的硬连线响应的系统和方法
公开(公告)号：US08219226B2
公开(公告)日：2012-07-10
申请号：US12202358
申请日：2008-09-01
申请人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas
发明人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas
IPC分类号： G06F17/00 , G06F13/00 , G06F9/30 , G06F9/40
CPC分类号： G06F3/162
摘要： Systems and methods for overriding hardwired responses of a codec to High Definition Audio (HDA) verbs that are received from an HDA controller. In one embodiment, an HDA codec is configured to store one or more overriding responses, each of which is associated with a corresponding HDA verb. When an HDA verb is received by the codec, the codec determines whether the verb is associated with one of the overriding responses. If the verb is associated with one of the overriding responses, the overriding response is returned to the HDA controller. If the first HDA verb is not associated with one of the stored overriding responses, provide a hardwired response associated with the first HDA verb to the HDA bus. Overriding responses can be returned for unsupported verbs only, or for any verbs that prompt responses.
摘要翻译：用于将编解码器的硬连线响应覆盖从HDA控制器接收的高清晰度音频（HDA）动词的系统和方法。在一个实施例中，HDA编解码器被配置为存储一个或多个覆盖的响应，每一个响应与相应的HDA动词相关联。当编解码器接收到HDA动词时，编解码器确定动词是否与其中一个重写的响应相关联。如果动词与其中一个覆盖的响应相关联，则覆盖的响应将返回给HDA控制器。如果第一HDA动词与存储的覆盖应答之一不相关联，则向HDA总线提供与第一HDA动词相关联的硬连线响应。可以仅针对不支持的动词或任何提示响应的动词返回重写响应。

29. 发明申请

US20090063828A1 Systems and Methods for Communication between a PC Application and the DSP in a HDA Audio Codec 审中-公开
标题翻译： PC应用程序与HDA音频编解码器中的DSP之间的通信系统和方法
公开(公告)号：US20090063828A1
公开(公告)日：2009-03-05
申请号：US12202356
申请日：2008-09-01
申请人： Daniel L. Chieng , Douglas D. Gephardt , Larry E. Hand , Jeffrey M. Klaas , Adam Zaharias
发明人： Daniel L. Chieng , Douglas D. Gephardt , Larry E. Hand , Jeffrey M. Klaas , Adam Zaharias
IPC分类号： G06F9/315
CPC分类号： G06F3/162
摘要： Systems and methods implemented in a PC for enabling communication between an application executing on the CPU and a DSP that is incorporated into a codec in the High Definition Audio (HDA) system, wherein the communication is carried out via the HDA bus. In one embodiment, an HDA codec includes one or more conventional HDA widgets coupled to a programmable processor such as a DSP. The codec includes a set of registers that are configured to store HDA verbs and data transmitted via the HDA bus. The programmable processor is configured to identify verbs that indicate associated information is a communication from an application executing on the CPU, read the associated information, and process the information according to the associated verbs. The information may be program instructions, parametric data, requests for information, etc.
摘要翻译：在PC中实现的用于实现在CPU上执行的应用程序与被并入高清晰度音频（HDA）系统中的编解码器的DSP之间的通信的系统和方法，其中通过HDA总线进行通信。在一个实施例中，HDA编解码器包括耦合到诸如DSP的可编程处理器的一个或多个常规HDA小部件。编解码器包括一组寄存器，用于存储通过HDA总线传输的HDA动词和数据。可编程处理器被配置为识别指示相关信息的动词是来自在CPU上执行的应用程序的通信，读取相关联的信息，以及根据相关联的动词处理信息。该信息可以是程序指令，参数数据，信息请求等。

30. 发明申请

US20090063738A1 Systems and Methods for Overriding Hardwired Responses in an HDA Codec 失效
标题翻译：用于覆盖HDA编解码器中的硬连线响应的系统和方法
公开(公告)号：US20090063738A1
公开(公告)日：2009-03-05
申请号：US12202358
申请日：2008-09-01
申请人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas
发明人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas
IPC分类号： G06F13/42
CPC分类号： G06F3/162
摘要： Systems and methods for overriding hardwired responses of a codec to High Definition Audio (HDA) verbs that are received from an HDA controller. In one embodiment, an HDA codec is configured to store one or more overriding responses, each of which is associated with a corresponding HDA verb. When an HDA verb is received by the codec, the codec determines whether the verb is associated with one of the overriding responses. If the verb is associated with one of the overriding responses, the overriding response is returned to the HDA controller. If the first HDA verb is not associated with one of the stored overriding responses, provide a hardwired response associated with the first HDA verb to the HDA bus. Overriding responses can be returned for unsupported verbs only, or for any verbs that prompt responses.
摘要翻译：用于将编解码器的硬连线响应覆盖从HDA控制器接收的高清晰度音频（HDA）动词的系统和方法。在一个实施例中，HDA编解码器被配置为存储一个或多个覆盖的响应，每一个响应与相应的HDA动词相关联。当编解码器接收到HDA动词时，编解码器确定动词是否与其中一个重写的响应相关联。如果动词与其中一个覆盖的响应相关联，则覆盖的响应将返回给HDA控制器。如果第一HDA动词与存储的覆盖应答之一不相关联，则向HDA总线提供与第一HDA动词相关联的硬连线响应。可以仅针对不支持的动词或任何提示响应的动词返回重写响应。

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