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21. 发明授权

US07439108B2 Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same 有权
标题翻译：具有不同晶体取向的共面绝缘体上硅（SOI）区域及其制造方法
公开(公告)号：US07439108B2
公开(公告)日：2008-10-21
申请号：US11155030
申请日：2005-06-16
申请人： Louis Lu-Chen Hsu , Jack A. Mandelman
发明人： Louis Lu-Chen Hsu , Jack A. Mandelman
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/045 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207
摘要： In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI region having a third crystal orientation on the substrate. The first, second and third SOI regions are coplanar. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了半导体器件制造的第一种方法。第一种方法包括以下步骤：（1）提供衬底; 和（2）在基板上形成具有第一晶体取向的第一绝缘体上硅（SOI）区域，具有第二晶体取向的第二SOI区域和具有第三晶体取向的第三SOI区域。第一，第二和第三SOI区域是共面的。提供了许多其他方面。

22. 发明授权

US07427545B2 Trench memory cells with buried isolation collars, and methods of fabricating same 有权
标题翻译：具有埋置隔离套环的沟槽记忆单元及其制造方法
公开(公告)号：US07427545B2
公开(公告)日：2008-09-23
申请号：US11164381
申请日：2005-11-21
申请人： Kangguo Cheng , Jack A. Mandelman
发明人： Kangguo Cheng , Jack A. Mandelman
IPC分类号： H01L21/76 , H01L21/44
CPC分类号： H01L29/945 , H01L27/1087
摘要： The present invention relates to semiconductor devices, preferably dynamic random access memory (DRAM) cells, each of which contains at least one trench capacitor with a buried isolation collar. The trench capacitor is located in a trench in a semiconductor substrate, and it comprises inner and outer electrodes and a dielectric layer. The buried isolation collar is recessed into a sidewall of the trench and has a substantially uniform thickness. Such a buried isolation collar is preferably formed by oxygen implantation before trench etching.
摘要翻译：本发明涉及半导体器件，优选动态随机存取存储器（DRAM）单元，每个单元包含至少一个具有埋入隔离环的沟槽电容器。沟槽电容器位于半导体衬底中的沟槽中，并且其包括内电极和外电极以及电介质层。埋入的隔离套环凹入沟槽的侧壁并且具有基本均匀的厚度。这种埋置的隔离环优选通过在沟槽蚀刻之前的氧注入形成。

23. 发明授权

US07417300B2 Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabrication thereof 有权
标题翻译：具有变宽的宽度区域的电可编程熔丝结构被配置为增强电流拥挤及其制造方法
公开(公告)号：US07417300B2
公开(公告)日：2008-08-26
申请号：US11372386
申请日：2006-03-09
申请人： Roger A. Booth, Jr. , Jack A. Mandelman , William R. Tonti
发明人： Roger A. Booth, Jr. , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width region where the first terminal portion and fuse element interface. The narrowed width region extends at least partially into and includes part of the first terminal portion. The width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein. In another implementation, the fuse element includes a restricted width region wherein width of the fuse element is less than the maximum width thereof to enhance current crowding therein, and length of the restricted width region is less than a total length of the fuse element.
摘要翻译：提出了电可编程熔丝结构及其制造方法，其中熔丝包括通过细长的熔丝元件互连的第一和第二端部。第一端子部分具有大于熔丝元件的最大宽度的最大宽度，并且熔丝包括第一端子部分和熔丝元件接合的变窄的宽度区域。狭窄宽度区域至少部分地延伸并包括第一端子部分的一部分。变窄区域中的第一端子部分的宽度小于第一端子部分的最大宽度，以增强其中的电流拥挤。在另一实施方式中，熔丝元件包括限制宽度区域，其中熔丝元件的宽度小于其最大宽度以增强其中的电流拥挤，并且受限宽度区域的长度小于熔丝元件的总长度。

24. 发明申请

US20080157261A1 PATTERNED SILICON-ON-INSULATOR LAYERS AND METHODS FOR FORMING THE SAME 有权
标题翻译：图案的绝缘硅绝缘层及其形成方法
公开(公告)号：US20080157261A1
公开(公告)日：2008-07-03
申请号：US12049258
申请日：2008-03-14
申请人： Roger Allen Booth, , Louis Lu-Chen Hsu , Jack A. Mandelman , William R. Tonti
发明人： Roger Allen Booth, , Louis Lu-Chen Hsu , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L27/12
CPC分类号： H01L21/76243
摘要： In an aspect, a method is provided for forming a silicon-on-insulator (SOI) layer. The method includes the steps of (1) providing a silicon substrate; (2) selectively implanting the silicon substrate with oxygen using a low implant energy to form an ultra-thin patterned seed layer; and (3) employing the ultra-thin patterned seed layer to form a patterned SOI layer on the silicon substrate. Numerous other aspects are provided.
摘要翻译：在一方面，提供了一种用于形成绝缘体上硅（SOI）层的方法。该方法包括以下步骤：（1）提供硅衬底; （2）使用低注入能量用氧选择性地注入硅衬底以形成超薄图案种子层; 和（3）使用超薄图案种子层在硅衬底上形成图案化SOI层。提供了许多其他方面。

25. 发明授权

US07388259B2 Strained finFET CMOS device structures 有权
标题翻译：应变finFET CMOS器件结构
公开(公告)号：US07388259B2
公开(公告)日：2008-06-17
申请号：US10536483
申请日：2002-11-25
申请人： Bruce B. Doris , Dureseti Chidambarrao , MeiKei Ieong , Jack A. Mandelman
发明人： Bruce B. Doris , Dureseti Chidambarrao , MeiKei Ieong , Jack A. Mandelman
IPC分类号： H01L29/94
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/7843 , H01L29/785
摘要： A semiconductor device structure, includes a PMOS device 200 and an NMOS device 300 disposed on a substrate 1,2, the PMOS device including a compressive layer 6 stressing an active region of the PMOS device, the NMOS device including a tensile layer 9 stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices 200, 300.
摘要翻译：半导体器件结构包括PMOS器件200和设置在衬底1,2上的NMOS器件300，PMOS器件包括压迫PMOS器件的有源区的压缩层6，NMOS器件包括拉伸层9，所述NMOS器件的有源区，其中所述压缩层包括第一介电材料，所述拉伸层包括第二介电材料，并且所述PMOS和NMOS器件为FinFET器件200,300。

26. 发明授权

US07358823B2 Programmable capacitors and methods of using the same 有权
标题翻译：可编程电容器及其使用方法
公开(公告)号：US07358823B2
公开(公告)日：2008-04-15
申请号：US11353516
申请日：2006-02-14
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
IPC分类号： H03B5/12
CPC分类号： H03L7/099 , H03B5/1212 , H03B5/1228 , H03B5/124 , H03L7/095 , H03L7/10 , H03L7/18 , H03L2207/06
摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种调整半导体器件的电容的方法。第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。提供了许多其他方面。

27. 发明授权

US07227233B2 Silicon-on-insulator (SOI) Read Only Memory (ROM) array and method of making a SOI ROM 有权
标题翻译：绝缘体上硅（SOI）只读存储器（ROM）阵列和制造SOI ROM的方法
公开(公告)号：US07227233B2
公开(公告)日：2007-06-05
申请号：US11162472
申请日：2005-09-12
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Jack A. Mandelman
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Jack A. Mandelman
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L27/1203 , H01L27/1021 , H01L27/112 , H01L27/11213
摘要： A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface of the stripes. ROM cell personalization is the presence or absence of a diode and/or contact.
摘要翻译：绝缘体上硅（SOI）只读存储器（ROM）以及制造SOI ROM的方法。 ROM单元位于导体层上的表面SOI层中的条纹与正交取向的导线之间的交叉处。电线的触点连接到条纹上表面的ROM单元二极管。 ROM单元个性化是存在或不存在二极管和/或接触。

28. 发明授权

US07023041B2 Trench capacitor vertical structure 有权
标题翻译：沟槽电容器垂直结构
公开(公告)号：US07023041B2
公开(公告)日：2006-04-04
申请号：US10341187
申请日：2003-01-13
申请人： Giuseppe La Rosa , Thomas W. Dyer , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens , Alvin W. Strong
发明人： Giuseppe La Rosa , Thomas W. Dyer , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens , Alvin W. Strong
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L29/945 , H01L27/10861 , H01L27/10894 , H01L29/66181
摘要： A versatile structure is formed, based on a deep trench, vertical transistor DRAM cell, that forms a conductive extension of the trench electrode in an elongated trench that contacts the lower electrode of the vertical transistor. The structure can be used as a capacitor, as a discrete transistor as a single-transistor amplifier or as a building block for more complex circuits.
摘要翻译：基于深沟槽垂直晶体管DRAM单元形成通用结构，其在与垂直晶体管的下电极接触的细长沟槽中形成沟槽电极的导电延伸。该结构可以用作电容器，作为单晶体管放大器的分立晶体管或作为更复杂电路的构建块。

29. 发明授权

US06972220B2 Structures and methods of anti-fuse formation in SOI 失效
标题翻译： SOI中抗熔丝形成的结构和方法
公开(公告)号：US06972220B2
公开(公告)日：2005-12-06
申请号：US10366298
申请日：2003-02-12
申请人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
发明人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L21/82 , H01L21/334 , H01L23/525 , H01L27/108 , H01L27/12 , H01L21/00
CPC分类号： H01L23/5252 , H01L27/10829 , H01L27/10897 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.
摘要翻译：可以在低电压和电流下被编程并且潜在地消耗很少的芯片空间并且可以间隙地在间隔最小光刻特征尺寸的元件之间形成的反熔丝结构形成在复合衬底上，例如绝缘体上硅通过蚀刻通过绝缘体的接触到支撑半导体层，优选结合形成到达或支撑层的电容器状结构。反熔丝可以由导体形成的选定位置和/或损坏电容器状结构的电介质来编程。绝缘环用于围绕导体或电容器状结构的一部分，以将损伤限制在所需位置。由于编程电流导致的加热效应电压和噪声被有效地隔离到体硅层，从而允许在器件正常工作期间进行编程。因此实现了自动修复而不中断操作的可能性。

30. 发明授权

US06884667B1 Field effect transistor with stressed channel and method for making same 失效
标题翻译：具有应力通道的场效应晶体管及其制造方法
公开(公告)号：US06884667B1
公开(公告)日：2005-04-26
申请号：US10669727
申请日：2003-09-25
申请人： Bruce B. Doris , Dureseti Chidambarrao , Xavier Baie , Jack A. Mandelman , Devendra K. Sadana , Dominic J. Schepis
发明人： Bruce B. Doris , Dureseti Chidambarrao , Xavier Baie , Jack A. Mandelman , Devendra K. Sadana , Dominic J. Schepis
IPC分类号： H01L27/08 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/78 , H01L29/786 , H01L21/00
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/7842 , H01L29/78603 , H01L29/78696
摘要： Field effect transistor with increased charge carrier mobility due to stress in the current channel 22. The stress is in the direction of current flow (longitudinal). In PFET device, the stress is compressive; in NFET devices, the stress is tensile. The stress is created by a compressive film 34 in an area 32 under the channel. The compressive film pushes up on the channel 22, causing it to bend. In PFET devices, the compressive film is disposed under ends 31 of the channel (e.g. under the source and drain), thereby causing compression in an upper portion 22A of the channel. In NFET devices, the compressive film is disposed under a middle portion 40 of the channel (e.g. under the gate), thereby causing tension in the, upper portion of the channel. Therefore, both NFET and PFET device can be enhanced. A method for making the devices is included.
摘要翻译：场效应晶体管由于电流通道22中的应力而具有增加的电荷载流子迁移率。应力在电流方向（纵向）。在PFET器件中，应力是压缩的; 在NFET器件中，应力为拉伸。应力由通道下的区域32中的压缩膜34产生。压缩膜在通道22上向上推动，使其弯曲。在PFET器件中，压缩膜设置在通道的端部31（例如在源极和漏极之下），从而在通道的上部22A中引起压缩。在NFET器件中，压缩膜设置在通道的中间部分40（例如在栅极下），从而在通道的上部产生张力。因此，可以增强NFET和PFET器件。包括制造装置的方法。

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