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21. 发明授权

US07813178B2 Semiconductor memory device and write control method therefor 有权
标题翻译：半导体存储器件及其写控制方法
公开(公告)号：US07813178B2
公开(公告)日：2010-10-12
申请号：US12003163
申请日：2007-12-20
申请人： Kiyoshi Nakai
发明人： Kiyoshi Nakai
IPC分类号： G11C11/34
CPC分类号： G11C7/22 , G11C7/1078 , G11C7/1096 , G11C8/06 , G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C13/0069 , G11C2013/0076 , G11C2207/2218 , G11C2207/2245
摘要： Disclosed is a semiconductor memory device which includes a read data latch that holds read data from a phase change memory and latches write data entered from outside and holds write data entered from outside, a write data latch that holds the write data for a cell for the time duration of a preset number of cycles until start of data write, a transfer switch that controls whether or not an output of the read data latch is to be transferred to the write data latch, a comparator circuit that decides whether or not data transferred to the write data latch via the transfer switch and held in the write data latch and data in the read data latch are coincident with each other, and a write flag latch that latches an output of the comparator circuit. Data is written only in case there is a write request and the result of comparison of the comparator circuit indicates non-coincidence, that is, only in bits in need of data writing.
摘要翻译：公开了一种半导体存储器件，其包括读取数据锁存器，其保存来自相变存储器的读取数据并锁存从外部输入的写入数据，并保存从外部输入的写入数据;写入数据锁存器，直到数据写入开始为止的预设数量的周期的持续时间;控制读取数据锁存器的输出是否被传送到写数据锁存器的转移开关;判定数据传送到通过转换开关写入数据锁存器并保持在写入数据锁存器中，读取数据锁存器中的数据彼此一致，并且写入标志锁存器锁存比较器电路的输出。只有在存在写请求的情况下才写入数据，并且比较电路的比较结果表示不一致，即仅在需要数据写入的位中。

22. 发明授权

US07742332B2 Phase-change random access memory device and semiconductor memory device 有权
标题翻译：相变随机存取存储器件和半导体存储器件
公开(公告)号：US07742332B2
公开(公告)日：2010-06-22
申请号：US12222953
申请日：2008-08-20
申请人： Kiyoshi Nakai
发明人： Kiyoshi Nakai
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C2213/72 , G11C2213/74 , G11C2213/78 , H01L27/2409 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： A semiconductor memory device includes: first and second wiring layers extending in substantially parallel to each other in a first direction; a first semiconductor region formed in a part of a portion between the first and second wiring layers; a second semiconductor region formed on an opposite side to the first semiconductor region with respect to the second wiring layer and making a pair with the first semiconductor region; a third semiconductor region formed in another part of the portion between the first and second wiring layers; a fourth semiconductor region formed on an opposite side to the third semiconductor region with respect to the first wiring layer and making a pair with the third semiconductor region; a third wiring layer extending in a second direction that crosses the first direction and having an electrical contact with the first semiconductor region; a fourth wiring layer extending in the second direction and having an electrical contact with the fourth semiconductor region; a fifth wiring layer extending in the first direction to cross over the first and third semiconductor regions.
摘要翻译：半导体存储器件包括：第一和第二布线层，其在第一方向上彼此基本平行地延伸; 形成在所述第一和第二布线层之间的部分的一部分中的第一半导体区域; 第二半导体区域，相对于所述第二布线层形成在与所述第一半导体区域相反的一侧，并与所述第一半导体区域成对; 形成在第一和第二布线层之间的部分的另一部分中的第三半导体区域; 第四半导体区域，其形成在与所述第三半导体区域相对于所述第一布线层的相反侧并与所述第三半导体区域成对; 第三布线层，沿与所述第一方向交叉的第二方向延伸并与所述第一半导体区域电接触; 第四布线层，沿第二方向延伸并与第四半导体区域电接触; 第五布线层，其沿第一方向延伸以跨过第一和第三半导体区域。

23. 发明授权

US07225390B2 Semiconductor memory device provided with error correcting code circuitry 有权
标题翻译：具有纠错码电路的半导体存储器件
公开(公告)号：US07225390B2
公开(公告)日：2007-05-29
申请号：US10617040
申请日：2003-07-11
申请人： Yutaka Ito , Kiyoshi Nakai
发明人： Yutaka Ito , Kiyoshi Nakai
IPC分类号： H03M13/00
CPC分类号： G11C11/40615 , G06F11/1012 , G11C11/406 , G11C2211/4062
摘要： A semiconductor synchronous dynamic random access memory (SDRAM) device capable of correcting bits having a low error rate in a Pause Refresh Tail distribution and of reducing a data holding current by lengthening a refresh period so that the refresh period exceeds a period for a Pause Refresh real power. The semiconductor memory device is made up of a 16-bit SDRAM having a Hamming Code and including an ECC (Error Correcting Code) circuit made up of an encoding circuit controlled by a first test signal to output a parity bit corresponding to an information bit, a decoding circuit controlled by second test signal to output an error location detecting signal indicating an error bit in codeword, and an error correcting circuit controlled by a third test signal to input an error location detecting signal and to output an error bit in a reverse manner.
摘要翻译：一种半导体同步动态随机存取存储器（SDRAM）装置，其能够在暂停刷新尾部分配中校正具有低错误率的比特，并且通过延长刷新周期来减少数据保持电流，使得刷新周期超过暂停刷新的周期真正的权力。半导体存储器件由具有汉明码的16位SDRAM构成，并包括由第一测试信号控制的编码电路组成的ECC（纠错码）电路，以输出对应于信息位的奇偶位，由第二测试信号控制的解码电路，以输出指示码字中的错误位的错误位置检测信号，以及由第三测试信号控制的纠错电路，以输入错误位置检测信号并以相反的方式输出错误位。

24. 发明授权

US06707139B2 Semiconductor device with plural unit regions in which one or more MOSFETs are formed 有权
标题翻译：具有多个单位区域的半导体器件，其中形成有一个或多个MOSFET
公开(公告)号：US06707139B2
公开(公告)日：2004-03-16
申请号：US09928497
申请日：2001-08-14
申请人： Isamu Fujii , Kiyoshi Nakai , Yukihide Suzuki , Sadayuki Morita , Hidekazu Egawa , Katura Abe , Noriaki Sakamoto
发明人： Isamu Fujii , Kiyoshi Nakai , Yukihide Suzuki , Sadayuki Morita , Hidekazu Egawa , Katura Abe , Noriaki Sakamoto
IPC分类号： H01L2348
CPC分类号： H01L27/10897 , G11C5/025 , G11C11/4097 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection, via the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto, as needed.
摘要翻译：具有用于实现特定逻辑电路的一个至多个MOSFET的多个单位区域被放置在第一方向上。在每个单位区域上形成沿第一方向延伸的第一互连。沿着第一方向延伸的第二互连沿着多个单元区域和单元区域外部形成。在相邻的单元区域之间分别设置具有沿与第一方向相交的第二方向延伸的第三互连的配线专用区域。根据需要，在每个单位区域中形成的逻辑电路具有连接到第一互连的第一连接形式和经由第二互连连接到第三互连的第二连接形式。

25. 发明授权

US5557580A Word line driving circuit 失效
标题翻译：字线驱动电路
公开(公告)号：US5557580A
公开(公告)日：1996-09-17
申请号：US292452
申请日：1994-08-18
申请人： Shigeki Numaga , Shunichi Sukegawa , Takashi Inui , Yukihide Suzuki , Kiyoshi Nakai
发明人： Shigeki Numaga , Shunichi Sukegawa , Takashi Inui , Yukihide Suzuki , Kiyoshi Nakai
IPC分类号： G11C11/407 , G11C8/08 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C8/00 , G11C7/00
CPC分类号： G11C8/08
摘要： A word line driving circuit which effectively prevents ground noise during word line discharge along with accommodating the narrowing of pitch in the word lines by making the layout area of the word line driver small. The word line driving circuit includes n-type MOS transistor 14 and p-type MOS transistor 12. The drain terminal of n-type MOS transistor 14 and drain terminal of p-type MOS transistor 12 in word line driver 10 are connected to the base terminal of word line WLi. The output terminal of an output transistor driving circuit 16 is connected to the source terminal of p-type MOS transistor 12, and the output terminal of a first output transistor controlling circuit 18 is connected to the gate terminal. The output terminal of a second output transistor controlling circuit 20 is connected to the gate terminal of n-type MOS transistor 14, and a ground terminal 22 as a reference potential terminal for leading in the electric current is connected to the source terminal.
摘要翻译：一种字线驱动电路，通过使字线驱动器的布局面积小，能够有效地防止字线放电期间的接地噪声，同时容纳字线中的音调变窄。字线驱动电路包括n型MOS晶体管14和p型MOS晶体管12. n型MOS晶体管14的漏极端子和字线驱动器10中的p型MOS晶体管12的漏极端子连接到基极字线WLi的终端。输出晶体管驱动电路16的输出端子与p型MOS晶体管12的源极端子连接，第一输出晶体管控制电路18的输出端子与栅极端子连接。第二输出晶体管控制电路20的输出端子与n型MOS晶体管14的栅极端子连接，作为引导电流的基准电位端子的接地端子22与源极端子连接。

26. 发明授权

US4408086A Oligomerization of m-isopropenylphenol 失效
标题翻译：间 - 异丙烯基苯酚的低聚
公开(公告)号：US4408086A
公开(公告)日：1983-10-04
申请号：US212511
申请日：1980-12-03
申请人： Shunsuke Matsushima , Kazuhiko Hata , Kentaro Mashita , Shuichi Kanagawa , Shinji Nakao , Kiyoshi Nakai , Kunimasa Kamio
发明人： Shunsuke Matsushima , Kazuhiko Hata , Kentaro Mashita , Shuichi Kanagawa , Shinji Nakao , Kiyoshi Nakai , Kunimasa Kamio
IPC分类号： C07C37/14 , C07C39/17 , C08G64/14 , C07C39/14
CPC分类号： C07C37/14 , C08G64/14 , C07C2102/08
摘要： m-Isopropenylphenol oligomer which is useful for the production of synthetic resins such as epoxy resins is produced by polyermizing m-isopropenylphenol at a temperature of 135.degree. to 230.degree. C. using a catalytic amount of an acid catalyst in the presence or absence of a solvent, or freezing m-isopropenylphenol in the presence or absence of an acid catalyst.
摘要翻译：可用于生产合成树脂如环氧树脂的间 - 异丙烯基苯酚低聚物是通过在135℃至230℃的温度下，使用催化量的酸催化剂在存在或不存在的情况下将m-异丙烯基苯酚溶剂或冷冻的异丙烯基苯酚在酸催化剂存在或不存在下进行。

27. 发明授权

US4337367A Oligomer of m-isopropenylphenol 失效
标题翻译：间 - 异丙烯基苯酚的低聚物
公开(公告)号：US4337367A
公开(公告)日：1982-06-29
申请号：US106845
申请日：1979-12-26
申请人： Shuichi Kanagawa , Shinji Nakao , Kiyoshi Nakai , Kunimasa Kamio , Shunsuke Matsushima , Kazuhiko Hata , Kentaro Mashita
发明人： Shuichi Kanagawa , Shinji Nakao , Kiyoshi Nakai , Kunimasa Kamio , Shunsuke Matsushima , Kazuhiko Hata , Kentaro Mashita
IPC分类号： C08G59/00 , C08G59/06 , C08G59/32 , C07C39/12 , C07C39/06
CPC分类号： C08G59/063 , C08G59/3218
摘要： An oligomer of m-isopropenylphenol is produced by subjecting m-isopropenylphenol to thermal polymerization in the absence of a catalyst.
摘要翻译：间 - 异丙烯基苯酚的低聚物是通过在不存在催化剂的情况下使间 - 异丙烯基苯酚进行热聚合而制备的。

28. 发明授权

US08605494B2 Memory device and writing method thereof 失效
标题翻译：存储器件及其写入方法
公开(公告)号：US08605494B2
公开(公告)日：2013-12-10
申请号：US12591295
申请日：2009-11-16
申请人： Koji Sato , Kiyoshi Nakai , Kenji Mae
发明人： Koji Sato , Kiyoshi Nakai , Kenji Mae
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C7/1078 , G11C7/1096 , G11C13/0069 , G11C2013/0078
摘要： A write amplifier for driving a bit line connected to a selected phase change memory cell drives the bit line with a first current driving capability and then drives the bit line with a second current driving capability lower than the first current driving capability.
摘要翻译：用于驱动连接到所选择的相变存储器单元的位线的写放大器以第一电流驱动能力驱动位线，然后以低于第一电流驱动能力的第二电流驱动能力驱动位线。

29. 发明授权

US08054679B2 Phase change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US08054679B2
公开(公告)日：2011-11-08
申请号：US12213195
申请日：2008-06-16
申请人： Kiyoshi Nakai , Shuichi Tsukada , Yusuke Jono
发明人： Kiyoshi Nakai , Shuichi Tsukada , Yusuke Jono
IPC分类号： G11C11/00
CPC分类号： G11C13/0023 , G11C11/5678 , G11C13/0004 , G11C13/0028 , G11C13/0069 , G11C2013/0078 , G11C2213/72
摘要： A phase change memory device comprises: a phase change element for rewritably storing data by changing a resistance state; a memory cell arranged at an intersection of a word line and a bit line and formed of the phase change element and a diode connected in series; a select transistor formed in a diffusion layer below the memory cell, for selectively controlling electric connection between an anode of the diode and a ground line in response to a potential of the word line connected to a gate; and a precharge circuit for precharging the diffusion layer below the memory cell corresponding to a non-selected word line to a predetermined voltage and for disconnecting the diffusion layer below the memory cell corresponding to a selected word line from the predetermined voltage.
摘要翻译：相变存储器件包括：相变元件，用于通过改变电阻状态来重写地存储数据; 存储单元，布置在字线和位线的交点处，并由所述相变元件和串联连接的二极管形成; 形成在存储单元下方的扩散层中的选择晶体管，用于响应于连接到栅极的字线的电位选择性地控制二极管的阳极与地线之间的电连接; 以及预充电电路，用于将对应于未选择字线的存储单元下面的扩散层预充电到预定电压，并且用于将与所选择的字线相对应的存储单元下面的扩散层与预定电压断开。

30. 发明授权

US07755952B2 Semiconductor memory device and writing control method thereof 失效
标题翻译：半导体存储器件及其写入控制方法
公开(公告)号：US07755952B2
公开(公告)日：2010-07-13
申请号：US12196393
申请日：2008-08-22
申请人： Kiyoshi Nakai
发明人： Kiyoshi Nakai
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1048 , G11C7/1096 , G11C13/0004 , G11C13/0061 , G11C13/0069 , G11C2213/79
摘要： A semiconductor memory device includes: a plurality of write control circuits; a plurality of memory cells grouped in the write control circuits; a plurality of write drivers that write data to a corresponding memory cell when the write control circuit is activated; and a main control circuit that causes the write control circuits to become active in response to presence of a data writing request to the memory cells belonging to a predetermined group and subsequent absence of the data writing request to the memory cells belonging to the same group within a predetermined period.
摘要翻译：半导体存储器件包括：多个写入控制电路; 分组在写入控制电路中的多个存储器单元; 写入驱动器，当写入控制电路被激活时，将数据写入对应的存储器单元; 以及主控制电路，其使写控制电路响应于对属于预定组的存储单元的数据写入请求的存在而变为有效，并且随后不存在属于同一组的存储单元的数据写入请求预定时间。

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