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    • 1. 发明授权
    • Semiconductor memory device provided with error correcting code circuitry
    • 具有纠错码电路的半导体存储器件
    • US07225390B2
    • 2007-05-29
    • US10617040
    • 2003-07-11
    • Yutaka ItoKiyoshi Nakai
    • Yutaka ItoKiyoshi Nakai
    • H03M13/00
    • G11C11/40615G06F11/1012G11C11/406G11C2211/4062
    • A semiconductor synchronous dynamic random access memory (SDRAM) device capable of correcting bits having a low error rate in a Pause Refresh Tail distribution and of reducing a data holding current by lengthening a refresh period so that the refresh period exceeds a period for a Pause Refresh real power. The semiconductor memory device is made up of a 16-bit SDRAM having a Hamming Code and including an ECC (Error Correcting Code) circuit made up of an encoding circuit controlled by a first test signal to output a parity bit corresponding to an information bit, a decoding circuit controlled by second test signal to output an error location detecting signal indicating an error bit in codeword, and an error correcting circuit controlled by a third test signal to input an error location detecting signal and to output an error bit in a reverse manner.
    • 一种半导体同步动态随机存取存储器(SDRAM)装置,其能够在暂停刷新尾部分配中校正具有低错误率的比特,并且通过延长刷新周期来减少数据保持电流,使得刷新周期超过暂停刷新的周期 真正的权力。 半导体存储器件由具有汉明码的16位SDRAM构成,并包括由第一测试信号控制的编码电路组成的ECC(纠错码)电路,以输出对应于信息位的奇偶位, 由第二测试信号控制的解码电路,以输出指示码字中的错误位的错误位置检测信号,以及由第三测试信号控制的纠错电路,以输入错误位置检测信号并以相反的方式输出错误位 。