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21. 发明申请

US20120313176A1 Buried Sublevel Metallizations for Improved Transistor Density 有权
标题翻译：用于改善晶体管密度的埋层次级金属化
公开(公告)号：US20120313176A1
公开(公告)日：2012-12-13
申请号：US13154548
申请日：2011-06-07
申请人： Kai Frohberg , Dominik Olligs , Jens Heinrich , Katrin Reiche
发明人： Kai Frohberg , Dominik Olligs , Jens Heinrich , Katrin Reiche
IPC分类号： H01L27/088 , H01L21/768
CPC分类号： H01L21/823475 , H01L21/76801 , H01L21/76816 , H01L21/76895 , H01L21/823871
摘要： Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein electrical interconnects between circuit elements based on a buried sublevel metallization may provide improved transistor density. One illustrative method disclosed herein includes forming a contact dielectric layer above first and second transistor elements of a semiconductor device, and after forming the contact dielectric layer, forming a buried conductive element below an upper surface of the contact dielectric layer, the conductive element providing an electrical connection between the first and second transistor elements.
摘要翻译：通常，本文公开的主题涉及现代复杂的半导体器件及其形成方法，其中基于掩埋的次级金属化的电路元件之间的电互连可以提供改善的晶体管密度。本文公开的一种说明性方法包括在半导体器件的第一和第二晶体管元件上形成接触电介质层，并且在形成接触电介质层之后，在接触电介质层的上表面下方形成掩埋导电元件，导电元件提供第一和第二晶体管元件之间的电连接。

22. 发明授权

US07531867B2 Method for forming an integrated memory device and memory device 失效
标题翻译：用于形成集成存储器件和存储器件的方法
公开(公告)号：US07531867B2
公开(公告)日：2009-05-12
申请号：US11390983
申请日：2006-03-27
申请人： Dominik Olligs
发明人： Dominik Olligs
IPC分类号： H01L29/94
CPC分类号： H01L27/11568 , H01L27/115
摘要： The invention in one of the embodiments refers to a method for forming an integrated memory device, the method including a forming a plurality of bitlines, wherein forming the plurality of bitlines includes forming diffusion lines in a substrate, forming an electrically conductive silicidation barrier layer on a substrate surface exposed, and depositing a conductive layer comprising a metal on the silicidation barrier layer.
摘要翻译：在一个实施例中的本发明涉及用于形成集成存储器件的方法，该方法包括形成多个位线，其中形成多个位线包括在衬底中形成扩散线，在...上形成导电硅化物阻挡层暴露的衬底表面，以及在硅化物阻挡层上沉积包含金属的导电层。

23. 发明申请

US20060286796A1 Method of forming a contact in a flash memory device 有权
标题翻译：在闪速存储器件中形成触点的方法
公开(公告)号：US20060286796A1
公开(公告)日：2006-12-21
申请号：US11157143
申请日：2005-06-20
申请人： Nicolas Nagel , Dominik Olligs
发明人： Nicolas Nagel , Dominik Olligs
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L27/115 , H01L21/76802 , H01L21/76895 , H01L27/11568
摘要： A method of forming a contact between a bitline and a local interconnect in a flash memory device comprises forming a hard mask layer on a planarized surface that includes an exposed top section of the local interconnects prior to depositing an oxide dielectric layer. The hard mask layer may be composed of a material that has an etch resistance as compared to the interlayer dielectric material, e.g., nitride. Openings in the hard mask define positions for the contacts to the local interconnects exposed in the top section.
摘要翻译：在闪速存储器件中形成位线和局部互连之间的接触的方法包括在沉积氧化物介电层之前在平坦化表面上形成硬掩模层，其包括局部互连的暴露的顶部部分。硬掩模层可以由与层间电介质材料（例如氮化物）相比具有耐蚀刻性的材料构成。硬掩模中的开口定义了与顶部暴露的局部互连的触点的位置。

24. 发明授权

US08941182B2 Buried sublevel metallizations for improved transistor density 有权
标题翻译：埋层次级金属化，以提高晶体管密度
公开(公告)号：US08941182B2
公开(公告)日：2015-01-27
申请号：US13154548
申请日：2011-06-07
申请人： Kai Frohberg , Dominik Olligs , Jens Heinrich , Katrin Reiche
发明人： Kai Frohberg , Dominik Olligs , Jens Heinrich , Katrin Reiche
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/768 , H01L21/8238
CPC分类号： H01L21/823475 , H01L21/76801 , H01L21/76816 , H01L21/76895 , H01L21/823871
摘要： Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein electrical interconnects between circuit elements based on a buried sublevel metallization may provide improved transistor density. One illustrative method disclosed herein includes forming a contact dielectric layer above first and second transistor elements of a semiconductor device, and after forming the contact dielectric layer, forming a buried conductive element below an upper surface of the contact dielectric layer, the conductive element providing an electrical connection between the first and second transistor elements.
摘要翻译：通常，本文公开的主题涉及现代复杂的半导体器件及其形成方法，其中基于掩埋的次级金属化的电路元件之间的电互连可以提供改善的晶体管密度。本文公开的一种说明性方法包括在半导体器件的第一和第二晶体管元件上形成接触电介质层，并且在形成接触电介质层之后，在接触电介质层的上表面下方形成掩埋导电元件，导电元件提供第一和第二晶体管元件之间的电连接。

25. 发明申请

US20130072016A1 METHODS OF FORMING CONDUCTIVE CONTACTS WITH REDUCED DIMENSIONS 有权
标题翻译：形成具有减小尺寸的导电性接触的方法
公开(公告)号：US20130072016A1
公开(公告)日：2013-03-21
申请号：US13237011
申请日：2011-09-20
申请人： Kai Frohberg , Dominik Olligs , Daniel Prochnow , Katrin Reiche
发明人： Kai Frohberg , Dominik Olligs , Daniel Prochnow , Katrin Reiche
IPC分类号： H01L21/28
CPC分类号： H01L29/665 , H01L21/76814 , H01L21/76816 , H01L21/76831 , H01L29/6659 , H01L29/7833
摘要： Disclosed herein are various methods of forming conductive contacts with reduced dimensions and various semiconductor devices incorporating such conductive contacts. In one example, one method disclosed herein includes forming a layer of insulating material above a semiconducting substrate, wherein the layer of material has a first thickness, forming a plurality of contact openings in the layer of material having the first thickness and forming an organic material in at least a portion of each of the contact openings. This illustrative method further includes the steps of, after forming the organic material, performing an etching process to reduce the first thickness of the layer of insulating material to a second thickness that is less than the first thickness, after performing the etching process, removing the organic material from the contact openings and forming a conductive contact in each of the contact openings.
摘要翻译：本文公开了形成具有减小的尺寸的导电触点和结合这种导电触点的各种半导体器件的各种方法。在一个示例中，本文公开的一种方法包括在半导体衬底上形成绝缘材料层，其中材料层具有第一厚度，在具有第一厚度的材料层中形成多个接触开口并形成有机材料在每个接触开口的至少一部分中。该说明性方法还包括以下步骤：在形成有机材料之后，进行蚀刻工艺，以在绝缘材料层的第一厚度减小至小于第一厚度的第二厚度之后，在进行蚀刻工艺之后，来自接触开口的有机材料，并在每个接触开口中形成导电接触。

26. 发明申请

US20090242955A1 Integrated Circuit, Memory Device and Methods of Manufacturing the Same 审中-公开
标题翻译：集成电路，存储器件及其制造方法
公开(公告)号：US20090242955A1
公开(公告)日：2009-10-01
申请号：US12059469
申请日：2008-03-31
申请人： Dominik Olligs
发明人： Dominik Olligs
IPC分类号： H01L29/788 , H01L21/336 , H01L27/115 , H01L21/8247
CPC分类号： H01L27/11524 , H01L27/11521 , H01L27/11568 , H01L29/66825 , H01L29/66833 , H01L29/78 , H01L29/7881 , H01L29/792
摘要： An integrated circuit includes: a contact structure with a first stack of at least two conductive layers, and a gate electrode with a second stack of conductive layers, the second stack of layers having the same sequence of conductive layers as the first stack.
摘要翻译：集成电路包括：具有至少两个导电层的第一堆叠的接触结构，以及具有第二层导电层的栅电极，所述第二层叠层具有与第一堆叠相同的导电层序列。

27. 发明授权

US07589019B2 Memory cell array and method of forming a memory cell array 有权
标题翻译：存储单元阵列和形成存储单元阵列的方法
公开(公告)号：US07589019B2
公开(公告)日：2009-09-15
申请号：US11443432
申请日：2006-05-31
申请人： Dominik Olligs , Veronika Polei
发明人： Dominik Olligs , Veronika Polei
IPC分类号： H01L21/44 , H01L29/40
CPC分类号： H01L27/115
摘要： A memory cell array includes a plurality of first conductive lines running in a first direction, where the first conductive lines have a pitch Bp, a plurality of second conductive lines, and a plurality of memory cells. Each of the memory cells are at least partially formed in a semiconductor substrate and are accessible by addressing at least a corresponding one of the first conductive lines and at least a corresponding one of the second conductive lines. The memory cell array further includes a plurality of supporting lines, where the supporting lines have a pitch Mp and are disposed above the first and second conductive lines, and a plurality of supporting contacts. The first conductive lines are connected with corresponding ones of the supporting lines via the supporting contacts, and Mp is larger than Bp.
摘要翻译：存储单元阵列包括沿第一方向延伸的多条第一导线，其中第一导线具有间距Bp，多条第二导线和多个存储单元。每个存储单元至少部分地形成在半导体衬底中，并且可以通过寻址至少对应的一个第一导线和至少相应的一个第二导线。存储单元阵列还包括多个支撑线，其中支撑线具有间距Mp并且设置在第一和第二导线上方，以及多个支撑触点。第一导线通过支撑触点与相应的支撑线连接，Mp大于Bp。

28. 发明授权

US07320934B2 Method of forming a contact in a flash memory device 有权
标题翻译：在闪速存储器件中形成触点的方法
公开(公告)号：US07320934B2
公开(公告)日：2008-01-22
申请号：US11157143
申请日：2005-06-20
申请人： Nicolas Nagel , Dominik Olligs
发明人： Nicolas Nagel , Dominik Olligs
IPC分类号： H01L21/4763
CPC分类号： H01L27/115 , H01L21/76802 , H01L21/76895 , H01L27/11568
摘要： A method of forming a contact between a bitline and a local interconnect in a flash memory device comprises forming a hard mask layer on a planarized surface that includes an exposed top section of the local interconnects prior to depositing an oxide dielectric layer. The hard mask layer may be composed of a material that has an etch resistance as compared to the interlayer dielectric material, e.g., nitride. Openings in the hard mask define positions for the contacts to the local interconnects exposed in the top section.
摘要翻译：在闪速存储器件中形成位线和局部互连之间的接触的方法包括在沉积氧化物介电层之前在平坦化表面上形成硬掩模层，其包括局部互连的暴露的顶部部分。硬掩模层可以由与层间电介质材料（例如氮化物）相比具有耐蚀刻性的材料构成。硬掩模中的开口定义了与顶部暴露的局部互连的触点的位置。

29. 发明申请

US20070278546A1 Memory cell array and method of forming a memory cell array 有权
标题翻译：存储单元阵列和形成存储单元阵列的方法
公开(公告)号：US20070278546A1
公开(公告)日：2007-12-06
申请号：US11443432
申请日：2006-05-31
申请人： Dominik Olligs , Veronika Polei
发明人： Dominik Olligs , Veronika Polei
IPC分类号： H01L29/94
CPC分类号： H01L27/115
摘要： A memory cell array includes a plurality of first conductive lines running in a first direction, where the first conductive lines have a pitch Bp, a plurality of second conductive lines, and a plurality of memory cells. Each of the memory cells are at least partially formed in a semiconductor substrate and are accessible by addressing at least a corresponding one of the first conductive lines and at least a corresponding one of the second conductive lines. The memory cell array further includes a plurality of supporting lines, where the supporting lines have a pitch Mp and are disposed above the first and second conductive lines, and a plurality of supporting contacts. The first conductive lines are connected with corresponding ones of the supporting lines via the supporting contacts, and Mp is larger than Bp.
摘要翻译：存储单元阵列包括沿第一方向延伸的多条第一导线，其中第一导线具有间距Bp，多条第二导线和多个存储单元。每个存储单元至少部分地形成在半导体衬底中，并且可以通过寻址至少对应的一个第一导线和至少相应的一个第二导线。存储单元阵列还包括多个支撑线，其中支撑线具有间距Mp并且设置在第一和第二导线上方，以及多个支撑触点。第一导线通过支撑触点与相应的支撑线连接，Mp大于Bp。

30. 发明申请

US20070238240A1 Method of forming a transistor in a non-volatile memory device 审中-公开
标题翻译：在非易失性存储器件中形成晶体管的方法
公开(公告)号：US20070238240A1
公开(公告)日：2007-10-11
申请号：US11392240
申请日：2006-03-29
申请人： Dominik Olligs , Florian Beug , Ricardo Mikalo
发明人： Dominik Olligs , Florian Beug , Ricardo Mikalo
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L27/11568
摘要： A field-effect transistor is formed that has spacers formed by etching openings into a conductive layer and filling the openings with spacer material. The openings are formed together with a gate web in the conductive layer, wherein the gate web is surrounded by the openings on at least two sides. The spacers serve to define lightly doped drain regions arranged in the underlying substrate between a highly doped drain region and a channel region of the transistor. The transistor thus formed is specifically suited for providing high-voltage currents to memory cells of a non-volatile memory array.
摘要翻译：形成场效应晶体管，其具有通过将开口蚀刻到导电层中并用间隔物材料填充开口而形成的间隔物。开口与导电层中的栅极网一起形成，其中栅极网在至少两侧上由开口包围。间隔物用于限定在高掺杂漏极区域和晶体管的沟道区域之间布置在下面的衬底中的轻掺杂漏极区域。这样形成的晶体管特别适于向非易失性存储器阵列的存储单元提供高电压电流。

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