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1. 发明授权

US08492217B2 Methods of forming conductive contacts with reduced dimensions 有权
标题翻译：形成尺寸减小的导电触点的方法
公开(公告)号：US08492217B2
公开(公告)日：2013-07-23
申请号：US13237011
申请日：2011-09-20
申请人： Kai Frohberg , Dominik Olligs , Daniel Prochnow , Katrin Reiche
发明人： Kai Frohberg , Dominik Olligs , Daniel Prochnow , Katrin Reiche
IPC分类号： H01L21/8238
CPC分类号： H01L29/665 , H01L21/76814 , H01L21/76816 , H01L21/76831 , H01L29/6659 , H01L29/7833
摘要： Disclosed herein are various methods of forming conductive contacts with reduced dimensions and various semiconductor devices incorporating such conductive contacts. In one example, one method disclosed herein includes forming a layer of insulating material above a semiconducting substrate, wherein the layer of material has a first thickness, forming a plurality of contact openings in the layer of material having the first thickness and forming an organic material in at least a portion of each of the contact openings. This illustrative method further includes the steps of, after forming the organic material, performing an etching process to reduce the first thickness of the layer of insulating material to a second thickness that is less than the first thickness, after performing the etching process, removing the organic material from the contact openings and forming a conductive contact in each of the contact openings.
摘要翻译：本文公开了形成具有减小的尺寸的导电触点和结合这种导电触点的各种半导体器件的各种方法。在一个示例中，本文公开的一种方法包括在半导体衬底上形成绝缘材料层，其中材料层具有第一厚度，在具有第一厚度的材料层中形成多个接触开口并形成有机材料在每个接触开口的至少一部分中。该说明性方法还包括以下步骤：在形成有机材料之后，进行蚀刻工艺，以在绝缘材料层的第一厚度减小至小于第一厚度的第二厚度之后，在进行蚀刻工艺之后，来自接触开口的有机材料，并在每个接触开口中形成导电接触。

2. 发明申请

US20130072016A1 METHODS OF FORMING CONDUCTIVE CONTACTS WITH REDUCED DIMENSIONS 有权
标题翻译：形成具有减小尺寸的导电性接触的方法
公开(公告)号：US20130072016A1
公开(公告)日：2013-03-21
申请号：US13237011
申请日：2011-09-20
申请人： Kai Frohberg , Dominik Olligs , Daniel Prochnow , Katrin Reiche
发明人： Kai Frohberg , Dominik Olligs , Daniel Prochnow , Katrin Reiche
IPC分类号： H01L21/28
CPC分类号： H01L29/665 , H01L21/76814 , H01L21/76816 , H01L21/76831 , H01L29/6659 , H01L29/7833
摘要： Disclosed herein are various methods of forming conductive contacts with reduced dimensions and various semiconductor devices incorporating such conductive contacts. In one example, one method disclosed herein includes forming a layer of insulating material above a semiconducting substrate, wherein the layer of material has a first thickness, forming a plurality of contact openings in the layer of material having the first thickness and forming an organic material in at least a portion of each of the contact openings. This illustrative method further includes the steps of, after forming the organic material, performing an etching process to reduce the first thickness of the layer of insulating material to a second thickness that is less than the first thickness, after performing the etching process, removing the organic material from the contact openings and forming a conductive contact in each of the contact openings.
摘要翻译：本文公开了形成具有减小的尺寸的导电触点和结合这种导电触点的各种半导体器件的各种方法。在一个示例中，本文公开的一种方法包括在半导体衬底上形成绝缘材料层，其中材料层具有第一厚度，在具有第一厚度的材料层中形成多个接触开口并形成有机材料在每个接触开口的至少一部分中。该说明性方法还包括以下步骤：在形成有机材料之后，进行蚀刻工艺，以在绝缘材料层的第一厚度减小至小于第一厚度的第二厚度之后，在进行蚀刻工艺之后，来自接触开口的有机材料，并在每个接触开口中形成导电接触。

3. 发明申请

US20120313176A1 Buried Sublevel Metallizations for Improved Transistor Density 有权
标题翻译：用于改善晶体管密度的埋层次级金属化
公开(公告)号：US20120313176A1
公开(公告)日：2012-12-13
申请号：US13154548
申请日：2011-06-07
申请人： Kai Frohberg , Dominik Olligs , Jens Heinrich , Katrin Reiche
发明人： Kai Frohberg , Dominik Olligs , Jens Heinrich , Katrin Reiche
IPC分类号： H01L27/088 , H01L21/768
CPC分类号： H01L21/823475 , H01L21/76801 , H01L21/76816 , H01L21/76895 , H01L21/823871
摘要： Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein electrical interconnects between circuit elements based on a buried sublevel metallization may provide improved transistor density. One illustrative method disclosed herein includes forming a contact dielectric layer above first and second transistor elements of a semiconductor device, and after forming the contact dielectric layer, forming a buried conductive element below an upper surface of the contact dielectric layer, the conductive element providing an electrical connection between the first and second transistor elements.
摘要翻译：通常，本文公开的主题涉及现代复杂的半导体器件及其形成方法，其中基于掩埋的次级金属化的电路元件之间的电互连可以提供改善的晶体管密度。本文公开的一种说明性方法包括在半导体器件的第一和第二晶体管元件上形成接触电介质层，并且在形成接触电介质层之后，在接触电介质层的上表面下方形成掩埋导电元件，导电元件提供第一和第二晶体管元件之间的电连接。

4. 发明授权

US08941182B2 Buried sublevel metallizations for improved transistor density 有权
标题翻译：埋层次级金属化，以提高晶体管密度
公开(公告)号：US08941182B2
公开(公告)日：2015-01-27
申请号：US13154548
申请日：2011-06-07
申请人： Kai Frohberg , Dominik Olligs , Jens Heinrich , Katrin Reiche
发明人： Kai Frohberg , Dominik Olligs , Jens Heinrich , Katrin Reiche
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/768 , H01L21/8238
CPC分类号： H01L21/823475 , H01L21/76801 , H01L21/76816 , H01L21/76895 , H01L21/823871
摘要： Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein electrical interconnects between circuit elements based on a buried sublevel metallization may provide improved transistor density. One illustrative method disclosed herein includes forming a contact dielectric layer above first and second transistor elements of a semiconductor device, and after forming the contact dielectric layer, forming a buried conductive element below an upper surface of the contact dielectric layer, the conductive element providing an electrical connection between the first and second transistor elements.
摘要翻译：通常，本文公开的主题涉及现代复杂的半导体器件及其形成方法，其中基于掩埋的次级金属化的电路元件之间的电互连可以提供改善的晶体管密度。本文公开的一种说明性方法包括在半导体器件的第一和第二晶体管元件上形成接触电介质层，并且在形成接触电介质层之后，在接触电介质层的上表面下方形成掩埋导电元件，导电元件提供第一和第二晶体管元件之间的电连接。

5. 发明授权

US08361844B2 Method for adjusting the height of a gate electrode in a semiconductor device 有权
标题翻译：用于调整半导体器件中的栅电极的高度的方法
公开(公告)号：US08361844B2
公开(公告)日：2013-01-29
申请号：US12754359
申请日：2010-04-05
申请人： Kai Frohberg , Heike Berthold , Katrin Reiche , Uwe Griebenow
发明人： Kai Frohberg , Heike Berthold , Katrin Reiche , Uwe Griebenow
IPC分类号： H01L21/335
CPC分类号： H01L21/28123 , H01L29/6653 , H01L29/66545 , H01L29/66575
摘要： By providing an implantation blocking material on the gate electrode structures of advanced semiconductor devices during high energy implantation processes, the required shielding effect with respect to the channel regions of the transistors may be accomplished. In a later manufacturing stage, the implantation blocking portion may be removed to reduce the gate electrode height to a desired level in order to enhance the process conditions during the deposition of an interlayer dielectric material, thereby significantly reducing the risk of creating irregularities, such as voids, in the interlayer dielectric material, even in densely packed device regions.
摘要翻译：通过在高能注入工艺期间在先进的半导体器件的栅电极结构上提供注入阻挡材料，可以实现相对于晶体管的沟道区所需的屏蔽效应。在稍后的制造阶段中，可以移除注入阻挡部分以将栅极电极的高度降低到期望的水平，以便在层间电介质材料的沉积期间增强工艺条件，从而显着降低产生不规则性的风险，例如在层间电介质材料中，甚至在密集装填区域也是空隙。

6. 发明申请

US20120115326A1 Method of Forming Metal Silicide Regions 审中-公开
标题翻译：形成金属硅化物区域的方法
公开(公告)号：US20120115326A1
公开(公告)日：2012-05-10
申请号：US12942116
申请日：2010-11-09
申请人： Kai Frohberg , Jens Heinrich , Katrin Reiche
发明人： Kai Frohberg , Jens Heinrich , Katrin Reiche
IPC分类号： H01L21/321
CPC分类号： H01L21/28052 , H01L21/28518 , H01L29/41783 , H01L29/665
摘要： The method described herein involves the formation of metal silicide regions. The method may involve forming a layer of refractory metal on a structure comprising silicon, forming a layer of silicon on the layer of refractory metal and, after forming the layer of silicon, performing at least one heat treatment process to form a metal silicide region in the structure.
摘要翻译：本文描述的方法涉及形成金属硅化物区域。该方法可以包括在包含硅的结构上形成难熔金属层，在难熔金属层上形成硅层，在形成硅层之后，进行至少一个热处理工艺以形成金属硅化物区域结构。

7. 发明授权

US08349744B2 Double deposition of a stress-inducing layer in an interlayer dielectric with intermediate stress relaxation in a semiconductor device 有权
标题翻译：在半导体器件中具有中等应力松弛的层间电介质中的应力诱导层双重沉积
公开(公告)号：US08349744B2
公开(公告)日：2013-01-08
申请号：US12272273
申请日：2008-11-17
申请人： Kai Frohberg , Uwe Griebenow , Katrin Reiche , Heike Berthold
发明人： Kai Frohberg , Uwe Griebenow , Katrin Reiche , Heike Berthold
IPC分类号： H01L21/31
CPC分类号： H01L21/823807 , H01L29/7843
摘要： Enhanced efficiency of a stress relaxation implantation process may be achieved by depositing a first layer of reduced thickness and relaxing the same at certain device regions, thereby obtaining an enhanced amount of substantially relaxed dielectric material in close proximity to the transistor under consideration, wherein a desired high amount of stressed dielectric material may be obtained above other transistors by performing a further deposition process. Hence, the negative effect of the highly stressed dielectric material for specific transistors, for instance in densely packed device regions, may be significantly reduced by depositing the highly stressed dielectric material in two steps with an intermediate relaxation implantation process.
摘要翻译：应力松弛注入工艺的增强的效率可以通过沉积厚度较小的第一层并在某些器件区域放松应力松弛注入工艺，从而获得在考虑的晶体管附近获得增加量的基本上松弛的电介质材料，其中期望的通过进行另外的沉积工艺，可以在其它晶体管之上获得大量的应力介电材料。因此，通过用中间松弛注入工艺在两个步骤中沉积高应力电介质材料，可以显着地降低高应力电介质材料对特定晶体管（例如密集封装器件区域）的负面影响。

8. 发明授权

US08318598B2 Contacts and vias of a semiconductor device formed by a hard mask and double exposure 有权
标题翻译：通过硬掩模和双重曝光形成的半导体器件的触点和通孔
公开(公告)号：US08318598B2
公开(公告)日：2012-11-27
申请号：US12537321
申请日：2009-08-07
申请人： Sven Beyer , Kai Frohberg , Katrin Reiche , Kerstin Ruttloff
发明人： Sven Beyer , Kai Frohberg , Katrin Reiche , Kerstin Ruttloff
IPC分类号： H01L21/4763
CPC分类号： H01L21/31144 , H01L21/76816 , H01L21/76897
摘要： A contact element may be formed on the basis of a hard mask, which may be patterned on the basis of a first resist mask and on the basis of a second resist mask, to define an appropriate intersection area which may represent the final design dimensions of the contact element. Consequently, each of the resist masks may be formed on the basis of a photolithography process with less restrictive constraints, since at least one of the lateral dimensions may be selected as a non-critical dimension in each of the two resist masks.
摘要翻译：可以基于硬掩模形成接触元件，硬掩模可以基于第一抗蚀剂掩模并且基于第二抗蚀剂掩模来图案化，以限定适当的交叉区域，其可以表示最终的设计尺寸接触元件。因此，可以基于具有较少限制性约束的光刻工艺来形成每个抗蚀剂掩模，因为在两个抗蚀剂掩模中的每一个中可以选择至少一个横向尺寸作为非临界尺寸。

9. 发明申请

US20130189822A1 METHODS OF FABRICATING INTEGRATED CIRCUITS WITH THE ELIMINATION OF VOIDS IN INTERLAYER DIELECTICS 审中-公开
标题翻译：一体化电路消除中间层电路中的失调的方法
公开(公告)号：US20130189822A1
公开(公告)日：2013-07-25
申请号：US13357285
申请日：2012-01-24
申请人： Kai Frohberg , Torsten Huisinga , Katrin Reiche
发明人： Kai Frohberg , Torsten Huisinga , Katrin Reiche
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/823475 , H01L29/7833
摘要： Methods are provided for fabricating integrated circuits that include forming first and second spaced apart gate structures overlying a semiconductor substrate, and forming first and second spaced apart source/drain regions in the semiconductor substrate between the gate structures. A first layer of insulating material is deposited overlying the gate structures and the source/drain regions by a process of atomic layer deposition, and a second layer of insulating material is deposited overlying the first layer by a process of chemical vapor deposition. First and second openings are etched through the second layer and the first layer to expose portions of the source/drain regions. The first and second openings are filled with conductive material to form first and second spaced apart contacts, electrically isolated from each other, in electrical contact with the first and second source/drain regions.
摘要翻译：提供了用于制造集成电路的方法，其包括形成覆盖半导体衬底的第一和第二间隔开的栅极结构，以及在栅极结构之间的半导体衬底中形成第一和第二间隔开的源/漏区。通过原子层沉积的过程沉积覆盖栅极结构和源极/漏极区的第一绝缘材料层，并且通过化学气相沉积工艺将第二层绝缘材料沉积在第一层上。通过第二层和第一层蚀刻第一和第二开口以暴露源/漏区的部分。第一和第二开口用导电材料填充以形成与第一和第二源极/漏极区域电接触的彼此电隔离的第一和第二间隔开的触点。

10. 发明授权

US08440534B2 Threshold adjustment for MOS devices by adapting a spacer width prior to implantation 有权
公开(公告)号：US08440534B2
公开(公告)日：2013-05-14
申请号：US13104474
申请日：2011-05-10
申请人： Uwe Griebenow , Jan Hoentschel , Kai Frohberg , Heike Berthold , Katrin Reiche , Frank Feustel , Kerstin Ruttloff
发明人： Uwe Griebenow , Jan Hoentschel , Kai Frohberg , Heike Berthold , Katrin Reiche , Frank Feustel , Kerstin Ruttloff
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/6656 , H01L21/26513 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/6653 , H01L29/7836
摘要： Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes.

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