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1. 发明授权

US08492217B2 Methods of forming conductive contacts with reduced dimensions 有权
标题翻译：形成尺寸减小的导电触点的方法
公开(公告)号：US08492217B2
公开(公告)日：2013-07-23
申请号：US13237011
申请日：2011-09-20
申请人： Kai Frohberg , Dominik Olligs , Daniel Prochnow , Katrin Reiche
发明人： Kai Frohberg , Dominik Olligs , Daniel Prochnow , Katrin Reiche
IPC分类号： H01L21/8238
CPC分类号： H01L29/665 , H01L21/76814 , H01L21/76816 , H01L21/76831 , H01L29/6659 , H01L29/7833
摘要： Disclosed herein are various methods of forming conductive contacts with reduced dimensions and various semiconductor devices incorporating such conductive contacts. In one example, one method disclosed herein includes forming a layer of insulating material above a semiconducting substrate, wherein the layer of material has a first thickness, forming a plurality of contact openings in the layer of material having the first thickness and forming an organic material in at least a portion of each of the contact openings. This illustrative method further includes the steps of, after forming the organic material, performing an etching process to reduce the first thickness of the layer of insulating material to a second thickness that is less than the first thickness, after performing the etching process, removing the organic material from the contact openings and forming a conductive contact in each of the contact openings.
摘要翻译：本文公开了形成具有减小的尺寸的导电触点和结合这种导电触点的各种半导体器件的各种方法。在一个示例中，本文公开的一种方法包括在半导体衬底上形成绝缘材料层，其中材料层具有第一厚度，在具有第一厚度的材料层中形成多个接触开口并形成有机材料在每个接触开口的至少一部分中。该说明性方法还包括以下步骤：在形成有机材料之后，进行蚀刻工艺，以在绝缘材料层的第一厚度减小至小于第一厚度的第二厚度之后，在进行蚀刻工艺之后，来自接触开口的有机材料，并在每个接触开口中形成导电接触。

2. 发明申请

US20130072016A1 METHODS OF FORMING CONDUCTIVE CONTACTS WITH REDUCED DIMENSIONS 有权
标题翻译：形成具有减小尺寸的导电性接触的方法
公开(公告)号：US20130072016A1
公开(公告)日：2013-03-21
申请号：US13237011
申请日：2011-09-20
申请人： Kai Frohberg , Dominik Olligs , Daniel Prochnow , Katrin Reiche
发明人： Kai Frohberg , Dominik Olligs , Daniel Prochnow , Katrin Reiche
IPC分类号： H01L21/28
CPC分类号： H01L29/665 , H01L21/76814 , H01L21/76816 , H01L21/76831 , H01L29/6659 , H01L29/7833
摘要： Disclosed herein are various methods of forming conductive contacts with reduced dimensions and various semiconductor devices incorporating such conductive contacts. In one example, one method disclosed herein includes forming a layer of insulating material above a semiconducting substrate, wherein the layer of material has a first thickness, forming a plurality of contact openings in the layer of material having the first thickness and forming an organic material in at least a portion of each of the contact openings. This illustrative method further includes the steps of, after forming the organic material, performing an etching process to reduce the first thickness of the layer of insulating material to a second thickness that is less than the first thickness, after performing the etching process, removing the organic material from the contact openings and forming a conductive contact in each of the contact openings.
摘要翻译：本文公开了形成具有减小的尺寸的导电触点和结合这种导电触点的各种半导体器件的各种方法。在一个示例中，本文公开的一种方法包括在半导体衬底上形成绝缘材料层，其中材料层具有第一厚度，在具有第一厚度的材料层中形成多个接触开口并形成有机材料在每个接触开口的至少一部分中。该说明性方法还包括以下步骤：在形成有机材料之后，进行蚀刻工艺，以在绝缘材料层的第一厚度减小至小于第一厚度的第二厚度之后，在进行蚀刻工艺之后，来自接触开口的有机材料，并在每个接触开口中形成导电接触。

3. 发明申请

US20120313176A1 Buried Sublevel Metallizations for Improved Transistor Density 有权
标题翻译：用于改善晶体管密度的埋层次级金属化
公开(公告)号：US20120313176A1
公开(公告)日：2012-12-13
申请号：US13154548
申请日：2011-06-07
申请人： Kai Frohberg , Dominik Olligs , Jens Heinrich , Katrin Reiche
发明人： Kai Frohberg , Dominik Olligs , Jens Heinrich , Katrin Reiche
IPC分类号： H01L27/088 , H01L21/768
CPC分类号： H01L21/823475 , H01L21/76801 , H01L21/76816 , H01L21/76895 , H01L21/823871
摘要： Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein electrical interconnects between circuit elements based on a buried sublevel metallization may provide improved transistor density. One illustrative method disclosed herein includes forming a contact dielectric layer above first and second transistor elements of a semiconductor device, and after forming the contact dielectric layer, forming a buried conductive element below an upper surface of the contact dielectric layer, the conductive element providing an electrical connection between the first and second transistor elements.
摘要翻译：通常，本文公开的主题涉及现代复杂的半导体器件及其形成方法，其中基于掩埋的次级金属化的电路元件之间的电互连可以提供改善的晶体管密度。本文公开的一种说明性方法包括在半导体器件的第一和第二晶体管元件上形成接触电介质层，并且在形成接触电介质层之后，在接触电介质层的上表面下方形成掩埋导电元件，导电元件提供第一和第二晶体管元件之间的电连接。

4. 发明授权

US08941182B2 Buried sublevel metallizations for improved transistor density 有权
标题翻译：埋层次级金属化，以提高晶体管密度
公开(公告)号：US08941182B2
公开(公告)日：2015-01-27
申请号：US13154548
申请日：2011-06-07
申请人： Kai Frohberg , Dominik Olligs , Jens Heinrich , Katrin Reiche
发明人： Kai Frohberg , Dominik Olligs , Jens Heinrich , Katrin Reiche
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/768 , H01L21/8238
CPC分类号： H01L21/823475 , H01L21/76801 , H01L21/76816 , H01L21/76895 , H01L21/823871
摘要： Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein electrical interconnects between circuit elements based on a buried sublevel metallization may provide improved transistor density. One illustrative method disclosed herein includes forming a contact dielectric layer above first and second transistor elements of a semiconductor device, and after forming the contact dielectric layer, forming a buried conductive element below an upper surface of the contact dielectric layer, the conductive element providing an electrical connection between the first and second transistor elements.
摘要翻译：通常，本文公开的主题涉及现代复杂的半导体器件及其形成方法，其中基于掩埋的次级金属化的电路元件之间的电互连可以提供改善的晶体管密度。本文公开的一种说明性方法包括在半导体器件的第一和第二晶体管元件上形成接触电介质层，并且在形成接触电介质层之后，在接触电介质层的上表面下方形成掩埋导电元件，导电元件提供第一和第二晶体管元件之间的电连接。

5. 发明授权

US08536052B2 Semiconductor device comprising contact elements with silicided sidewall regions 有权
标题翻译：半导体器件包括具有硅化物侧壁区域的接触元件
公开(公告)号：US08536052B2
公开(公告)日：2013-09-17
申请号：US13208835
申请日：2011-08-12
申请人： Jens Heinrich , Kai Frohberg , Katrin Reiche
发明人： Jens Heinrich , Kai Frohberg , Katrin Reiche
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/76844 , H01L21/76855 , H01L23/53266 , H01L29/665 , H01L29/66575 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： When forming a metal silicide within contact openings in complex semiconductor devices, a silicidation of sidewall surface areas of the contact openings may be initiated by forming a silicon layer therein, thereby reducing unwanted diffusion of the refractory metal species into the laterally adjacent dielectric material. In this manner, superior reliability and electrical performance of the resulting contact elements may be achieved on the basis of a late silicide process.
摘要翻译：当在复合半导体器件的接触开口内形成金属硅化物时，可以通过在其中形成硅层来引发接触开口的侧壁表面区域的硅化，从而减少难熔金属物质进入横向相邻电介质材料的不想要的扩散。以这种方式，可以基于后期硅化物工艺实现所得到的接触元件的优异的可靠性和电性能。

6. 发明申请

US20120161324A1 Semiconductor Device Comprising Contact Elements with Silicided Sidewall Regions 有权
标题翻译：包含接触元件与硅化物侧壁区域的半导体器件
公开(公告)号：US20120161324A1
公开(公告)日：2012-06-28
申请号：US13208835
申请日：2011-08-12
申请人： Jens Heinrich , Kai Frohberg , Katrin Reiche
发明人： Jens Heinrich , Kai Frohberg , Katrin Reiche
IPC分类号： H01L23/482 , H01L21/26
CPC分类号： H01L21/28518 , H01L21/76844 , H01L21/76855 , H01L23/53266 , H01L29/665 , H01L29/66575 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： When forming a metal silicide within contact openings in complex semiconductor devices, a silicidation of sidewall surface areas of the contact openings may be initiated by forming a silicon layer therein, thereby reducing unwanted diffusion of the refractory metal species into the laterally adjacent dielectric material. In this manner, superior reliability and electrical performance of the resulting contact elements may be achieved on the basis of a late silicide process.
摘要翻译：当在复合半导体器件的接触开口内形成金属硅化物时，可以通过在其中形成硅层来引发接触开口的侧壁表面区域的硅化，从而减少难熔金属物质进入横向相邻电介质材料的不想要的扩散。以这种方式，可以基于后期硅化物工艺实现所得到的接触元件的优异的可靠性和电性能。

7. 发明申请

US20100078823A1 CONTACTS AND VIAS OF A SEMICONDUCTOR DEVICE FORMED BY A HARD MASK AND DOUBLE EXPOSURE 有权
标题翻译：通过硬掩模和双重暴露形成的半导体器件的接触和孔
公开(公告)号：US20100078823A1
公开(公告)日：2010-04-01
申请号：US12537321
申请日：2009-08-07
申请人： Sven Beyer , Kai Frohberg , Katrin Reiche , Kerstin Ruttloff
发明人： Sven Beyer , Kai Frohberg , Katrin Reiche , Kerstin Ruttloff
IPC分类号： H01L23/522 , H01L21/306
CPC分类号： H01L21/31144 , H01L21/76816 , H01L21/76897
摘要： A contact element may be formed on the basis of a hard mask, which may be patterned on the basis of a first resist mask and on the basis of a second resist mask, to define an appropriate intersection area which may represent the final design dimensions of the contact element. Consequently, each of the resist masks may be formed on the basis of a photolithography process with less restrictive constraints, since at least one of the lateral dimensions may be selected as a non-critical dimension in each of the two resist masks.
摘要翻译：可以基于硬掩模形成接触元件，硬掩模可以基于第一抗蚀剂掩模并且基于第二抗蚀剂掩模来图案化，以限定适当的交叉区域，其可以表示最终的设计尺寸接触元件。因此，可以基于具有较少限制性约束的光刻工艺来形成每个抗蚀剂掩模，因为在两个抗蚀剂掩模中的每一个中可以选择至少一个横向尺寸作为非临界尺寸。

8. 发明申请

US20090294868A1 DRIVE CURRENT ADJUSTMENT FOR TRANSISTORS FORMED IN THE SAME ACTIVE REGION BY LOCALLY INDUCING DIFFERENT LATERAL STRAIN LEVELS IN THE ACTIVE REGION 审中-公开
标题翻译：通过局部诱导活跃区域中不同的侧向应变水平在同一活跃区域形成的晶体管的驱动电流调整
公开(公告)号：US20090294868A1
公开(公告)日：2009-12-03
申请号：US12424095
申请日：2009-04-15
申请人： Uwe Griebenow , Kai Frohberg , Kerstin Ruttloff , Katrin Reiche
发明人： Uwe Griebenow , Kai Frohberg , Kerstin Ruttloff , Katrin Reiche
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823412 , H01L21/823425 , H01L21/823807 , H01L29/7843
摘要： The drive current capability of a pull-down transistor and a pass transistor formed in a common active region may be adjusted on the basis of a strain-inducing mechanism, such as a stressed dielectric material and a stress memorization technique, thereby providing a simplified overall geometric configuration of the active region. Hence, static RAM cells may be formed on the basis of a minimum channel length with a simplified configuration of the active region, thereby avoiding significant yield losses as may be observed in sophisticated devices in which a pronounced variation of the transistor width may be used to adjust the ratio of the drive current capabilities for the pull-down transistor and the pass transistor.
摘要翻译：形成在公共有源区域中的下拉晶体管和传输晶体管的驱动电流能力可以基于诸如应力介电材料和应力记忆技术之类的应变诱导机构来调节，从而提供简化的总体活动区域的几何配置。因此，可以基于具有有源区域的简化配置的最小沟道长度形成静态RAM单元，从而避免了在可以使用晶体管宽度的显着变化的复杂器件中可观察到的显着的产量损失调整下拉晶体管和传输晶体管的驱动电流能力的比值。

9. 发明申请

US20130189822A1 METHODS OF FABRICATING INTEGRATED CIRCUITS WITH THE ELIMINATION OF VOIDS IN INTERLAYER DIELECTICS 审中-公开
标题翻译：一体化电路消除中间层电路中的失调的方法
公开(公告)号：US20130189822A1
公开(公告)日：2013-07-25
申请号：US13357285
申请日：2012-01-24
申请人： Kai Frohberg , Torsten Huisinga , Katrin Reiche
发明人： Kai Frohberg , Torsten Huisinga , Katrin Reiche
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/823475 , H01L29/7833
摘要： Methods are provided for fabricating integrated circuits that include forming first and second spaced apart gate structures overlying a semiconductor substrate, and forming first and second spaced apart source/drain regions in the semiconductor substrate between the gate structures. A first layer of insulating material is deposited overlying the gate structures and the source/drain regions by a process of atomic layer deposition, and a second layer of insulating material is deposited overlying the first layer by a process of chemical vapor deposition. First and second openings are etched through the second layer and the first layer to expose portions of the source/drain regions. The first and second openings are filled with conductive material to form first and second spaced apart contacts, electrically isolated from each other, in electrical contact with the first and second source/drain regions.
摘要翻译：提供了用于制造集成电路的方法，其包括形成覆盖半导体衬底的第一和第二间隔开的栅极结构，以及在栅极结构之间的半导体衬底中形成第一和第二间隔开的源/漏区。通过原子层沉积的过程沉积覆盖栅极结构和源极/漏极区的第一绝缘材料层，并且通过化学气相沉积工艺将第二层绝缘材料沉积在第一层上。通过第二层和第一层蚀刻第一和第二开口以暴露源/漏区的部分。第一和第二开口用导电材料填充以形成与第一和第二源极/漏极区域电接触的彼此电隔离的第一和第二间隔开的触点。

10. 发明授权

US08440534B2 Threshold adjustment for MOS devices by adapting a spacer width prior to implantation 有权
公开(公告)号：US08440534B2
公开(公告)日：2013-05-14
申请号：US13104474
申请日：2011-05-10
申请人： Uwe Griebenow , Jan Hoentschel , Kai Frohberg , Heike Berthold , Katrin Reiche , Frank Feustel , Kerstin Ruttloff
发明人： Uwe Griebenow , Jan Hoentschel , Kai Frohberg , Heike Berthold , Katrin Reiche , Frank Feustel , Kerstin Ruttloff
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/6656 , H01L21/26513 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/6653 , H01L29/7836
摘要： Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes.

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