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21. 发明授权

US07974866B2 System and method for managing workflow among a plurality of business processes associated respectively with users having access rights to artifacts 失效
标题翻译：用于在分别与具有对工件的访问权限的用户相关联的多个业务处理中管理工作流的系统和方法
公开(公告)号：US07974866B2
公开(公告)日：2011-07-05
申请号：US11776151
申请日：2007-07-11
申请人： Hiroyuki Akatsu , Kenji Eda , Yo Murai , Teruaki Okano , Yasuharu Yada , Masao Yamada
发明人： Hiroyuki Akatsu , Kenji Eda , Yo Murai , Teruaki Okano , Yasuharu Yada , Masao Yamada
IPC分类号： G06Q10/00
CPC分类号： G06Q10/06 , G06Q10/063 , G06Q10/0633
摘要： A system and method for managing a workflow are provided. A system for managing a workflow in accordance with an embodiment of the invention includes: a storage unit for storing, as an access history for each of at least one artifact, identification information of a business process that has accessed the artifact; a request reception unit for receiving an access request to an artifact from a user; a first notification unit for retrieving an access history corresponding to a first artifact from the storage unit on a condition that a first access request received from the user corresponding to a first business process is an update request of the first artifact, and for notifying a user corresponding to the business process that is identified in the retrieved access history that the first artifact is to be updated; and a history adding unit for adding identification information of the first business process to the access history corresponding to the first artifact in response to an accessing of the first artifact based on the first access request.
摘要翻译：提供了一种用于管理工作流的系统和方法。根据本发明的实施例的用于管理工作流的系统包括：存储单元，用于存储已访问所述工件的业务处理的识别信息作为至少一个工件中的每一个的访问历史; 请求接收单元，用于从用户接收对工件的访问请求; 第一通知单元，用于在从与第一业务处理相对应的用户接收的第一访问请求是第一伪像的更新请求的条件下从存储单元检索与第一伪像相对应的访问历史，并且用于通知用户对应于在检索的访问历史中识别出的第一个工件将被更新的业务流程; 以及历史添加单元，用于响应于基于第一访问请求访问第一伪像，将第一业务处理的标识信息添加到与第一伪像相对应的访问历史。

22. 发明授权

US07425754B2 Structure and method of self-aligned bipolar transistor having tapered collector 有权
标题翻译：具有锥形集电极的自对准双极晶体管的结构和方法
公开(公告)号：US07425754B2
公开(公告)日：2008-09-16
申请号：US10708340
申请日：2004-02-25
申请人： Hiroyuki Akatsu , Rama Divakaruni , Gregory G. Freeman , David R. Greenberg , Marwan H. Khater , William R. Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Gregory G. Freeman , David R. Greenberg , Marwan H. Khater , William R. Tonti
IPC分类号： H01L27/102
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/7378
摘要： A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.
摘要翻译：提供了一种双极晶体管，其包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有基本上较小的面积下表面。双极晶体管还包括覆盖集电极基座的上表面的本征基极，与本征基极导电连接的升高的外部基极和覆盖本征基极的发射极。在特定实施例中，发射器与收集器基座自对准，具有与收集器基座的中心线对准的中心线。

23. 发明申请

US20070096259A1 Fabrication of bipolar transistor having reduced collector-base capacitance 失效
标题翻译：具有减小的集电极 - 基极电容的双极晶体管的制造
公开(公告)号：US20070096259A1
公开(公告)日：2007-05-03
申请号：US11633380
申请日：2006-12-04
申请人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher Schnabel , William Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher Schnabel , William Tonti
IPC分类号： H01L27/082
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/0692 , H01L29/0821
摘要： A method is provided for fabricating a bipolar transistor in which a collector layer is formed which includes an active portion having a relatively high dopant concentration and a second portion which has a lower dopant concentration. An epitaxial intrinsic base layer is formed to overlie the collector layer in conductive communication with the active portion of the collector layer. A low-capacitance region is formed laterally adjacent to the second portion of the collector layer, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer. An emitter layer is formed to overlie the intrinsic base layer.
摘要翻译：提供一种用于制造双极晶体管的方法，其中形成集电极层，其包括具有较高掺杂剂浓度的有源部分和具有较低掺杂剂浓度的第二部分。外延本征基极层形成为覆盖集电极层，与集电极层的有源部分导电连通。低电容区域形成为与集电极层的第二部分横向相邻，低电容区域包括设置在直接位于本征基极层下方的底切处的电介质区域。形成发射极层以覆盖本征基极层。

24. 发明授权

US06485894B1 Method to self-align a lithographic pattern to a workpiece 失效
标题翻译：将光刻图案对准工件的方法
公开(公告)号：US06485894B1
公开(公告)日：2002-11-26
申请号：US09675250
申请日：2000-09-29
申请人： Hiroyuki Akatsu , Franz X. Zach
发明人： Hiroyuki Akatsu , Franz X. Zach
IPC分类号： G03C556
CPC分类号： G03F7/0035 , G03F7/2002
摘要： A method to self-align a lithographic pattern to a workpiece, the method including the steps of obtaining a workpiece having a predetermined pattern of features; modifying at least some of the features so that when a photoresist material is applied to the pattern, there is a substantial difference in reflectivity between two adjacent features, at least one of which has been modified; applying a photoresist material; masklessly exposing the photoresist material; developing the photoresist material, the substantial difference in reflectivity of the two adjacent features causing the developed photoresist material to reveal one adjacent feature but not the other.
摘要翻译：一种将平版印刷图案自对准到工件的方法，该方法包括以下步骤：获得具有预定特征图案的工件; 修改至少一些特征，使得当将光致抗蚀剂材料施加到图案时，两个相邻特征之间的反射率存在显着差异，其中至少一个已被修改; 施加光致抗蚀剂材料; 无光泽地曝光光致抗蚀剂材料; 显影光致抗蚀剂材料，两个相邻特征的反射率的显着差异导致显影的光致抗蚀剂材料显露出一个相邻特征而不是另一个特征。

25. 发明授权

US06387782B2 Process of forming an ultra-shallow junction dopant layer having a peak concentration within a dielectric layer 失效
标题翻译：形成在介电层内具有峰值浓度的超浅结掺杂剂层的工艺
公开(公告)号：US06387782B2
公开(公告)日：2002-05-14
申请号：US09875072
申请日：2001-06-06
申请人： Hiroyuki Akatsu , Omer H. Dokumaci , Suryanarayan G. Hegde , Yujun Li , Rajesh Rengarajan , Paul A. Ronsheim
发明人： Hiroyuki Akatsu , Omer H. Dokumaci , Suryanarayan G. Hegde , Yujun Li , Rajesh Rengarajan , Paul A. Ronsheim
IPC分类号： H01L21336
CPC分类号： H01L21/2652 , H01L21/2254 , H01L21/2255 , H01L29/6659
摘要： A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate. A low thermal budget is maintained because of the proximity of the as-implanted peak concentration to the interface and the presence of species implanted through the dielectric film and into the substrate.
摘要翻译：一种用于在硅衬底内形成超浅结深度掺杂区的工艺。该方法包括在衬底上形成电介质膜，然后将离子掺杂剂物质注入结构中。植入物种的轮廓包括通过电介质膜注入硅衬底中的群体，以及刻意限制在电介质膜中的接近于介电膜和硅衬底之间界面的峰值浓度。使用高能量，低剂量的植入工艺，并且产生基本上不含位错环和其它缺陷簇的结构。使用退火工艺来驱动更接近界面的峰值浓度，以及从电介质膜到硅衬底的最初注入物质的一些群体。由于植入的峰浓度与界面的接近以及通过电介质膜注入并进入衬底的物质的存在，维持了低热量预算。

26. 发明授权

US6039055A Wafer cleaning with dissolved gas concentration control 失效
标题翻译：晶圆清洗采用溶解气浓度控制
公开(公告)号：US6039055A
公开(公告)日：2000-03-21
申请号：US4691
申请日：1998-01-08
申请人： Hiroyuki Akatsu
发明人： Hiroyuki Akatsu
IPC分类号： B08B3/12 , H01L21/00 , B08B6/00
CPC分类号： H01L21/67253 , B08B3/12 , H01L21/67057 , Y10S134/902
摘要： The improved methods and apparatus for cleaning semiconductor wafers and other planar substrates using megasonic cleaning are characterized by the use of monitoring of gas content (i) the liquid flowing to the megasonic cleaning environment, (ii) the liquid in the megasonic cleaning environment, and/or (iii) liquid leaving the megasonic cleaning environment. The methods use information obtained from directly monitoring of the gas content to control the supply of gas-containing liquid to the wafer-cleaning environment to achieve improved cleaning performance on the application of megasonic energy to the cleaning liquid. The gas content information may be used to control the supply of gas containing liquid in real time or may be used to pre-program the controller to achieve a desired gas content in the cleaning bath liquid.
摘要翻译：用于使用兆声波清洗来清洁半导体晶片和其它平面基板的改进方法和装置的特征在于使用监测气体含量（i）流入兆声波清洗环境的液体，（ii）兆声波清洗环境中的液体，以及 /或（iii）离开兆声波清洗环境的液体。该方法使用从直接监测气体含量获得的信息来控制向晶圆清洁环境供应含气体的液体，从而在将超声波能量应用于清洗液时提高清洁性能。气体含量信息可以用于实时控制含气体的供应，或者可以用于对控制器进行预编程，以实现清洗浴液体中所需的气体含量。

27. 发明授权

US5980770A Removal of post-RIE polymer on Al/Cu metal line 失效
标题翻译：在Al / Cu金属线上去除RIE后聚合物
公开(公告)号：US5980770A
公开(公告)日：1999-11-09
申请号：US061565
申请日：1998-04-16
申请人： Ravikumar Ramachandran , Wesley Natzle , Martin Gutsche , Hiroyuki Akatsu , Chien Yu
发明人： Ravikumar Ramachandran , Wesley Natzle , Martin Gutsche , Hiroyuki Akatsu , Chien Yu
IPC分类号： H01L21/302 , H01L21/02 , H01L21/3213 , C03C25/06 , C23F1/12
CPC分类号： H01L21/02071 , H01L21/31138 , H01L21/32136 , Y10S438/906
摘要： A method for removal of post reactive ion etch sidewall polymer rails on a Al/Cu metal line of a semiconductor or microelectronic composite structure comprising:1) supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber in which said composite structure is supported to form a water soluble material of sidewall polymer rails left behind on the Al/Cu metal line from the RIE process; removing the water soluble material with deionized water; and removing photo-resist from said composite structure by either a water-only plasma process or a chemical down stream etching method; or2) forming a water-only plasma process to strip the photo-resist layer of a semiconductor or microelectronic composite structure previously subjected to a RIE process;supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber on which said structure is supported to form a water soluble material of saidwall polymer rails left behind on the Al/Cu metal line from the RIE process; andremoving the water soluble material with deionized water.
摘要翻译：一种用于去除在半导体或微电子复合结构的Al / Cu金属线上的反应活性离子蚀刻侧壁聚合物轨道的方法，包括：1）将蚀刻气体和酸中和气体的混合物供应到真空室中，其中所述复合材料结构被支撑以形成从RIE工艺在Al / Cu金属线上留下的侧壁聚合物轨道的水溶性材料; 用去离子水去除水溶性物质; 以及通过水纯等离子体工艺或化学下游蚀刻方法从所述复合结构中除去光致抗蚀剂; 或2）形成仅水等离子体工艺以剥离先前经过RIE工艺的半导体或微电子复合结构的光致抗蚀剂层; 将一种蚀刻气体和酸中和气体的混合物供给到所述结构被支撑的真空室中，以形成从RIE工艺在Al / Cu金属管线上留下的所述壁聚合物轨道的水溶性材料; 并用去离子水除去水溶性物质。

28. 发明授权

US5934299A Apparatus and method for improved washing and drying of semiconductor wafers 失效
标题翻译：用于改善半导体晶片的洗涤和干燥的装置和方法
公开(公告)号：US5934299A
公开(公告)日：1999-08-10
申请号：US95985
申请日：1998-06-11
申请人： Hiroyuki Akatsu , Ravikumar Ramachandran
发明人： Hiroyuki Akatsu , Ravikumar Ramachandran
IPC分类号： H01L21/304 , H01L21/00 , B08B3/00
CPC分类号： H01L21/67028 , H01L21/67023 , Y10S134/902
摘要： Apparatus and method are provided for improved washing and drying of semiconductor wafers utilizing an enhanced "Marangoni effect" flow of liquid off of the wafers for superior prevention of watermarks (water spots) on integrated circuits (ICs) on the wafers. The apparatus includes a housing 12 which may be hermetically sealed, an open-top wash tank 60 within a lower part of the housing, a moveable rack 16 for holding the wafers either in the tank for washing or in an upper part of the housing for drying, apparatus 34 for supplying chilled (near freezing) de-ionized water (DIW) to a lower part of the tank, the DIW flowing within the tank and overflowing the top thereof, a pump 20 for draining overflowing DIW from the housing, and apparatus 40 for supplying to the housing organic vapor such as isopropyl alcohol (IPA) in a dry gas such as nitrogen. During wafer drying operation of the apparatus the pressure within the housing is kept at about one Torr or less.
摘要翻译：提供了用于利用晶片的液体增强的“马兰戈尼效应”流动来改善半导体晶片的洗涤和干燥的装置和方法，以优越地防止晶片上的集成电路（IC）上的水印（水斑）。该装置包括可以气密密封的壳体12，在壳体的下部内的开放式清洗罐60，用于将晶片保持在用于洗涤的罐中或在壳体的上部中的可移动的支架16 干燥装置34，用于向罐的下部供应冷冻（近冷冻）去离子水（DIW），DIW在罐内流动并溢出其顶部;泵20，用于从壳体排出溢流的DIW;以及用于在诸如氮气的干燥气体中供应到壳体有机蒸气如异丙醇（IPA）的装置40。在设备的晶片干燥操作期间，壳体内的压力保持在约1托或更低。

29. 发明授权

US5717635A High density EEPROM for solid state file 失效
标题翻译：用于固态文件的高密度EEPROM
公开(公告)号：US5717635A
公开(公告)日：1998-02-10
申请号：US703833
申请日：1996-08-27
申请人： Hiroyuki Akatsu
发明人： Hiroyuki Akatsu
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H07L29/68
CPC分类号： H01L27/115
摘要： An EEPROM of NOR-type architecture is formed at high integration density and allows selective programming without selective production of hot electron currents in storage transistor channels. common transistor channel conductors are formed as n-wells running parallel to bit lines having a width of minimum lithographic feature size and separated by shallow trench isolation structures. Connections from bit lines and the n-wells to respective transistors is formed by sub-lithographic metal plugs formed in a self-aligned manner to sidewalls of a layered structure including floating gates and a control gate/word line conductor. Thus a cell size only slightly greater than four times the minimum lithographic feature size can be produced. Provision of a transistor connecting a bit line and an associated n-well unconditionally prevents hot electron current concentration in the gate oxide to increase durability during both programming and flash erasure to either logical state. Programming in combination with erasure to either logical state further doubles memory cell durability.
摘要翻译： NOR型结构的EEPROM以高集成密度形成，并且允许选择性编程，而不选择性地在存储晶体管通道中产生热电子电流。公共晶体管沟道导体形成为平行于具有最小光刻特征尺寸的宽度并由浅沟槽隔离结构分隔的位线的n阱。从位线和n阱到相应晶体管的连接通过以自对准方式形成为包括浮动栅极和控制栅极/字线导体的分层结构的侧壁的亚平版印刷金属插塞形成。因此，可以产生仅略微大于最小光刻特征尺寸的四倍的单元尺寸。提供连接位线和相关联的n阱的晶体管无条件地防止栅极氧化物中的热电子电流集中，以在编程和闪存擦除期间将耐久性提高到逻辑状态。编程结合擦除到逻辑状态进一步增加了存储单元的耐久性。

30. 发明授权

US07615457B2 Method of fabricating self-aligned bipolar transistor having tapered collector 有权
标题翻译：制造具有锥形集电极的自对准双极晶体管的方法
公开(公告)号：US07615457B2
公开(公告)日：2009-11-10
申请号：US12220521
申请日：2008-07-25
申请人： Hiroyuki Akatsu , Rama Divakaruni , Gregory G. Freeman , David R. Greenberg , Marwan H. Khater , William R. Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Gregory G. Freeman , David R. Greenberg , Marwan H. Khater , William R. Tonti
IPC分类号： H01L21/265 , H01L27/102
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/7378
摘要： A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions.
摘要翻译：提供了一种用于制造双极晶体管的方法，该双极晶体管包括具有上部基本上平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁的锥形，即截头锥形收集器基座，上表面具有比下表面小得多的面积。收集器基座可以形成在暴露在通过第一和第二覆盖介质区域延伸的开口内的集电极有源区域的表面上，其中开口限定第一和第二电介质区域的垂直对齐的边缘。

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