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21. 发明申请

US20060213437A1 Plasma enhanced atomic layer deposition system 审中-公开
标题翻译：等离子体增强原子层沉积系统
公开(公告)号：US20060213437A1
公开(公告)日：2006-09-28
申请号：US11090255
申请日：2005-03-28
申请人： Tadahiro Ishizaka , Kaoru Yamamoto
发明人： Tadahiro Ishizaka , Kaoru Yamamoto
IPC分类号： C23C16/00
CPC分类号： C23C16/4409 , C23C16/4404 , C23C16/4412 , C23C16/45542 , C23C16/45544 , C23C16/5096
摘要： A plasma enhanced atomic layer deposition (PEALD) system includes a processing chamber defining an isolated processing space within the processing chamber, and a substrate holder provided within the processing chamber and configured to support a substrate. A first process material supply system is configured to supply a first process material to the processing chamber, a second process material supply system is configured to supply a second process material to the processing chamber and a power source is configured to couple electromagnetic power to the processing chamber. A contaminant shield is positioned along a periphery of the substrate holder and configured to impede external contaminants that permeate the chamber from traveling to a region of the substrate holder, wherein the film is formed on the substrate by alternatingly introducing the first process material and the second process material.
摘要翻译：等离子体增强原子层沉积（PEALD）系统包括限定处理室内的隔离处理空间的处理室和设置在处理室内并被配置为支撑衬底的衬底保持器。第一处理材料供应系统被配置为将第一处理材料供应到处理室，第二处理材料供应系统被配置为将第二处理材料供应到处理室，并且电源被配置为将电磁功率耦合到处理房间。污染物屏蔽沿着衬底保持器的周边设置，并且构造成阻止渗透室的外部污染物移动到衬底保持器的区域，其中通过交替地引入第一工艺材料和第二工艺材料而在衬底上形成膜工艺材料。

22. 发明申请

US20060185597A1 Film precursor evaporation system and method of using 审中-公开
标题翻译：膜前驱体蒸发系统及其使用方法
公开(公告)号：US20060185597A1
公开(公告)日：2006-08-24
申请号：US11351539
申请日：2006-02-10
申请人： Kenji Suzuki , Emmanuel Guidotti , Gerrit Leusink , Masamichi Hara , Daisuke Kuroiwa , Tadahiro Ishizaka
发明人： Kenji Suzuki , Emmanuel Guidotti , Gerrit Leusink , Masamichi Hara , Daisuke Kuroiwa , Tadahiro Ishizaka
IPC分类号： C23C16/00
CPC分类号： C23C16/4481
摘要： A high conductance, multi-tray film precursor evaporation system coupled with a high conductance vapor delivery system is described for increasing deposition rate by increasing exposed surface area of film precursor. The multi-tray film precursor evaporation system includes one or more trays. Each tray is configured to support and retain film precursor in, for example, solid powder form or solid tablet form. Additionally, each tray is configured to provide for a high conductance flow of carrier gas over the film precursor while the film precursor is heated. For example, the carrier gas flows inward over the film precursor, and vertically upward through a flow channel within the stackable trays and through an outlet in the solid precursor evaporation system.
摘要翻译：描述了与高电导蒸气传输系统耦合的高电导多托盘膜前体蒸发系统，以通过增加膜前体的暴露表面积来增加沉积速率。多托盘膜前体蒸发系统包括一个或多个托盘。每个托盘被构造成支撑和保持例如固体粉末形式或固体片剂形式的膜前体。此外，每个托盘构造成在膜前体被加热的同时提供载气在膜前体上的高电导流。例如，载体气体向内流过膜前体，并且垂直向上流过可堆放托盘内的流动通道并通过固体前驱物蒸发系统中的出口。

23. 发明申请

US20050272247A1 Substrate processing method and fabrication process of a semiconductor device 有权
标题翻译：半导体器件的基板处理方法和制造工艺
公开(公告)号：US20050272247A1
公开(公告)日：2005-12-08
申请号：US11142457
申请日：2005-06-02
申请人： Taro Ikeda , Tadahiro Ishizaka , Masamichi Hara
发明人： Taro Ikeda , Tadahiro Ishizaka , Masamichi Hara
IPC分类号： H01L21/768 , H01L21/285 , H01L21/4763 , H01L23/522
CPC分类号： H01L21/76843 , H01L21/28556 , H01L21/28562 , H01L21/76807 , H01L21/76814
摘要： A method of fabricating a semiconductor device includes the steps of forming a via-hole in an interlayer insulation film such that a metal interconnection pattern formed underneath the interlayer insulation film is exposed at a bottom of the via-hole, forming a conductive barrier film on the interlayer insulation film so as to cover a sidewall surface of the via-hole and the exposed metal interconnection pattern in conformity with a shape of the via-hole. and forming a metal film on the conductive barrier film, wherein there is provided a preprocessing step, after the step of forming the via-hole but before the step of forming the conductive barrier film, of processing the interlayer insulation film including the sidewall surface of the via-hole and a bottom surface of the via-hole, with plasma containing hydrogen having energy not causing sputtering of the metal interconnection pattern.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在层间绝缘膜中形成通孔，使得形成在层间绝缘膜下方的金属互连图案在通孔的底部露出，形成导电阻挡膜层间绝缘膜，以覆盖通孔的侧壁表面和暴露的金属互连图案，与通孔的形状一致。在所述导电阻挡膜上形成金属膜，其中，在形成所述导通阻挡膜的步骤之后，在形成所述通孔的步骤之后，提供预处理步骤，处理包括所述侧壁表面的层间绝缘膜通孔和通孔的底表面，其中含有氢的等离子体具有不引起金属互连图案的溅射的能量。

24. 发明授权

US08999841B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US08999841B2
公开(公告)日：2015-04-07
申请号：US13566515
申请日：2012-08-03
申请人： Tadahiro Ishizaka , Atsushi Gomi , Kenzi Suzuki , Tatsuo Hatano , Yasushi Mizusawa
发明人： Tadahiro Ishizaka , Atsushi Gomi , Kenzi Suzuki , Tatsuo Hatano , Yasushi Mizusawa
IPC分类号： H01L21/44 , H01L21/768 , H01L21/02 , H01L21/3105 , H01L21/67 , C23C14/02 , C23C14/04 , C23C16/02 , C23C16/04 , H01L21/285
CPC分类号： H01L21/76841 , C23C14/02 , C23C14/046 , C23C16/02 , C23C16/045 , H01L21/02063 , H01L21/02126 , H01L21/28556 , H01L21/3105 , H01L21/67207 , H01L21/76814 , H01L21/76826 , H01L21/76843
摘要： A semiconductor device manufacturing method includes: modifying a surface of a burying recess, of which surface is hydrophobic and which is formed in a dielectric film, to a hydrophilic state by supplying a plasma containing H ions and H radicals or a plasma containing NHx (x being 1, 2 or 3) ions and NHx radicals to the dielectric film formed on a substrate and containing silicon, carbon, hydrogen and oxygen, a bottom portion of the burying recess being exposed with a lower conductive layer; and directly forming an adhesion film formed of a Ru film on the hydrophilic surface of the recess. The method further includes burying copper forming a conductive path in the recess.
摘要翻译：半导体器件制造方法包括：通过供给含有H离子和H基团的等离子体或包含NH x（x）的等离子体，将其表面是疏水性的并且形成在电介质膜中的掩埋凹槽的表面改性为亲水状态是1,2或3）离子和NH x自由基，形成在衬底上并含有硅，碳，氢和氧的电介质膜，埋入凹部的底部用下导电层暴露; 并且在凹部的亲水性表面上直接形成由Ru膜形成的粘合膜。该方法还包括在凹槽中形成导电路径的铜。

25. 发明授权

US08242019B2 Selective deposition of metal-containing cap layers for semiconductor devices 有权
标题翻译：用于半导体器件的含金属盖层的选择性沉积
公开(公告)号：US08242019B2
公开(公告)日：2012-08-14
申请号：US12414917
申请日：2009-03-31
申请人： Tadahiro Ishizaka , Shigeru Mizuno , Satohiko Hoshino , Hiroyuki Nagai , Yuki Chiba , Frank M. Cerio, Jr.
发明人： Tadahiro Ishizaka , Shigeru Mizuno , Satohiko Hoshino , Hiroyuki Nagai , Yuki Chiba , Frank M. Cerio, Jr.
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/302
CPC分类号： H01L21/76849 , H01L21/02063 , H01L21/02074 , H01L21/3105 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76846 , H01L21/76856 , H01L21/76859 , H01L21/76883
摘要： A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing metal surfaces and dielectric layer surfaces, and modifying the dielectric layer surfaces by exposure to a reactant gas containing a hydrophobic functional group, where the modifying substitutes a hydrophilic functional group in the dielectric layer surfaces with a hydrophobic functional group. The method further includes depositing metal-containing cap layers selectively on the metal surfaces by exposing the modified dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor.
摘要翻译：一种用于将含金属盖层整合到半导体器件的铜（Cu）金属化中的方法。在一个实施例中，该方法包括提供含有金属表面和电介质层表面的图案化衬底，以及通过暴露于含有疏水官能团的反应气体来修饰电介质层表面，其中修饰取代介电层表面中的亲水性官能团具有疏水官能团。该方法还包括通过将改性的介电层表面和金属表面暴露于含有金属的前体蒸气的沉积气体中，将金属含有的盖层选择性地沉积在金属表面上。

26. 发明授权

US08026168B2 Semiconductor device containing an aluminum tantalum carbonitride barrier film and method of forming 有权
标题翻译：含有氮化钽碳氮化物阻挡膜的半导体器件及其形成方法
公开(公告)号：US08026168B2
公开(公告)日：2011-09-27
申请号：US11839410
申请日：2007-08-15
申请人： Tadahiro Ishizaka , Shigeru Mizuno
发明人： Tadahiro Ishizaka , Shigeru Mizuno
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , C23C16/36 , H01L21/28562 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76864 , H01L21/76873 , H01L2221/1089 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The method includes providing a substrate containing a dielectric layer having a recessed feature and forming a aluminum tantalum carbonitride barrier film over a surface of the recessed feature. The aluminum tantalum carbonitride barrier film is formed by depositing a plurality of tantalum carbonitride films, and depositing aluminum between each of the plurality of tantalum carbonitride films. One embodiment further comprises depositing a Ru film on the aluminum tantalum carbonitride barrier film, depositing a Cu seed layer on the Ru film, and filling the recessed feature with bulk Cu. A semiconductor device containing an aluminum tantalum carbonitride barrier film is described.
摘要翻译：该方法包括提供含有具有凹陷特征的介电层的基板，并在凹陷特征的表面上形成铝钽碳氮化物阻挡膜。通过沉积多个碳氮化钽膜并在多个碳氮化钽薄膜中的每一个之间沉积铝来形成氮化钽碳氮化物阻挡膜。一个实施例还包括在氮化钽碳氮化物阻挡膜上沉积Ru膜，在Ru膜上沉积Cu籽晶层，并用体积Cu填充凹陷特征。描述了包含氮化钽碳氮化物阻挡膜的半导体器件。

27. 发明授权

US07727912B2 Method of light enhanced atomic layer deposition 有权
标题翻译：光增强原子层沉积的方法
公开(公告)号：US07727912B2
公开(公告)日：2010-06-01
申请号：US11378270
申请日：2006-03-20
申请人： Tadahiro Ishizaka , Frank M. Cerio, Jr. , Jacques Faguet
发明人： Tadahiro Ishizaka , Frank M. Cerio, Jr. , Jacques Faguet
IPC分类号： H01L21/469
CPC分类号： H01L21/76843 , C23C16/32 , C23C16/36 , C23C16/45536 , C23C16/482 , H01L21/28562
摘要： A method light enhanced atomic layer deposition for forming a film on a substrate. The method includes disposing the substrate in a process chamber of a light enhanced atomic layer deposition (LEALD) system configured to perform a LEALD process; and depositing a film on the substrate using the LEALD process, where the depositing includes (a) exposing the substrate to a first process material, (b) exposing the substrate to a second process material containing a reducing agent and irradiating the substrate with a first light radiation having either no or at least partial temporal overlap with the exposing of the substrate to the second process material, (c) repeating steps (a) and (b) until the desired film has been deposited. According to one embodiment of the invention, the deposited film can be a TaCN film or a TaC film.
摘要翻译：一种用于在基板上形成薄膜的光增强原子层沉积。该方法包括将衬底设置在被配置为执行LEALD处理的光增强原子层沉积（LEALD）系统的处理室中; 以及使用LEALD工艺在衬底上沉积膜，其中沉积包括（a）将衬底暴露于第一工艺材料，（b）将衬底暴露于含有还原剂的第二工艺材料上，并用第一具有或不至少部分时间重叠的光辐射与基板暴露于第二工艺材料，（c）重复步骤（a）和（b），直到所需的膜沉积为止。根据本发明的一个实施例，沉积膜可以是TaCN膜或TaC膜。

28. 发明授权

US07718527B2 Method for forming cobalt tungsten cap layers 有权
标题翻译：形成钴钨帽层的方法
公开(公告)号：US07718527B2
公开(公告)日：2010-05-18
申请号：US12242914
申请日：2008-10-01
申请人： Tadahiro Ishizaka , Shigeru Mizuno , Miho Jomen
发明人： Tadahiro Ishizaka , Shigeru Mizuno , Miho Jomen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76856 , H01L21/02063 , H01L21/02074 , H01L21/76814 , H01L21/76846 , H01L21/76849 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method is provided for integrating cobalt tungsten cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt tungsten cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k regions, and forming a cobalt tungsten cap layer on the Cu paths.
摘要翻译：提供了一种用于将钴钨帽层集成到半导体器件制造中以改善铜（Cu）金属中的电迁移和应力迁移的方法。一个实施例包括提供包含形成在低k材料中的凹陷特征的图案化基底和位于特征底部的第一金属化层，在第一金属化层上形成钴钨帽层，在凹陷特征中沉积阻挡层包括在低k电介质材料和第一钴金属帽层上，并用Cu金属填充凹陷特征。另一实施例包括提供具有Cu路径和低k区域的基本上平坦的表面的图案化衬底，以及在Cu路径上形成钴钨帽层。

29. 发明申请

US20100081276A1 METHOD FOR FORMING COBALT TUNGSTEN CAP LAYERS 有权
标题翻译：形成钴铁矿石层的方法
公开(公告)号：US20100081276A1
公开(公告)日：2010-04-01
申请号：US12242914
申请日：2008-10-01
申请人： Tadahiro Ishizaka , Shigeru Mizuno , Miho Jomen
发明人： Tadahiro Ishizaka , Shigeru Mizuno , Miho Jomen
IPC分类号： H01L21/768
CPC分类号： H01L21/76856 , H01L21/02063 , H01L21/02074 , H01L21/76814 , H01L21/76846 , H01L21/76849 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method is provided for integrating cobalt tungsten cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt tungsten cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k regions, and forming a cobalt tungsten cap layer on the Cu paths.
摘要翻译：提供了一种用于将钴钨帽层集成到半导体器件制造中以改善铜（Cu）金属中的电迁移和应力迁移的方法。一个实施例包括提供包含形成在低k材料中的凹陷特征的图案化基底和位于特征底部的第一金属化层，在第一金属化层上形成钴钨帽层，在凹陷特征中沉积阻挡层包括在低k电介质材料和第一钴金属帽层上，并用Cu金属填充凹陷特征。另一实施例包括提供具有Cu路径和低k区域的基本上平坦的表面的图案化衬底，以及在Cu路径上形成钴钨帽层。

30. 发明申请

US20080237860A1 INTERCONNECT STRUCTURES CONTAINING A RUTHENIUM BARRIER FILM AND METHOD OF FORMING 审中-公开
标题翻译：包含椽子膜的互连结构和形成方法
公开(公告)号：US20080237860A1
公开(公告)日：2008-10-02
申请号：US11691897
申请日：2007-03-27
申请人： Tadahiro Ishizaka , Atsushi Gomi
发明人： Tadahiro Ishizaka , Atsushi Gomi
IPC分类号： H01L23/52 , H01L21/3205
CPC分类号： H01L21/76876 , H01L21/28556 , H01L21/32051 , H01L21/76843 , H01L21/76844 , H01L21/76864 , H01L21/76873 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention provide a method for integrating a Ru barrier film with good barrier properties into Cu metallization. The method includes exposing a substrate to a Ta-, Ti-, or W-containing precursor at a substrate temperature below the thermal decomposition temperature of the Ta-, Ti-, or W-containing precursor on the substrate to form a chemisorbed seed layer of partially decomposed Ta-, Ti-, or W-containing precursor on the substrate. The method further includes depositing a Ru barrier film on the chemisorbed seed layer, and forming bulk Cu metal on the Ru barrier film. According to additional embodiments, an interconnect structure and method of forming are provided.
摘要翻译：本发明的实施方案提供了一种将具有良好阻隔性能的Ru阻挡膜整合到Cu金属化中的方法。该方法包括在低于衬底上的含Ta，Ti或W的前体的热分解温度的衬底温度下将衬底暴露于含Ta，Ti或W的前体，以形成化学吸附的种子层在基底上部分分解的Ta，Ti或W的前体。该方法还包括在化学吸附的种子层上沉积Ru阻挡膜，并在Ru阻挡膜上形成块状Cu金属。根据另外的实施例，提供了互连结构和形成方法。

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