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1. 发明授权

US08242019B2 Selective deposition of metal-containing cap layers for semiconductor devices 有权
标题翻译：用于半导体器件的含金属盖层的选择性沉积
公开(公告)号：US08242019B2
公开(公告)日：2012-08-14
申请号：US12414917
申请日：2009-03-31
申请人： Tadahiro Ishizaka , Shigeru Mizuno , Satohiko Hoshino , Hiroyuki Nagai , Yuki Chiba , Frank M. Cerio, Jr.
发明人： Tadahiro Ishizaka , Shigeru Mizuno , Satohiko Hoshino , Hiroyuki Nagai , Yuki Chiba , Frank M. Cerio, Jr.
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/302
CPC分类号： H01L21/76849 , H01L21/02063 , H01L21/02074 , H01L21/3105 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76846 , H01L21/76856 , H01L21/76859 , H01L21/76883
摘要： A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing metal surfaces and dielectric layer surfaces, and modifying the dielectric layer surfaces by exposure to a reactant gas containing a hydrophobic functional group, where the modifying substitutes a hydrophilic functional group in the dielectric layer surfaces with a hydrophobic functional group. The method further includes depositing metal-containing cap layers selectively on the metal surfaces by exposing the modified dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor.
摘要翻译：一种用于将含金属盖层整合到半导体器件的铜（Cu）金属化中的方法。在一个实施例中，该方法包括提供含有金属表面和电介质层表面的图案化衬底，以及通过暴露于含有疏水官能团的反应气体来修饰电介质层表面，其中修饰取代介电层表面中的亲水性官能团具有疏水官能团。该方法还包括通过将改性的介电层表面和金属表面暴露于含有金属的前体蒸气的沉积气体中，将金属含有的盖层选择性地沉积在金属表面上。

2. 发明申请

US20100248473A1 SELECTIVE DEPOSITION OF METAL-CONTAINING CAP LAYERS FOR SEMICONDUCTOR DEVICES 有权
标题翻译：用于半导体器件的金属包层的选择性沉积
公开(公告)号：US20100248473A1
公开(公告)日：2010-09-30
申请号：US12414917
申请日：2009-03-31
申请人： Tadahiro Ishizaka , Shigeru Mizuno , Satohiko Hoshino , Hiroyuki Nagai , Yuki Chiba , Frank M. Cerio, JR.
发明人： Tadahiro Ishizaka , Shigeru Mizuno , Satohiko Hoshino , Hiroyuki Nagai , Yuki Chiba , Frank M. Cerio, JR.
IPC分类号： H01L21/768 , H01L21/3205
CPC分类号： H01L21/76849 , H01L21/02063 , H01L21/02074 , H01L21/3105 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76846 , H01L21/76856 , H01L21/76859 , H01L21/76883
摘要： A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing metal surfaces and dielectric layer surfaces, and modifying the dielectric layer surfaces by exposure to a reactant gas containing a hydrophobic functional group, where the modifying substitutes a hydrophilic functional group in the dielectric layer surfaces with a hydrophobic functional group. The method further includes depositing metal-containing cap layers selectively on the metal surfaces by exposing the modified dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor.
摘要翻译：一种用于将含金属盖层整合到半导体器件的铜（Cu）金属化中的方法。在一个实施例中，该方法包括提供含有金属表面和电介质层表面的图案化衬底，以及通过暴露于含有疏水官能团的反应气体来修饰电介质层表面，其中修饰取代介电层表面中的亲水性官能团具有疏水官能团。该方法还包括通过将改性的介电层表面和金属表面暴露于含有金属的前体蒸气的沉积气体中，将金属含有的盖层选择性地沉积在金属表面上。

3. 发明授权

US08012880B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08012880B2
公开(公告)日：2011-09-06
申请号：US12216155
申请日：2008-06-30
申请人： Yuki Chiba
发明人： Yuki Chiba
IPC分类号： H01L21/302 , B44C1/22
CPC分类号： H01L21/31138 , H01J37/3244 , H01J37/32449 , H01L21/02063 , H01L21/3105 , H01L21/31116 , H01L21/31144 , H01L21/76814 , H01L21/76826
摘要： The present invention relates to a method of manufacturing a semiconductor device using a substrate including an organic low dielectric constant film containing a silicon, a carbon, an oxygen, and a hydrogen, with a resist pattern being formed on an upper layer side of the low dielectric constant film. The method comprising: an etching step in which the low dielectric constant film is etched by a plasma; an ashing step following to the etching step, in which the resist pattern is ashed by a plasma that is rich in oxygen radicals in such a manner that a relative dielectric constant of the low dielectric constant film can become 5.2 or more; and a recovering step following to the ashing step, in which an organic gas is supplied to the low dielectric constant film so as to recovery a damage of the low dielectric constant film caused by the plasma.
摘要翻译：本发明涉及一种使用包含含有硅，碳，氧和氢的有机低介电常数膜的基板的半导体器件的制造方法，其中抗蚀剂图案形成在低层的上层侧介电常数膜。该方法包括：蚀刻步骤，其中通过等离子体蚀刻低介电常数膜; 在蚀刻步骤之后的灰化步骤，其中抗蚀剂图案以能够使低介电常数膜的相对介电常数达到5.2以上的方式被富含氧自由基的等离子体灰化; 以及在灰化步骤之后的恢复步骤，其中向低介电常数膜提供有机气体，以便恢复由等离子体引起的低介电常数膜的损坏。

4. 发明申请

US20080314520A1 Method and apparatus for manufacturing semiconductor device, and storage medium 有权
标题翻译：用于制造半导体器件的方法和装置以及存储介质
公开(公告)号：US20080314520A1
公开(公告)日：2008-12-25
申请号：US12155746
申请日：2008-06-09
申请人： Yuki Chiba , Shigeru Tahara
发明人： Yuki Chiba , Shigeru Tahara
IPC分类号： H01L21/306 , H01L21/461
CPC分类号： H01L21/31138 , H01J37/3244 , H01L21/02063 , H01L21/3105 , H01L21/31144 , H01L21/76807 , H01L21/76816 , H01L21/76826
摘要： The present invention provides a method for manufacturing a semiconductor device. In the method, a connection hole such as a via hole is formed in an interlayer insulating film by plasma etching with high etching uniformity regardless of the array density of connection holes. In the method, an upper layer film having a mask pattern is formed on the interlayer insulating film present on a substrate. A gas required for dehydration is then supplied to the substrate under the condition that an upper surface of the interlayer insulating film is exposed in order to remove moisture from the interlayer insulating film. A portion of the interlayer insulating film is etched to form a connection hole in which an electrical connection portion is to be embedded.
摘要翻译：本发明提供一种制造半导体器件的方法。在该方法中，不管连接孔的阵列密度如何，通过等离子体蚀刻以高蚀刻均匀性在层间绝缘膜中形成诸如通孔的连接孔。在该方法中，在存在于基板上的层间绝缘膜上形成具有掩模图案的上层膜。然后在层间绝缘膜的上表面露出的条件下向基板供给脱水所需的气体，以从层间绝缘膜去除水分。蚀刻层间绝缘膜的一部分，形成嵌入电连接部的连接孔。

5. 发明申请

US20130096982A1 INTEREST LEVEL ESTIMATION APPARATUS, INTEREST LEVEL ESTIMATION METHOD, AND COMPUTER-READABLE RECORDING MEDIUM 审中-公开
标题翻译：利益水平估算装置，利益水平估算方法和计算机可读记录介质
公开(公告)号：US20130096982A1
公开(公告)日：2013-04-18
申请号：US13704675
申请日：2011-06-13
申请人： Yoji Miyazaki , Yuki Chiba
发明人： Yoji Miyazaki , Yuki Chiba
IPC分类号： G06Q30/02
CPC分类号： G06Q30/0201 , G06Q30/0242
摘要： An interest level estimation apparatus 10 is provided with an interest level estimation unit 11 that, using at least one of environmental information specifying an environment of every section within a specific space 100 and position information specifying a position of every section, and visitor number information specifying, for every section, the number of people visiting the section, estimates, for every section, a level of interest indicating a level to which people visiting the section are interested in the section.
摘要翻译：感兴趣度估计装置10设置有兴趣度估计单元11，其使用指定特定空间100内的每个区段的环境的环境信息和指定每个区段的位置的位置信息和指定的位置信息中的至少一个对于每个部分，访问该部分的人数估计，对于每个部分，表示访问该部分的人对该部分感兴趣的级别的兴趣水平。

6. 发明申请

US20090011605A1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090011605A1
公开(公告)日：2009-01-08
申请号：US12216154
申请日：2008-06-30
申请人： Yuki Chiba , Eiichi Nishimura , Ryuichi Asako
发明人： Yuki Chiba , Eiichi Nishimura , Ryuichi Asako
IPC分类号： H01L21/3065
CPC分类号： H01L21/02063 , H01J37/32522 , H01J2237/2001 , H01L21/3105 , H01L21/31116 , H01L21/31138 , H01L21/76807 , H01L21/76814 , H01L21/76826
摘要： The present invention is an apparatus for manufacturing a semiconductor device comprising: a process vessel including a stage on which a substrate is placed, the substrate having a low dielectric constant film with a resist pattern being formed in an upper layer of the low dielectric constant film; an etching-gas supply unit that supplies an etching gas into the process vessel so as to etch the low dielectric constant film; an ashing-gas unit means that supplies an ashing gas into the process vessel so as to ash the resist pattern formed in the upper layer of the low dielectric constant film after the low dielectric constant film has been subjected to an etching process; a plasma generating means that generates a plasma by supplying an energy to the etching gas and the ashing gas in the process vessel; a unit that supplies a dipivaloylmethane gas into the process vessel, after the low dielectric constant film has been subjected to an ashing process, in order to recover a damage layer of the low dielectric constant film which has been damaged by the plasma; and a heating unit that enables the dipivaloylmethane gas to come into contact with a surface of the substrate under a heated condition.
摘要翻译：本发明是一种半导体器件的制造装置，其特征在于，包括：处理容器，其具有载置基板的载物台，所述基板具有低介电常数膜，所述低介电常数膜形成在所述低介电常数膜的上层中 ; 蚀刻气体供给单元，其将蚀刻气体供给到所述处理容器中，以蚀刻所述低介电常数膜; 灰化单元意味着在低介电常数薄膜进行了蚀刻处理之后，将灰化气体供给到处理容器中，以使在低介电常数膜的上层形成的抗蚀剂图案灰化; 等离子体产生装置，其通过向处理容器中的蚀刻气体和灰化气体供应能量来产生等离子体; 在低介电常数薄膜已进行灰化处理之后，向该处理容器中供给二过代甲烷气体的单元，以回收已被等离子体损坏的低介电常数膜的损伤层; 以及加热单元，其使得二辛酰甲烷气体在加热条件下与基材的表面接触。

7. 发明申请

US20080194115A1 PROCESSING METHOD AND STORAGE MEDIUM 有权
标题翻译：处理方法和储存介质
公开(公告)号：US20080194115A1
公开(公告)日：2008-08-14
申请号：US12025359
申请日：2008-02-04
申请人： Kazuhiro KUBOTA , Naotsugu Hoshi , Yuki Chiba , Ryuichi Asako
发明人： Kazuhiro KUBOTA , Naotsugu Hoshi , Yuki Chiba , Ryuichi Asako
IPC分类号： H01L21/469
CPC分类号： H01L21/76802 , H01L21/3105 , H01L21/31058 , H01L21/76814 , H01L21/76826 , H01L21/76835
摘要： A processing method includes a gas having a Si—CH3 bond supplied into a processing chamber after a target substrate to be processed is loaded into the processing chamber; and a silylation process performed on the target substrate. The internal pressure of the chamber by the supply of the gas having the Si—CH3 bond and the gas supply time are set to be within ranges where the silylation process can be performed while the internal pressure of the chamber is decreased to reach an eligible pressure level where the wafer can be unloaded after the internal pressure of the chamber is increased up to a preset pressure by the supply of the gas.
摘要翻译：处理方法包括在待处理的目标基板被加载到处理室中之后提供到处理室中的具有Si-CH 3键的气体; 和在靶基质上进行的甲硅烷基化处理。通过供给具有Si-CH 3键的气体和气体供给时间，室的内部压力被设定在能够进行甲硅烷化处理的范围内，同时，室降低到合格的压力水平，其中通过气体的供应将室的内部压力增加到预定压力之后可以卸载晶片。

8. 发明申请

US20050282394A1 Method for manufacturing a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20050282394A1
公开(公告)日：2005-12-22
申请号：US11153539
申请日：2005-06-16
申请人： Yuki Chiba
发明人： Yuki Chiba
IPC分类号： H01L21/033 , H01L21/311 , H01L21/3205
CPC分类号： H01L21/31138 , H01L21/0337 , H01L21/0338 , H01L21/31116 , H01L21/31144
摘要： In a method for manufacturing a semiconductor device, a first high frequency power of a first frequency is applied to a processing gas to generate a plasma of the processing gas, a second high frequency power of a second frequency smaller than the first frequency is applied to a substrate to be processed. Further, a to-be-etched layer disposed under a resist film having a pattern of openings is etched by using the resist film as a mask, the to-be-etched layer being disposed on a surface of the substrate. In addition, dimensions of openings formed in the to-be-etched layer are controlled by varying an applied power of the first high frequency.
摘要翻译：在制造半导体器件的方法中，将第一频率的第一高频功率施加到处理气体以产生处理气体的等离子体，将小于第一频率的第二频率的第二高频功率施加到待加工的基材。此外，通过使用抗蚀剂膜作为掩模蚀刻设置在具有开口图案的抗蚀剂膜下方的被蚀刻层，被蚀刻层设置在基板的表面上。此外，通过改变第一高频的施加功率来控制在待蚀刻层中形成的开口的尺寸。

9. 发明授权

US08484491B2 Power supply apparatus and power supply control method 有权
标题翻译：电源装置及电源控制方式
公开(公告)号：US08484491B2
公开(公告)日：2013-07-09
申请号：US12805097
申请日：2010-07-12
申请人： Hironobu Kageyama , Takashi Sato , Yuki Chiba , Koki Watanabe
发明人： Hironobu Kageyama , Takashi Sato , Yuki Chiba , Koki Watanabe
IPC分类号： G06F1/26
CPC分类号： H02J9/061 , H02J9/005
摘要： A main power supply and a backup power supply have the same set voltage. To prevent electrical power from being supplied from the backup power supply to a load circuit, during a normal operation, a power supply control unit gives a standby instruction to the backup power supply so that the backup power supply is on standby at a voltage lower than that of the main power supply. When an AC power supply is stopped, the backup power supply is operated at the set voltage and the main power supply is stopped.
摘要翻译：主电源和备用电源具有相同的设定电压。为了防止从备用电源向负载电路供电，在正常操作期间，电源控制单元向备用电源发出备用指令，使得备用电源处于低于主电源。当交流电源停止时，备用电源以设定电压运行，主电源停止。

10. 发明授权

US07922865B2 Magnetic field generator for magnetron plasma, and plasma etching apparatus and method comprising the magnetic field generator 有权
标题翻译：用于磁控管等离子体的磁场发生器，以及包括磁场发生器的等离子体蚀刻装置和方法
公开(公告)号：US07922865B2
公开(公告)日：2011-04-12
申请号：US10362879
申请日：2001-08-28
申请人： Koji Miyata , Jun Hirose , Akira Kodashima , Shigeki Tozawa , Kazuhiro Kubota , Yuki Chiba
发明人： Koji Miyata , Jun Hirose , Akira Kodashima , Shigeki Tozawa , Kazuhiro Kubota , Yuki Chiba
IPC分类号： H01L21/306
CPC分类号： H01J37/3266 , H01J37/3408
摘要： In a magnetic field generator for magnetron plasma generation which comprises a dipole-ring magnet with a plurality of columnar anisotropic segment magnets arranged in a ring-like manner, or in an etching apparatus and a method both of which utilize the magnetic field generator, the uniformity of plasma treatment over the entire surface of a wafer (workpiece) is improved by controlling the direction of the magnetic field relative to the working surface of the wafer (workpiece) which is subject to plasma treatment such as etching.
摘要翻译：在用于磁控管等离子体生成的磁场发生器中，其包括具有以环状布置的多个柱状各向异性区段磁体的偶极环磁体，或者在利用磁场发生器的蚀刻装置和方法中，通过控制相对于进行诸如蚀刻等离子体处理的晶片（工件）的工作表面的磁场方向来改善晶片（工件）整个表面上的等离子体处理的均匀性。

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