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21. 发明申请

US20110037141A1 Semiconductor Device and Method of Fabricating the Same 有权
公开(公告)号：US20110037141A1
公开(公告)日：2011-02-17
申请号：US12906652
申请日：2010-10-18
申请人： Jung-Hwan Kim , Hun-Hyeoung Leam , Tae-Hyun Kim , Seok-Woo Nam , Hyun Namkoong , Yong-Seok Kim , Tea-Kwang Yu
发明人： Jung-Hwan Kim , Hun-Hyeoung Leam , Tae-Hyun Kim , Seok-Woo Nam , Hyun Namkoong , Yong-Seok Kim , Tea-Kwang Yu
IPC分类号： H01L29/02
CPC分类号： H01L29/785 , H01L21/28282 , H01L21/308 , H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/1079 , H01L29/42352 , H01L29/66818 , H01L29/66833 , H01L29/7851 , H01L29/7854 , H01L2029/7858
摘要： A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

22. 发明申请

US20080057670A1 Semiconductor Device and Method of Fabricating the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080057670A1
公开(公告)日：2008-03-06
申请号：US11931571
申请日：2007-10-31
申请人： Jung Kim , Hun-Hyeoung Leam , Tae-Hyun kim , Seok-Woo Nam , Hyun Namkoong , Yong-Seok Kim , Tea-Kwang Yu
发明人： Jung Kim , Hun-Hyeoung Leam , Tae-Hyun kim , Seok-Woo Nam , Hyun Namkoong , Yong-Seok Kim , Tea-Kwang Yu
IPC分类号： H01L21/76
CPC分类号： H01L29/785 , H01L21/28282 , H01L21/308 , H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/1079 , H01L29/42352 , H01L29/66818 , H01L29/66833 , H01L29/7851 , H01L29/7854 , H01L2029/7858
摘要： A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
摘要翻译：半导体器件包括限定形成在半导体衬底中的有源区的隔离层。在隔离层上执行第一凹陷处理以暴露活性区域的边缘部分。执行第一舍入处理以围绕活动区域的边缘部分。在隔离层上进行第二凹陷处理。执行第二舍入处理以围绕活动区域的边缘部分。

23. 发明授权

US07119392B2 Storage electrode of a semiconductor device and method of forming the same 有权
标题翻译：半导体器件的存储电极及其形成方法
公开(公告)号：US07119392B2
公开(公告)日：2006-10-10
申请号：US11086318
申请日：2005-03-23
申请人： Kyoung-Seok Kim , Ki-Hyun Hwang , Hyo-Jung Kim , Hyeon-Deok Lee , Seok-Woo Nam
发明人： Kyoung-Seok Kim , Ki-Hyun Hwang , Hyo-Jung Kim , Hyeon-Deok Lee , Seok-Woo Nam
IPC分类号： H01L21/8242
CPC分类号： H01L28/84 , H01L27/10814 , H01L27/10817 , H01L27/10852 , H01L28/90
摘要： In a storage electrode of a semiconductor device, and a method of forming the same, the storage electrode includes an outer cylinder including a first outer cylindrical portion having a first outer diameter, and a second outer cylindrical portion that is formed on the first outer cylindrical portion and having a second outer diameter, which is less than the first outer diameter, the first and second outer cylindrical portions having substantially equal inner diameters, and an inner cylinder formed on inner surfaces of the outer cylinder.
摘要翻译：在半导体器件的存储电极及其形成方法中，所述存储电极包括：外筒，所述外筒包括具有第一外径的第一外筒部和形成在所述第一外筒上的第二外筒部; 部分具有小于第一外径的第二外径，第一和第二外筒部具有基本相等的内径，以及形成在外筒内表面上的内筒。

24. 发明授权

US6133109A Method for manufacturing a DRAM cell capacitor 失效
标题翻译： DRAM单元电容器的制造方法
公开(公告)号：US6133109A
公开(公告)日：2000-10-17
申请号：US221605
申请日：1998-12-29
申请人： Seok-Woo Nam
发明人： Seok-Woo Nam
IPC分类号： H01L21/02 , H01L21/20 , H01L21/8242
CPC分类号： H01L28/84 , H01L21/2026 , H01L27/10852
摘要： A method of manufacturing a DRAM cell capacitor is provided wherein a capacitor storage electrode is covered with an HSG (Hemi-Spherical Grain) silicon layer to increase capacitance, but the HSG silicon layer is not formed on the top edge of the capacitor storage electrode.
摘要翻译：提供一种制造DRAM单元电容器的方法，其中电容器存储电极被HSG（半球形晶粒）硅层覆盖以增加电容，但是在电容器存储电极的顶部边缘上不形成HSG硅层。

25. 发明申请

US20110284968A1 SEMICONDUCTOR DEVICES INCLUDING GATE STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：包括门结构的半导体器件及其制造方法
公开(公告)号：US20110284968A1
公开(公告)日：2011-11-24
申请号：US13097409
申请日：2011-04-29
申请人： Kwang-Wook Lee , Jae-Jik Baek , In-Seak Hwang , Seok-Woo Nam
发明人： Kwang-Wook Lee , Jae-Jik Baek , In-Seak Hwang , Seok-Woo Nam
IPC分类号： H01L29/772
CPC分类号： H01L29/66545 , H01L29/165 , H01L29/66621 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device includes a semiconductor substrate having a top surface and a recessed portion including at least two oblique side surfaces and a first bottom surface therebetween, a gate insulating layer formed on the recessed portion, a gate electrode formed on the gate insulating layer, a channel region below the gate electrode in the semiconductor substrate, and gate spacers formed on side surfaces of the gate electrode, wherein both the bottom surface and the side surfaces of the recessed portion include flat surfaces. A method of manufacturing a semiconductor device comprising the steps of forming a recess portion including at least two oblique side surfaces and a bottom surface therebetween in a semiconductor substrate, forming a gate insulating layer formed on the recessed portion, forming a gate electrode formed on the gate insulating layer, forming a channel region below the gate electrode in the semiconductor substrate, and forming gate spacers formed on side surfaces of the gate electrode.
摘要翻译：半导体器件包括具有顶表面和凹部的半导体衬底，该凹部包括至少两个倾斜侧表面和其间的第一底表面，形成在凹陷部分上的栅极绝缘层，形成在栅极绝缘层上的栅电极，半导体衬底中的栅电极下方的沟道区域和形成在栅电极的侧表面上的栅极间隔，其中凹部的底表面和侧表面均包括平坦表面。一种制造半导体器件的方法，包括以下步骤：在半导体衬底中形成包括至少两个倾斜侧表面和底表面的凹部，形成在所述凹部上形成的栅极绝缘层，形成在所述凹部上形成的栅电极栅极绝缘层，在半导体衬底中的栅电极下方形成沟道区，以及形成在栅电极的侧表面上的栅极间隔。

26. 发明授权

US07928495B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07928495B2
公开(公告)日：2011-04-19
申请号：US12906652
申请日：2010-10-18
申请人： Jung-Hwan Kim , Hun-Hyeoung Leam , Tae-Hyun Kim , Seok-Woo Nam , Hyun Namkoong , Yong-Seok Kim , Tea-Kwang Yu
发明人： Jung-Hwan Kim , Hun-Hyeoung Leam , Tae-Hyun Kim , Seok-Woo Nam , Hyun Namkoong , Yong-Seok Kim , Tea-Kwang Yu
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/28282 , H01L21/308 , H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/1079 , H01L29/42352 , H01L29/66818 , H01L29/66833 , H01L29/7851 , H01L29/7854 , H01L2029/7858
摘要： A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
摘要翻译：半导体器件包括限定形成在半导体衬底中的有源区的隔离层。在隔离层上执行第一凹陷处理以暴露活性区域的边缘部分。执行第一舍入处理以围绕活动区域的边缘部分。在隔离层上进行第二凹陷处理。执行第二舍入处理以围绕活动区域的边缘部分。

27. 发明授权

US07741222B2 Etch stop structure and method of manufacture, and semiconductor device and method of manufacture 有权
标题翻译：蚀刻止蚀结构及其制造方法，半导体器件及其制造方法
公开(公告)号：US07741222B2
公开(公告)日：2010-06-22
申请号：US11102849
申请日：2005-04-11
申请人： Young-Sub You , Jae-Young Park , Won-Shik Shin , Hyeon-Deok Lee , Ki-Vin Im , Seok-Woo Nam , Hun-Young Lim , Won-Jun Jang , Yong-Woo Hyung
发明人： Young-Sub You , Jae-Young Park , Won-Shik Shin , Hyeon-Deok Lee , Ki-Vin Im , Seok-Woo Nam , Hun-Young Lim , Won-Jun Jang , Yong-Woo Hyung
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L28/91
摘要： An etch stop layer is formed over a first structure by depositing a metal oxide material over the first structure and annealing the deposited metal oxide material. A second structure is formed over the etch stop layer, and a formation is etched through the second structure using the etch stop layer as an etch stop.
摘要翻译：通过在第一结构上沉积金属氧化物材料并退火沉积的金属氧化物材料，在第一结构上形成蚀刻停止层。在蚀刻停止层上形成第二结构，并且使用蚀刻停止层作为蚀刻停止层，通过第二结构蚀刻形成。

28. 发明申请

US20070001209A1 Method of forming a storage electrode of a semiconductor device 有权
标题翻译：形成半导体器件的存储电极的方法
公开(公告)号：US20070001209A1
公开(公告)日：2007-01-04
申请号：US11516707
申请日：2006-09-07
申请人： Kyoung-Seok Kim , Ki-Hyun Hwang , Hyo-Jung Kim , Hyeon-Deok Lee , Seok-Woo Nam
发明人： Kyoung-Seok Kim , Ki-Hyun Hwang , Hyo-Jung Kim , Hyeon-Deok Lee , Seok-Woo Nam
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L28/84 , H01L27/10814 , H01L27/10817 , H01L27/10852 , H01L28/90
摘要： In a storage electrode of a semiconductor device, and a method of forming the same, the storage electrode includes an outer cylinder including a first outer cylindrical portion having a first outer diameter, and a second outer cylindrical portion that is formed on the first outer cylindrical portion and having a second outer diameter, which is less than the first outer diameter, the first and second outer cylindrical portions having substantially equal inner diameters, and an inner cylinder formed on inner surfaces of the outer cylinder.
摘要翻译：在半导体器件的存储电极及其形成方法中，所述存储电极包括：外筒，所述外筒包括具有第一外径的第一外筒部和形成在所述第一外筒上的第二外筒部; 部分具有小于第一外径的第二外径，第一和第二外筒部具有基本相等的内径，以及形成在外筒内表面上的内筒。

29. 发明申请

US20060267019A1 Capacitor and methods of manufacturing the same 审中-公开
标题翻译：电容器和制造方法相同
公开(公告)号：US20060267019A1
公开(公告)日：2006-11-30
申请号：US11434921
申请日：2006-05-17
申请人： Kyoung-Seok Kim , Yong-Woo Hyung , Jae-Young Park , Hyeon-Deok Lee , Ki-Vin Im , Wook-Yeol Yi , Ko-Eun Lee , Young-Jin Kim , Seok-Woo Nam
发明人： Kyoung-Seok Kim , Yong-Woo Hyung , Jae-Young Park , Hyeon-Deok Lee , Ki-Vin Im , Wook-Yeol Yi , Ko-Eun Lee , Young-Jin Kim , Seok-Woo Nam
IPC分类号： H01L27/108
CPC分类号： H01L28/75 , H01L27/10814 , H01L27/10852 , H01L28/90
摘要： In a capacitor having a semiconductor-insulator-metal (SIM) structure, an upper electrode may be formed into a multilayer structure including a polycrystalline semiconductor Group IV material. A dielectric layer may include a metal oxide, and a lower electrode may include a metal-based material. Therefore, a capacitor may have a sufficiently small equivalent oxide thickness (EOT) and/or may have improved current leakage characteristics.
摘要翻译：在具有半导体 - 绝缘体 - 金属（SIM）结构的电容器中，上电极可以形成为包括多晶半导体IV族材料的多层结构。电介质层可以包括金属氧化物，下电极可以包括金属基材料。因此，电容器可以具有足够小的等效氧化物厚度（EOT）和/或可以具有改善的电流泄漏特性。

30. 发明申请

US20060160337A1 Method of manufacturing a hemisperical grain silicon layer and method of manufacturing a semiconductor device using the same 审中-公开
标题翻译：制造半晶粒硅层的方法及使用其制造半导体器件的方法
公开(公告)号：US20060160337A1
公开(公告)日：2006-07-20
申请号：US11323999
申请日：2005-12-29
申请人： Young-Jin Kim , Hyeon-Deok Lee , Seok-Woo Nam , Yong-Jae Lee , Hyun-Seok Lim , Wan-Goo Hwang , Jin-Il Lee , Jung-Hwan Oh
发明人： Young-Jin Kim , Hyeon-Deok Lee , Seok-Woo Nam , Yong-Jae Lee , Hyun-Seok Lim , Wan-Goo Hwang , Jin-Il Lee , Jung-Hwan Oh
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L28/84 , H01L27/10817 , H01L27/10852 , H01L28/91
摘要： In a method of manufacturing a capacitor including a hemispherical grain (HSG) silicon layer, after forming a storage electrode electrically coupled to a contact region of a substrate, the HSG silicon layer is formed on the storage electrode by providing a first gas including silicon and a second gas onto a surface of the storage electrode with a volume ratio of about 1.0:0.1 to about 1.0:5.0. A dielectric layer and a plate electrode are sequentially formed on the HSG silicon layer. A grain size of the HSG silicon layer may be easily adjusted and abnormal growths of the HSG at a lower portion of the storage electrode may be suppressed. Therefore, the HSG silicon layer may be uniformly formed on the storage electrode, and a structural stability of the storage electrode may be improved to prevent electrical defects of the capacitor.
摘要翻译：在制造包括半球形晶粒（HSG）硅层的电容器的方法中，在形成与基板的接触区域电耦合的存储电极之后，通过提供包括硅的第一气体和存储电极形成HSG硅层，第二气体以约1.0:0.1至约1.0:5.0的体积比存储在存储电极的表面上。在HSG硅层上依次形成电介质层和平板电极。可以容易地调节HSG硅层的晶粒尺寸，并且可以抑制存储电极下部的HSG的异常生长。因此，HSG硅层可以均匀地形成在存储电极上，并且可以改善存储电极的结构稳定性，以防止电容器的电缺陷。

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