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21. 发明授权

US08139407B2 Nonvolatile semiconductor memory device including NAND-type flash memory and the like 有权
标题翻译：包括NAND型闪存等的非易失性半导体存储器件
公开(公告)号：US08139407B2
公开(公告)日：2012-03-20
申请号：US12955621
申请日：2010-11-29
申请人： Atsuhiro Sato , Keiji Shuto , Fumitaka Arai
发明人： Atsuhiro Sato , Keiji Shuto , Fumitaka Arai
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3418 , G11C11/5642 , G11C16/0483 , G11C2211/5642
摘要： A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.
摘要翻译：非易失性半导体存储器件设置有存储单元阵列，判断电位校正电路和读出电路。在存储单元阵列中，以矩阵形式布置多个存储单元，并且阵列包括作为读出对象的第一存储单元和与第一存储单元相邻设置的第二存储单元。判定电位校正电路根据第二存储单元的阈值校正判定电位。读出电路通过使用校正的判断电位读出作为读出对象的第一存储单元。

22. 发明授权

US08088661B2 Nonvolatile semiconductor memory with resistance elements and method of manufacturing the same 失效
标题翻译：具有电阻元件的非易失性半导体存储器及其制造方法
公开(公告)号：US08088661B2
公开(公告)日：2012-01-03
申请号：US12652548
申请日：2010-01-05
申请人： Fumitaka Arai , Atsuhiro Sato
发明人： Fumitaka Arai , Atsuhiro Sato
IPC分类号： H01L29/72
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11539 , H01L29/78
摘要： A nonvolatile semiconductor memory of an aspect of the present invention comprises a memory cell transistor and a resistance element arranged on a semiconductor substrate. The memory cell transistor includes a floating gate electrode constituted of a first conductive material arranged on a gate insulating film on a surface of the semiconductor substrate, an inter-gate insulating film arranged on the floating gate electrode, a control gate electrode arranged on the inter-gate insulating film, and a source/drain diffusion layer provided in the semiconductor substrate. The resistance element includes an element isolation insulating layer arranged in the semiconductor substrate and including a depression, and a resistor constituted of a second conductive material filling up the depression. An impurity concentration of the second conductive material is lower than that of the first conductive material.
摘要翻译：本发明的一个方面的非易失性半导体存储器包括存储单元晶体管和布置在半导体衬底上的电阻元件。存储单元晶体管包括由在半导体衬底的表面上配置在栅极绝缘膜上的第一导电材料构成的浮置栅极电极，布置在浮置栅电极上的栅极间绝缘膜，栅极绝缘膜和设置在半导体衬底中的源极/漏极扩散层。电阻元件包括布置在半导体衬底中并包括凹陷的元件隔离绝缘层和由填充凹陷的第二导电材料构成的电阻器。第二导电材料的杂质浓度低于第一导电材料的杂质浓度。

23. 发明授权

US08084324B2 Nonvolatile semiconductor memory and fabrication method for the same 有权
标题翻译：非易失性半导体存储器及其制造方法相同
公开(公告)号：US08084324B2
公开(公告)日：2011-12-27
申请号：US12720062
申请日：2010-03-09
申请人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
发明人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/4763
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0433 , G11C16/0483 , G11C16/30 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region of the high voltage transistor.
摘要翻译：非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧道绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层和第一金属硅化物膜; 包括形成在高压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层和第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅极电极层和第三金属硅化物膜的低压晶体管; 以及直接设置在存储单元晶体管的第一源极和漏极区域，低压晶体管的第二源极和漏极区域以及高压晶体管的第三源极和漏极区域中的衬垫绝缘膜。

24. 发明授权

US07859898B2 Nonvolatile semiconductor memory device including NAND-type flash memory and the like 有权
标题翻译：包括NAND型闪存等的非易失性半导体存储器件
公开(公告)号：US07859898B2
公开(公告)日：2010-12-28
申请号：US12354946
申请日：2009-01-16
申请人： Atsuhiro Sato , Keiji Shuto , Fumitaka Arai
发明人： Atsuhiro Sato , Keiji Shuto , Fumitaka Arai
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3418 , G11C11/5642 , G11C16/0483 , G11C2211/5642
摘要： A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.
摘要翻译：非易失性半导体存储器件设置有存储单元阵列，判断电位校正电路和读出电路。在存储单元阵列中，以矩阵形式布置多个存储单元，并且阵列包括作为读出对象的第一存储单元和与第一存储单元相邻设置的第二存储单元。判定电位校正电路根据第二存储单元的阈值校正判定电位。读出电路通过使用校正的判断电位读出作为读出对象的第一存储单元。

25. 发明申请

US20120037976A1 NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20120037976A1
公开(公告)日：2012-02-16
申请号：US13235948
申请日：2011-09-19
申请人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
发明人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
IPC分类号： H01L27/105
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0433 , G11C16/0483 , G11C16/30 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on a high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on source and drain regions of each of the memory cell transistor, the low voltage transistor, and the high voltage transistor.
摘要翻译：非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧穿绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层以及第一金属硅化物膜; 包括形成在高压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层以及第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅电极层和第三金属硅化物膜的低压晶体管; 以及直接设置在每个存储单元晶体管，低压晶体管和高压晶体管的源极和漏极区域上的衬垫绝缘膜。

26. 发明授权

US07983086B2 NAND flash memory 失效
标题翻译： NAND闪存
公开(公告)号：US07983086B2
公开(公告)日：2011-07-19
申请号：US12564598
申请日：2009-09-22
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： G11C16/00
CPC分类号： G11C11/5628 , G11C16/0483
摘要： In a state in which a first and second selection gate transistors are turned off and a first voltage is applied to a control gate of a second memory cell transistor which is connected to a source line side of a first memory cell transistor selected from among the memory cell transistors and which is to be cut off, a second voltage which is higher than the first voltage and which causes a plurality of third memory cell transistors remaining unselected in the memory cell transistors to conduct is applied to control gates of the third memory cell transistors, and thereafter a threshold voltage of the first memory cell transistor is changed to a threshold voltage higher than the first threshold voltage corresponding to the erase state by applying a third voltage which is higher than the second voltage to a control gate of the first memory cell transistor.
摘要翻译：在第一和第二选择栅极晶体管被截止并且第一电压被施加到第二存储单元晶体管的控制栅极的状态下，第二存储单元晶体管连接到从存储器中选择的第一存储单元晶体管的源极线侧单元晶体管并且要被切断，高于第一电压的第二电压并且使得在存储单元晶体管导通时保持未选择的多个第三存储单元晶体管被施加到第三存储单元晶体管的控制栅极之后，通过向第一存储单元的控制栅极施加高于第二电压的第三电压，将第一存储单元晶体管的阈值电压改变为高于与擦除状态相对应的第一阈值电压的阈值电压晶体管。

27. 发明申请

US20100173471A1 NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20100173471A1
公开(公告)日：2010-07-08
申请号：US12720062
申请日：2010-03-09
申请人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
发明人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0433 , G11C16/0483 , G11C16/30 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region of the high voltage transistor.
摘要翻译：非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧道绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层和第一金属硅化物膜; 包括形成在高压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层和第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅极电极层和第三金属硅化物膜的低压晶体管; 以及直接设置在存储单元晶体管的第一源极和漏极区域，低压晶体管的第二源极和漏极区域以及高压晶体管的第三源极和漏极区域中的衬垫绝缘膜。

28. 发明申请

US20100105177A1 NONVOLATILE SEMICONDUCTOR MEMORY WITH RESISTANCE ELEMENTS AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：具有电阻元件的非线性半导体存储器及其制造方法
公开(公告)号：US20100105177A1
公开(公告)日：2010-04-29
申请号：US12652548
申请日：2010-01-05
申请人： Fumitaka ARAI , Atsuhiro Sato
发明人： Fumitaka ARAI , Atsuhiro Sato
IPC分类号： H01L21/02 , H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11539 , H01L29/78
摘要： A nonvolatile semiconductor memory of an aspect of the present invention comprises a memory cell transistor and a resistance element arranged on a semiconductor substrate. The memory cell transistor includes a floating gate electrode constituted of a first conductive material arranged on a gate insulating film on a surface of the semiconductor substrate, an inter-gate insulating film arranged on the floating gate electrode, a control gate electrode arranged on the inter-gate insulating film, and a source/drain diffusion layer provided in the semiconductor substrate. The resistance element includes an element isolation insulating layer arranged in the semiconductor substrate and including a depression, and a resistor constituted of a second conductive material filling up the depression. An impurity concentration of the second conductive material is lower than that of the first conductive material.
摘要翻译：本发明的一个方面的非易失性半导体存储器包括存储单元晶体管和布置在半导体衬底上的电阻元件。存储单元晶体管包括由在半导体衬底的表面上配置在栅极绝缘膜上的第一导电材料构成的浮置栅极电极，布置在浮置栅电极上的栅极间绝缘膜，栅极绝缘膜和设置在半导体衬底中的源极/漏极扩散层。电阻元件包括布置在半导体衬底中并包括凹陷的元件隔离绝缘层和由填充凹陷的第二导电材料构成的电阻器。第二导电材料的杂质浓度低于第一导电材料的杂质浓度。

29. 发明授权

US07705394B2 Nonvolatile semicondutor memory with metallic silicide film electrically connected to a control gate electrode layer 失效
标题翻译：非易失性半导体存储器，其与金属硅化物膜电连接到控制栅电极层
公开(公告)号：US07705394B2
公开(公告)日：2010-04-27
申请号：US11553661
申请日：2006-10-27
申请人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
发明人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0433 , G11C16/0483 , G11C16/30 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on first, second and third source and drain regions of the memory cell transistor, low voltage transistor, and high voltage transistor, respectively.
摘要翻译：非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧穿绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层以及第一金属硅化物膜; 包括形成在高电压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层以及第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅电极层和第三金属硅化物膜的低压晶体管; 以及分别直接设置在存储单元晶体管，低压晶体管和高压晶体管的第一，第二和第三源极和漏极区上的衬垫绝缘膜。

30. 发明授权

US07663178B2 Nonvolatile semiconductor memory with resistance elements and method of manufacturing the same 失效
标题翻译：具有电阻元件的非易失性半导体存储器及其制造方法
公开(公告)号：US07663178B2
公开(公告)日：2010-02-16
申请号：US11850978
申请日：2007-09-06
申请人： Fumitaka Arai , Atsuhiro Sato
发明人： Fumitaka Arai , Atsuhiro Sato
IPC分类号： H01L29/72
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11539 , H01L29/78
摘要： A nonvolatile semiconductor memory of an aspect of the present invention comprises a memory cell transistor and a resistance element arranged on a semiconductor substrate. The memory cell transistor includes a floating gate electrode constituted of a first conductive material arranged on a gate insulating film on a surface of the semiconductor substrate, an inter-gate insulating film arranged on the floating gate electrode, a control gate electrode arranged on the inter-gate insulating film, and a source/drain diffusion layer provided in the semiconductor substrate. The resistance element includes an element isolation insulating layer arranged in the semiconductor substrate and including a depression, and a resistor constituted of a second conductive material filling up the depression. An impurity concentration of the second conductive material is lower than that of the first conductive material.
摘要翻译：本发明的一个方面的非易失性半导体存储器包括存储单元晶体管和布置在半导体衬底上的电阻元件。存储单元晶体管包括由在半导体衬底的表面上配置在栅极绝缘膜上的第一导电材料构成的浮置栅极电极，布置在浮置栅电极上的栅极间绝缘膜，栅极绝缘膜和设置在半导体衬底中的源极/漏极扩散层。电阻元件包括布置在半导体衬底中并包括凹陷的元件隔离绝缘层和由填充凹陷的第二导电材料构成的电阻器。第二导电材料的杂质浓度低于第一导电材料的杂质浓度。

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