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21. 发明申请

US20080265422A1 STRUCTURE FOR CHARGE DISSIPATION DURING FABRICATION OF INTEGRATED CIRCUITS AND ISOLATION THEREOF 有权
标题翻译：集成电路制造过程中的充电结构及其隔离结构
公开(公告)号：US20080265422A1
公开(公告)日：2008-10-30
申请号：US12166362
申请日：2008-07-02
申请人： John Joseph Ellis-Monaghan , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Steven Howard Voldman
发明人： John Joseph Ellis-Monaghan , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Steven Howard Voldman
IPC分类号： H01L23/48
CPC分类号： H01L27/0248 , Y10S438/926
摘要： A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.
摘要翻译：用于在集成电路制造期间耗散电荷的结构。该结构包括：半导体衬底中的衬底接触; 衬底上的一个或多个布线层; 一个或多个导电电荷耗散结构，其从所述一个或多个布线层的最上层布线层的顶表面延伸通过所述一个或多个布线层的每个下布线层与所述基板接触电接触; 以及在基板中和在一个或多个布线层中的电路结构，电荷耗散结构在电路结构之间分散的一个或多个电荷耗散结构不会电接触任何一个或多个布线层中的任何一个电路结构。

22. 发明授权

US07861204B2 Structures including integrated circuits for reducing electromigration effect 有权
标题翻译：包括用于降低电迁移效应的集成电路的结构
公开(公告)号：US07861204B2
公开(公告)日：2010-12-28
申请号：US11960853
申请日：2007-12-20
申请人： Anthony Kendall Stamper , Timothy Dooling Sullivan , Ping-Chuan Wang
发明人： Anthony Kendall Stamper , Timothy Dooling Sullivan , Ping-Chuan Wang
IPC分类号： G06F17/50
CPC分类号： H01L23/53223 , H01L23/528 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A design structure including an integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) directly above the first source/drain region and (ii) electrically coupled to the first source/drain region through first contact regions and second contact regions, respectively. The first and second electrically conductive line segments (i) reside in a first interconnect layer of the integrated circuit and (ii) run in the reference direction. The IC further includes an electrically conductive line being (i) directly above the first source/drain region, (ii) electrically coupled to the first and second electrically conductive line segments through a first via and a second via, respectively, (iii) resides in a second interconnect layer of the integrated circuit, and (iv) runs in the reference direction.
摘要翻译：一种设计结构，包括用于降低电迁移效应的集成电路。 IC包括具有第一和第二源/漏区的衬底和功率晶体管。 IC还包括第一，第二和第三导电线段，其直接在第一源极/漏极区域的上方，以及（ii）分别通过第一接触区域和第二接触区域电耦合到第一源极/漏极区域。第一和第二导电线段（i）驻留在集成电路的第一互连层中，并且（ii）沿参考方向延伸。 IC还包括导电线，其是（i）直接在第一源极/漏极区域上方，（ii）分别通过第一通孔和第二通孔电耦合到第一和第二导电线段，（iii）驻留在集成电路的第二互连层中，以及（iv）在参考方向上延伸。

23. 发明申请

US20090273084A1 OPTICALLY TRANSPARENT WIRES FOR SECURE CIRCUITS AND METHODS OF MAKING SAME 有权
标题翻译：用于安全电路的光学透明线及其制造方法
公开(公告)号：US20090273084A1
公开(公告)日：2009-11-05
申请号：US12115056
申请日：2008-05-05
申请人： Stephen Peter Ayotte , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Kimball M. Watson
发明人： Stephen Peter Ayotte , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Kimball M. Watson
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/522 , H01L21/76849 , H01L21/76867 , H01L21/76888 , H01L23/53214 , H01L23/53238 , H01L23/53257 , H01L23/57 , H01L2924/0002 , H01L2924/00
摘要： A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.
摘要翻译：一种结构和方法。该方法包括：在基板上形成电介质层; 在所述电介质层中形成导电的第一和第二布线，所述第一和第二布线的顶表面与所述电介质层的顶表面共面; 并且（i）在介电层的顶表面上形成导电的第三导线，并且在第一和第二导线的顶表面之上，第三线电连接第一和第二导线中的每一个，第三线不可检测通过光学显微镜检查或（ii）在电介质层的顶表面和衬底之间形成导电的第三线，第三电线电接触第一和第二电线中的每一个，第三电线不能通过光学显微镜检测。

24. 发明授权

US06243283B1 Impedance control using fuses 有权
标题翻译：使用熔断器进行阻抗控制
公开(公告)号：US06243283B1
公开(公告)日：2001-06-05
申请号：US09589922
申请日：2000-06-07
申请人： Claude Louis Bertin , John A. Fifield , Erik Leigh Hedberg , Russell J. Houghton , Timothy Dooling Sullivan , Steven William Tomashot , William Robert Tonti
发明人： Claude Louis Bertin , John A. Fifield , Erik Leigh Hedberg , Russell J. Houghton , Timothy Dooling Sullivan , Steven William Tomashot , William Robert Tonti
IPC分类号： G11C506
CPC分类号： H01L23/481 , G11C17/16 , H01L25/0657 , H01L2224/06181 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/48227 , H01L2224/4826 , H01L2225/06517 , H01L2225/06541 , H01L2225/06555 , H01L2225/06562 , H01L2225/06589 , H01L2225/06596 , H01L2924/01012 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/13091 , H01L2924/15192 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2924/00012
摘要： A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective device; connecting a current source device associated with each fuse device in the integrated circuit, the current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the current source and the I/O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I/O connection. Such a system and method is employed in a memory system comprising integrated circuit chips disposed in a stacked relation, with each chip including: a layer of active circuitry formed at a first layer of each chip; a plurality of through conducting structures disposed substantially vertically through each chip for enabling electronic connection with active circuitry at the first layer; second conducting device disposed at an end of the through conducting structure at an opposite side of a chip for connection with a corresponding through conductive structure of an adjacent stacked chip, the stacked chip structure formed by aligning one or more through conducting structures and second conducting devices of adjacent chips, whereby a chip of the stack is electronically connected to active circuitry formed on other chips of the stack. The stacked chip structure is ideal for reducing data access latency in memory systems employing memory chips such as DRAM.
摘要翻译：一种用于减少半导体集成电路器件的阻抗负载的系统和方法，其实现了有助于I / O焊盘连接处的阻抗加载的保护器件结构。该方法包括在I / O焊盘连接和保护装置之间设置熔丝装置; 连接与所述集成电路中的每个熔丝装置相关联的电流源装置，所述电流源装置连接到所述熔丝装置的一端; 提供保险丝选择电路，用于在电流源和I / O连接之间激活通过选定的保险丝装置的电流流动，电流量足以吹入保险丝并将保护装置与电路结构断开，从而减少阻抗负载在I / O连接。这种系统和方法被用在包括以堆叠关系布置的集成电路芯片的存储器系统中，每个芯片包括：形成在每个芯片的第一层的有源电路层; 多个通过导电结构，其基本垂直设置穿过每个芯片，以使得能够与第一层处的有源电路电连接; 第二导电装置，其设置在通孔导电结构的与芯片相对侧的端部处，与相邻的堆叠芯片的相应的贯穿导电结构相连接，所述堆叠的芯片结构通过将一个或多个穿过导电结构和第二导电装置的相邻芯片，由此堆叠的芯片电连接到形成在堆叠的其他芯片上的有源电路。堆叠式芯片结构非常适用于采用诸如DRAM之类的存储器芯片的存储器系统中的数据访问延迟。

25. 发明授权

US06219215B1 Chip thermal protection device 有权
标题翻译：芯片热保护装置
公开(公告)号：US06219215B1
公开(公告)日：2001-04-17
申请号：US09303042
申请日：1999-04-30
申请人： Claude Louis Bertin , Erik Leigh Hedberg , Timothy Dooling Sullivan , William Robert Tonti
发明人： Claude Louis Bertin , Erik Leigh Hedberg , Timothy Dooling Sullivan , William Robert Tonti
IPC分类号： H02H300
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10T307/25 , H01L2924/00
摘要： A gap conducting structure for an integrated electronic circuit that functions as an electronic fuse device and that is integrated as part of the semi-conductor chip wiring for providing over-current and thermal runaway protection. The gap conducting structure includes one or more air gap regions of predefined volume that fully or partially exposes a length of interlevel conductor layer in an IC. Alternately, the air gap region may wholly located within the dielectric region below a corresponding conductor and separated by insulator. When functioning as a fuse, the gap region acts to reduce thermal conductivity away from the exposed portion of the conductor enabling generation of higher heat currents in the conducting line with lower applied voltages sufficient to destruct a part of the partially exposed/fully exposed conducting line, thus preventing thermal runaway and over-current condition. The presence of gaps, and hence, the fuses, are scalable and may be tailored to the capacity of currents they must carry with the characteristics of the fuses defined by a circuit designer.
摘要翻译：用作集成电子电路的间隙导电结构，其用作电子熔断器件，并且被集成为用于提供过电流和热失控保护的半导体芯片布线的一部分。间隙导电结构包括一个或多个预定体积的气隙区域，其完全或部分地暴露IC中的层间导体层的长度。或者，气隙区域可以完全位于相应导体下方的电介质区域内并被绝缘体分隔开。当用作熔丝时，间隙区域用于降低远离导体的暴露部分的热导率，使得能够以较低的施加电压在导电线中产生更高的热流，足以破坏部分暴露/完全暴露的导电线的一部分，从而防止热失控和过电流状态。间隙的存在以及保险丝的存在是可扩展的，并且可以根据电路设计者定义的保险丝的特性来适应其必须携带的电流的容量。

26. 发明授权

US6141245A Impedance control using fuses 有权
标题翻译：使用熔断器进行阻抗控制
公开(公告)号：US6141245A
公开(公告)日：2000-10-31
申请号：US302902
申请日：1999-04-30
申请人： Claude Louis Bertin , John A. Fifield , Erik Leigh Hedberg , Russell J. Houghton , Timothy Dooling Sullivan , Steven William Tomashot , William Robert Tonti
发明人： Claude Louis Bertin , John A. Fifield , Erik Leigh Hedberg , Russell J. Houghton , Timothy Dooling Sullivan , Steven William Tomashot , William Robert Tonti
IPC分类号： H01L27/02 , G11C17/16 , H01L25/065 , G11C16/04
CPC分类号： H01L23/481 , G11C17/16 , H01L25/0657 , H01L2224/06181 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/48227 , H01L2224/4826 , H01L2225/06517 , H01L2225/06541 , H01L2225/06555 , H01L2225/06562 , H01L2225/06589 , H01L2225/06596 , H01L2924/01012 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/13091 , H01L2924/15192 , H01L2924/181 , H01L2924/3011
摘要： A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective device; connecting a current source device associated with each fuse device in the integrated circuit, the current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the current source and the I/O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I/O connection. Such a system and method is employed in a memory system comprising integrated circuit chips disposed in a stacked relation, with each chip including: a layer of active circuitry formed at a first layer of each chip; a plurality of through conducting structures disposed substantially vertically through each chip for enabling electronic connection with active circuitry at the first layer; second conducting device disposed at an end of the through conducting structure at an opposite side of a chip for connection with a corresponding through conductive structure of an adjacent stacked chip, the stacked chip structure formed by aligning one or more through conducting structures and second conducting devices of adjacent chips, whereby a chip of the stack is electronically connected to active circuitry formed on other chips of the stack. The stacked chip structure is ideal for reducing data access latency in memory systems employing memory chips such as DRAM.
摘要翻译：一种用于减少半导体集成电路器件的阻抗负载的系统和方法，其实现了有助于I / O焊盘连接处的阻抗加载的保护器件结构。该方法包括在I / O焊盘连接和保护装置之间设置熔丝装置; 连接与所述集成电路中的每个熔丝装置相关联的电流源装置，所述电流源装置连接到所述熔丝装置的一端; 提供保险丝选择电路，用于在电流源和I / O连接之间激活通过选定的保险丝装置的电流流动，电流量足以吹入保险丝并将保护装置与电路结构断开，从而减少阻抗负载在I / O连接。这种系统和方法被用在包括以堆叠关系布置的集成电路芯片的存储器系统中，每个芯片包括：形成在每个芯片的第一层的有源电路层; 多个通过导电结构，其基本垂直设置穿过每个芯片，以使得能够与第一层处的有源电路电连接; 第二导电装置，其设置在通孔导电结构的与芯片相对侧的端部处，与相邻的堆叠芯片的相应的贯穿导电结构相连接，所述堆叠的芯片结构通过将一个或多个穿过导电结构和第二导电装置的相邻芯片，由此堆叠的芯片电连接到形成在堆叠的其他芯片上的有源电路。堆叠式芯片结构非常适用于采用诸如DRAM之类的存储器芯片的存储器系统中的数据访问延迟。

27. 发明授权

US08592976B2 Ball-limiting-metallurgy layers in solder ball structures 失效
标题翻译：焊球结构中的限界冶金层
公开(公告)号：US08592976B2
公开(公告)日：2013-11-26
申请号：US13615826
申请日：2012-09-14
申请人： Charles L. Arvin , Timothy Harrison Daubenspeck , Wolfgang Sauter , Timothy Dooling Sullivan
发明人： Charles L. Arvin , Timothy Harrison Daubenspeck , Wolfgang Sauter , Timothy Dooling Sullivan
IPC分类号： H01L23/48
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/12 , H01L24/94 , H01L2224/03912 , H01L2224/0401 , H01L2224/05557 , H01L2224/05558 , H01L2224/05559 , H01L2224/1147 , H01L2224/13006 , H01L2224/13017 , H01L2224/13022 , H01L2224/13099 , H01L2224/274 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/00012
摘要： A structure. The structure includes: a first dielectric layer which includes a top dielectric surface; an electrically conductive line on the first dielectric layer; a second dielectric layer on the first dielectric layer and the electrically conductive line; a ball-limiting-metallurgy (BLM) region on the second dielectric layer and the electrically conductive line such that the BLM region is electrically connected to the electrically conductive line; and a solder ball on the BLM region. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface and is entirely in the BLM region does not exceed a pre-specified maximum value, wherein the pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface.
摘要翻译：一个结构。该结构包括：第一电介质层，其包括顶部电介质表面; 在所述第一电介质层上的导电线; 在所述第一电介质层和所述导电线上的第二电介质层; 所述第二电介质层和所述导电线上的限界冶金（BLM）区域使得所述BLM区电连接到所述导电线; 和BLM区域上的焊球。 BLM区域的特征在于，平行于顶部电介质表面并且完全在BLM区域中的最长直线段的长度不超过预定的最大值，其中预定的最大值最多为 BLM区域的最大水平尺寸的一半在平行于顶部电介质表面的水平方向上测量。

28. 发明授权

US08017514B2 Optically transparent wires for secure circuits and methods of making same 有权
标题翻译：用于安全电路的光学透明导线及其制造方法
公开(公告)号：US08017514B2
公开(公告)日：2011-09-13
申请号：US12115056
申请日：2008-05-05
申请人： Stephen Peter Ayotte , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Kimball M. Watson
发明人： Stephen Peter Ayotte , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Kimball M. Watson
IPC分类号： H01L21/00
CPC分类号： H01L23/522 , H01L21/76849 , H01L21/76867 , H01L21/76888 , H01L23/53214 , H01L23/53238 , H01L23/53257 , H01L23/57 , H01L2924/0002 , H01L2924/00
摘要： A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.
摘要翻译：一种结构和方法。该方法包括：在基板上形成电介质层; 在所述电介质层中形成导电的第一和第二布线，所述第一和第二布线的顶表面与所述电介质层的顶表面共面; 并且（i）在介电层的顶表面上形成导电的第三导线，并且在第一和第二导线的顶表面之上，第三线电连接第一和第二导线中的每一个，第三线不可检测通过光学显微镜检查或（ii）在电介质层的顶表面和衬底之间形成导电的第三线，第三电线电接触第一和第二电线中的每一个，第三电线不能通过光学显微镜检测。

29. 发明申请

US20100258940A1 BALL-LIMITING-METALLURGY LAYERS IN SOLDER BALL STRUCTURES 有权
标题翻译：焊接球结构中的限流金属层
公开(公告)号：US20100258940A1
公开(公告)日：2010-10-14
申请号：US12547540
申请日：2009-08-26
申请人： Charles L. Arvin , Timothy Harrison Daubenspeck , Wolfgang Sauter , Timothy Dooling Sullivan
发明人： Charles L. Arvin , Timothy Harrison Daubenspeck , Wolfgang Sauter , Timothy Dooling Sullivan
IPC分类号： H01L23/488 , H01L21/60 , H01L21/768
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/12 , H01L24/94 , H01L2224/03912 , H01L2224/0401 , H01L2224/05557 , H01L2224/05558 , H01L2224/05559 , H01L2224/1147 , H01L2224/13006 , H01L2224/13017 , H01L2224/13022 , H01L2224/13099 , H01L2224/274 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/00012
摘要： A solder ball structure and a method for forming the same. The structure includes (i) a first dielectric layer which includes a top dielectric surface, (ii) an electrically conductive line, (iii) a second dielectric layer, (iv) a ball-limiting-metallurgy (BLM) region, and (v) a solder ball. The BLM region is electrically connected to the electrically conductive line and the solder ball. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface of the first dielectric layer and is entirely in the BLM region does not exceed a pre-specified maximum value. The pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface of the first dielectric layer.
摘要翻译：焊球结构及其形成方法。该结构包括（i）包括顶部电介质表面的第一电介质层，（ii）导电线，（iii）第二电介质层，（iv）球限制冶金（BLM）区域和（v ）焊球。 BLM区域电连接到导电线和焊球。 BLM区域具有与第一介电层的顶部电介质表面平行且完全在BLM区域中的最长直线段的长度不超过预定的最大值的特性。预定的最大值为平行于第一介电层的顶部电介质表面的水平方向上测量的BLM区域的最大水平尺寸的至多一半。

30. 发明授权

US07741722B2 Through-wafer vias 有权
标题翻译：通晶圆通孔
公开(公告)号：US07741722B2
公开(公告)日：2010-06-22
申请号：US11690181
申请日：2007-03-23
申请人： Paul Stephen Andry , Edmund Juris Sprogis , Kenneth Jay Stein , Timothy Dooling Sullivan , Cornelia Kang-I Tsang , Ping-Chuan Wang , Bucknell C. Webb
发明人： Paul Stephen Andry , Edmund Juris Sprogis , Kenneth Jay Stein , Timothy Dooling Sullivan , Cornelia Kang-I Tsang , Ping-Chuan Wang , Bucknell C. Webb
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A through-wafer via structure and method for forming the same. The through-wafer via structure includes a wafer having an opening and a top wafer surface. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The through-wafer via structure further includes a through-wafer via in the opening. The through-wafer via has a shape of a rectangular plate. A height of the through-wafer via in the first reference direction essentially equals a thickness of the wafer in the first reference direction. A length of the through-wafer via in a second reference direction is at least ten times greater than a width of the through-wafer via in a third reference direction. The first, second, and third reference directions are perpendicular to each other.
摘要翻译：一种晶片通孔结构及其形成方法。贯通晶片通孔结构包括具有开口和顶部晶片表面的晶片。顶部晶片表面限定垂直于顶部晶片表面的第一参考方向。贯通晶片通孔结构还包括在开口中的通晶片通孔。贯通晶片通孔具有矩形板的形状。贯通晶片通孔在第一参考方向上的高度基本上等于晶片在第一参考方向上的厚度。贯穿晶片通孔在第二参考方向上的长度比通过晶片通孔在第三参考方向上的宽度大至少十倍。第一，第二和第三参考方向彼此垂直。

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