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1. 发明授权

US08110875B2 Structure for charge dissipation during fabrication of integrated circuits and isolation thereof 有权
标题翻译：集成电路制造过程中电荷耗散的结构及其分离
公开(公告)号：US08110875B2
公开(公告)日：2012-02-07
申请号：US12166362
申请日：2008-07-02
申请人： John Joseph Ellis-Monaghan , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Steven Howard Voldman
发明人： John Joseph Ellis-Monaghan , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Steven Howard Voldman
IPC分类号： H01L23/62
CPC分类号： H01L27/0248 , Y10S438/926
摘要： A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.
摘要翻译：用于在集成电路制造期间耗散电荷的结构。该结构包括：半导体衬底中的衬底接触; 衬底上的一个或多个布线层; 一个或多个导电电荷耗散结构，其从所述一个或多个布线层的最上层布线层的顶表面延伸通过所述一个或多个布线层的每个下布线层与所述基板接触电接触; 以及在基板中和在一个或多个布线层中的电路结构，电荷耗散结构在电路结构之间分散的一个或多个电荷耗散结构不会电接触任何一个或多个布线层中的任何一个电路结构。

2. 发明申请

US20080265422A1 STRUCTURE FOR CHARGE DISSIPATION DURING FABRICATION OF INTEGRATED CIRCUITS AND ISOLATION THEREOF 有权
标题翻译：集成电路制造过程中的充电结构及其隔离结构
公开(公告)号：US20080265422A1
公开(公告)日：2008-10-30
申请号：US12166362
申请日：2008-07-02
申请人： John Joseph Ellis-Monaghan , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Steven Howard Voldman
发明人： John Joseph Ellis-Monaghan , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Steven Howard Voldman
IPC分类号： H01L23/48
CPC分类号： H01L27/0248 , Y10S438/926
摘要： A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.
摘要翻译：用于在集成电路制造期间耗散电荷的结构。该结构包括：半导体衬底中的衬底接触; 衬底上的一个或多个布线层; 一个或多个导电电荷耗散结构，其从所述一个或多个布线层的最上层布线层的顶表面延伸通过所述一个或多个布线层的每个下布线层与所述基板接触电接触; 以及在基板中和在一个或多个布线层中的电路结构，电荷耗散结构在电路结构之间分散的一个或多个电荷耗散结构不会电接触任何一个或多个布线层中的任何一个电路结构。

3. 发明授权

US08193563B2 High power device isolation and integration 有权
标题翻译：大功率器件隔离和集成
公开(公告)号：US08193563B2
公开(公告)日：2012-06-05
申请号：US12768877
申请日：2010-04-28
申请人： Jeffrey Peter Gambino , Steven Howard Voldman , Michael Joseph Zierak
发明人： Jeffrey Peter Gambino , Steven Howard Voldman , Michael Joseph Zierak
IPC分类号： H01L29/66
CPC分类号： H01L21/76229 , H01L21/76232 , H01L21/823481 , H01L21/84 , H01L27/088 , H01L29/0653 , H01L29/0878 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7824 , H01L29/7835
摘要： A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device.
摘要翻译：一种制造结构的结构和方法。所述结构包括：在半导体衬底中的介电隔离，所述电介质隔离部在垂直于所述衬底的顶表面的方向上延伸到所述衬底中的第一距离，围绕所述衬底的第一区域和所述第二区域的介电隔离，介质隔离的顶表面与基底的顶表面共面; 在所述基板的所述第二区域中的介电区域; 所述电介质区域沿垂直方向延伸到所述衬底中第二距离，所述第一距离大于所述第二距离; 以及第一区域中的第一器件和第二区域中的第二器件，所述第一器件不同于所述第二器件，所述电介质区域将所述第二器件的第一元件与所述第二器件的第二元件隔离。

4. 发明授权

US07781292B2 High power device isolation and integration 有权
标题翻译：大功率器件隔离和集成
公开(公告)号：US07781292B2
公开(公告)日：2010-08-24
申请号：US11741889
申请日：2007-04-30
申请人： Jeffrey Peter Gambino , Steven Howard Voldman , Michael Joseph Zierak
发明人： Jeffrey Peter Gambino , Steven Howard Voldman , Michael Joseph Zierak
IPC分类号： H01L21/336
CPC分类号： H01L21/76229 , H01L21/76232 , H01L21/823481 , H01L21/84 , H01L27/088 , H01L29/0653 , H01L29/0878 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7824 , H01L29/7835
摘要： A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device.
摘要翻译：一种制造结构的结构和方法。所述结构包括：在半导体衬底中的介电隔离，所述电介质隔离部在垂直于所述衬底的顶表面的方向上延伸到所述衬底中的第一距离，围绕所述衬底的第一区域和所述第二区域的介电隔离，介质隔离的顶表面与基底的顶表面共面; 在所述基板的所述第二区域中的介电区域; 所述电介质区域沿垂直方向延伸到所述衬底中第二距离，所述第一距离大于所述第二距离; 以及第一区域中的第一器件和第二区域中的第二器件，所述第一器件不同于所述第二器件，所述电介质区域将所述第二器件的第一元件与所述第二器件的第二元件隔离。

5. 发明申请

US20090127619A1 DEEP TRENCH SEMICONDUCTOR STRUCTURE AND METHOD 有权
标题翻译： DEEP TRENCH SEMICONDUCTOR结构与方法
公开(公告)号：US20090127619A1
公开(公告)日：2009-05-21
申请号：US11942756
申请日：2007-11-20
申请人： Jeffrey Peter Gambino , Benjamin Thomas Voegeli , Steven Howard Voldman , Michael Joseph Zierak
发明人： Jeffrey Peter Gambino , Benjamin Thomas Voegeli , Steven Howard Voldman , Michael Joseph Zierak
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823437 , H01L21/823828 , H01L29/1037 , H01L29/4236 , H01L29/66621 , H01L29/66787
摘要： An electrical structure and method of forming. The electrical structure includes a semiconductor substrate comprising a deep trench, an oxide liner layer is formed over an exterior surface of the deep trench, and a field effect transistor (FET) formed within the semiconductor substrate. The first FET includes a source structure, a drain structure, and a gate structure. The gate structure includes a gate contact connected to a polysilicon fill structure. The polysilicon fill structure is formed over the oxide liner layer and within the deep trench. The polysilicon fill structure is configured to flow current laterally across the polysilicon fill structure such that the current will flow parallel to a top surface of the semiconductor substrate.
摘要翻译：一种电气结构和成型方法。电结构包括半导体衬底，其包括深沟槽，在深沟槽的外表面上形成氧化物衬层，以及形成在半导体衬底内的场效应晶体管（FET）。第一FET包括源极结构，漏极结构和栅极结构。栅极结构包括连接到多晶硅填充结构的栅极触点。多晶硅填充结构形成在氧化物衬垫层之上和深沟槽内。多晶硅填充结构被配置为横向跨越多晶硅填充结构流动电流，使得电流平行于半导体衬底的顶表面流动。

6. 发明申请

US20100207233A1 HIGH POWER DEVICE ISOLATION AND INTEGRATION 有权
标题翻译：高功率器件隔离和集成
公开(公告)号：US20100207233A1
公开(公告)日：2010-08-19
申请号：US12768877
申请日：2010-04-28
申请人： Jeffrey Peter Gambino , Steven Howard Voldman , Michael Joseph Zierak
发明人： Jeffrey Peter Gambino , Steven Howard Voldman , Michael Joseph Zierak
IPC分类号： H01L29/06 , H01L27/12
CPC分类号： H01L21/76229 , H01L21/76232 , H01L21/823481 , H01L21/84 , H01L27/088 , H01L29/0653 , H01L29/0878 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7824 , H01L29/7835
摘要： A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device.
摘要翻译：一种制造结构的结构和方法。所述结构包括：在半导体衬底中的介电隔离，所述电介质隔离部在垂直于所述衬底的顶表面的方向上延伸到所述衬底中的第一距离，围绕所述衬底的第一区域和所述第二区域的介电隔离，介质隔离的顶表面与基底的顶表面共面; 在所述基板的所述第二区域中的介电区域; 所述电介质区域沿垂直方向延伸到所述衬底中第二距离，所述第一距离大于所述第二距离; 以及第一区域中的第一器件和第二区域中的第二器件，所述第一器件不同于所述第二器件，所述电介质区域将所述第二器件的第一元件与所述第二器件的第二元件隔离。

7. 发明授权

US08017995B2 Deep trench semiconductor structure and method 有权
标题翻译：深沟槽半导体结构及方法
公开(公告)号：US08017995B2
公开(公告)日：2011-09-13
申请号：US11942756
申请日：2007-11-20
申请人： Jeffrey Peter Gambino , Benjamin Thomas Voegeli , Steven Howard Voldman , Michael Joseph Zierak
发明人： Jeffrey Peter Gambino , Benjamin Thomas Voegeli , Steven Howard Voldman , Michael Joseph Zierak
IPC分类号： H01L31/119 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/823437 , H01L21/823828 , H01L29/1037 , H01L29/4236 , H01L29/66621 , H01L29/66787
摘要： An electrical structure and method of forming. The electrical structure includes a semiconductor substrate comprising a deep trench, an oxide liner layer is formed over an exterior surface of the deep trench, and a field effect transistor (FET) formed within the semiconductor substrate. The first FET includes a source structure, a drain structure, and a gate structure. The gate structure includes a gate contact connected to a polysilicon fill structure. The polysilicon fill structure is formed over the oxide liner layer and within the deep trench. The polysilicon fill structure is configured to flow current laterally across the polysilicon fill structure such that the current will flow parallel to a top surface of the semiconductor substrate.
摘要翻译：一种电气结构和成型方法。电结构包括半导体衬底，其包括深沟槽，在深沟槽的外表面上形成氧化物衬层，以及形成在半导体衬底内的场效应晶体管（FET）。第一FET包括源极结构，漏极结构和栅极结构。栅极结构包括连接到多晶硅填充结构的栅极触点。多晶硅填充结构形成在氧化物衬垫层之上和深沟槽内。多晶硅填充结构被配置为横向跨越多晶硅填充结构流动电流，使得电流平行于半导体衬底的顶表面流动。

8. 发明申请

US20080265363A1 HIGH POWER DEVICE ISOLATION AND INTEGRATION 有权
标题翻译：高功率器件隔离和集成
公开(公告)号：US20080265363A1
公开(公告)日：2008-10-30
申请号：US11741889
申请日：2007-04-30
申请人： Jeffrey Peter Gambino , Steven Howard Voldman , Michael Joseph Zierak
发明人： Jeffrey Peter Gambino , Steven Howard Voldman , Michael Joseph Zierak
IPC分类号： H01L21/8248 , H01L29/06
CPC分类号： H01L21/76229 , H01L21/76232 , H01L21/823481 , H01L21/84 , H01L27/088 , H01L29/0653 , H01L29/0878 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7824 , H01L29/7835
摘要： A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device.
摘要翻译：一种制造结构的结构和方法。所述结构包括：在半导体衬底中的介电隔离，所述电介质隔离部在垂直于所述衬底的顶表面的方向上延伸到所述衬底中的第一距离，围绕所述衬底的第一区域和所述第二区域的介电隔离，介质隔离的顶表面与基底的顶表面共面; 在所述基板的所述第二区域中的介电区域; 所述电介质区域沿垂直方向延伸到所述衬底中第二距离，所述第一距离大于所述第二距离; 以及第一区域中的第一器件和第二区域中的第二器件，所述第一器件不同于所述第二器件，所述电介质区域将所述第二器件的第一元件与所述第二器件的第二元件隔离。

9. 发明申请

US20120044732A1 ISOLATED EPITAXIAL MODULATION DEVICE 有权
标题翻译：隔离外来调制装置
公开(公告)号：US20120044732A1
公开(公告)日：2012-02-23
申请号：US13050536
申请日：2011-03-17
申请人： Yu Li , Steven Howard Voldman
发明人： Yu Li , Steven Howard Voldman
IPC分类号： H01L27/06 , H02M1/00 , H01L21/76
CPC分类号： H01L23/60 , H01L21/76283 , H01L21/823481 , H01L24/04 , H01L27/0277 , H01L27/0623 , H01L27/0635 , H01L2924/01037 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： An isolated epitaxial modulation device comprises a substrate; a barrier structure formed on the substrate; an isolated epitaxial region formed above the substrate and electrically isolated from the substrate by the barrier structure; a semiconductor device, the semiconductor device located in the isolated epitaxial region; and a modulation network formed on the substrate and electrically coupled to the semiconductor device. The device also comprises a bond pad and a ground pad. The isolated epitaxial region is electrically coupled to at least one of the bond pad and the ground pad. The semiconductor device and the epitaxial modulation network are configured to modulate an input voltage.
摘要翻译：隔离的外延调制装置包括基板; 形成在所述基板上的阻挡结构; 隔离的外延区，形成在衬底上并通过阻挡结构与衬底电隔离; 半导体器件，位于隔离的外延区域中的半导体器件; 以及形成在所述基板上并且电耦合到所述半导体器件的调制网络。该装置还包括接合焊盘和接地焊盘。隔离的外延区电耦合到接合焊盘和接地焊盘中的至少一个。半导体器件和外延调制网络被配置为调制输入电压。

10. 发明授权

US07541247B2 Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication 失效
标题翻译：使用LDMOS（横向双扩散金属氧化物半导体）器件制造的高压CMOS /低电压CMOS技术的保护环结构
公开(公告)号：US07541247B2
公开(公告)日：2009-06-02
申请号：US11778414
申请日：2007-07-16
申请人： Steven Howard Voldman
发明人： Steven Howard Voldman
IPC分类号： H01L21/336 , H01L21/761
CPC分类号： H01L29/7835 , H01L29/0619 , H01L29/0692 , H01L29/1083 , H01L29/1087 , H01L29/66659
摘要： A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate. The method further includes simultaneously forming a first doped transistor region of a first transistor and a first doped guard-ring region of a guard ring on the semiconductor substrate. The first doped transistor region and the first doped guard-ring region comprise dopants of a first doping polarity. The method further includes simultaneously forming a second doped transistor region of the first transistor and a second doped guard-ring region of the guard ring on the semiconductor substrate. The second doped transistor region and the second doped guard-ring region comprise dopants of the first doping polarity. The second doped guard-ring region is in direct physical contact with the first doped guard-ring region. The guard ring forms a closed loop around the first and second doped transistor regions.
摘要翻译：一种半导体结构及其形成方法。该方法包括提供半导体结构。半导体结构包括半导体衬底。该方法还包括在半导体衬底上同时形成第一晶体管的第一掺杂晶体管区域和保护环的第一掺杂保护环区域。第一掺杂晶体管区域和第一掺杂保护环区域包括第一掺杂极性的掺杂剂。该方法还包括在半导体衬底上同时形成第一晶体管的第二掺杂晶体管区域和保护环的第二掺杂保护环区域。第二掺杂晶体管区域和第二掺杂保护环区域包括第一掺杂极性的掺杂剂。第二掺杂保护环区域与第一掺杂保护环区域直接物理接触。保护环围绕第一和第二掺杂晶体管区域形成闭环。

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