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1. 发明授权

US08207609B2 Optically transparent wires for secure circuits and methods of making same 有权
标题翻译：用于安全电路的光学透明导线及其制造方法
公开(公告)号：US08207609B2
公开(公告)日：2012-06-26
申请号：US13195255
申请日：2011-08-01
申请人： Stephen Peter Ayotte , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Kimball M. Watson
发明人： Stephen Peter Ayotte , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Kimball M. Watson
IPC分类号： H01L21/00
CPC分类号： H01L23/522 , H01L21/76849 , H01L21/76867 , H01L21/76888 , H01L23/53214 , H01L23/53238 , H01L23/53257 , H01L23/57 , H01L2924/0002 , H01L2924/00
摘要： A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.
摘要翻译：一种结构和方法。该方法包括：在基板上形成电介质层; 在所述电介质层中形成导电的第一和第二布线，所述第一和第二布线的顶表面与所述电介质层的顶表面共面; 并且（i）在介电层的顶表面上形成导电的第三导线，并且在第一和第二导线的顶表面之上，第三导线与第一和第二导线中的每一个电接触，第三导线不可检测通过光学显微镜检查或（ii）在电介质层的顶表面和衬底之间形成导电的第三线，第三电线电接触第一和第二电线中的每一个，第三电线不能通过光学显微镜检测。

2. 发明申请

US20110284280A1 OPTICALLY TRANSPARENT WIRES FOR SECURE CIRCUITS AND METHODS OF MAKING SAME 有权
标题翻译：用于安全电路的光学透明线及其制造方法
公开(公告)号：US20110284280A1
公开(公告)日：2011-11-24
申请号：US13195255
申请日：2011-08-01
申请人： Stephen Peter Ayotte , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Kimball M. Watson
发明人： Stephen Peter Ayotte , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Kimball M. Watson
IPC分类号： H05K1/11
CPC分类号： H01L23/522 , H01L21/76849 , H01L21/76867 , H01L21/76888 , H01L23/53214 , H01L23/53238 , H01L23/53257 , H01L23/57 , H01L2924/0002 , H01L2924/00
摘要： A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.
摘要翻译：一种结构和方法。该方法包括：在基板上形成电介质层; 在所述电介质层中形成导电的第一和第二布线，所述第一和第二布线的顶表面与所述电介质层的顶表面共面; 并且（i）在介电层的顶表面上形成导电的第三导线，并且在第一和第二导线的顶表面之上，第三线电连接第一和第二导线中的每一个，第三线不可检测通过光学显微镜检查或（ii）在电介质层的顶表面和衬底之间形成导电的第三线，第三电线电接触第一和第二电线中的每一个，第三电线不能通过光学显微镜检测。

3. 发明申请

US20090273084A1 OPTICALLY TRANSPARENT WIRES FOR SECURE CIRCUITS AND METHODS OF MAKING SAME 有权
标题翻译：用于安全电路的光学透明线及其制造方法
公开(公告)号：US20090273084A1
公开(公告)日：2009-11-05
申请号：US12115056
申请日：2008-05-05
申请人： Stephen Peter Ayotte , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Kimball M. Watson
发明人： Stephen Peter Ayotte , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Kimball M. Watson
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/522 , H01L21/76849 , H01L21/76867 , H01L21/76888 , H01L23/53214 , H01L23/53238 , H01L23/53257 , H01L23/57 , H01L2924/0002 , H01L2924/00
摘要： A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.
摘要翻译：一种结构和方法。该方法包括：在基板上形成电介质层; 在所述电介质层中形成导电的第一和第二布线，所述第一和第二布线的顶表面与所述电介质层的顶表面共面; 并且（i）在介电层的顶表面上形成导电的第三导线，并且在第一和第二导线的顶表面之上，第三线电连接第一和第二导线中的每一个，第三线不可检测通过光学显微镜检查或（ii）在电介质层的顶表面和衬底之间形成导电的第三线，第三电线电接触第一和第二电线中的每一个，第三电线不能通过光学显微镜检测。

4. 发明授权

US08017514B2 Optically transparent wires for secure circuits and methods of making same 有权
标题翻译：用于安全电路的光学透明导线及其制造方法
公开(公告)号：US08017514B2
公开(公告)日：2011-09-13
申请号：US12115056
申请日：2008-05-05
申请人： Stephen Peter Ayotte , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Kimball M. Watson
发明人： Stephen Peter Ayotte , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Kimball M. Watson
IPC分类号： H01L21/00
CPC分类号： H01L23/522 , H01L21/76849 , H01L21/76867 , H01L21/76888 , H01L23/53214 , H01L23/53238 , H01L23/53257 , H01L23/57 , H01L2924/0002 , H01L2924/00
摘要： A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.
摘要翻译：一种结构和方法。该方法包括：在基板上形成电介质层; 在所述电介质层中形成导电的第一和第二布线，所述第一和第二布线的顶表面与所述电介质层的顶表面共面; 并且（i）在介电层的顶表面上形成导电的第三导线，并且在第一和第二导线的顶表面之上，第三线电连接第一和第二导线中的每一个，第三线不可检测通过光学显微镜检查或（ii）在电介质层的顶表面和衬底之间形成导电的第三线，第三电线电接触第一和第二电线中的每一个，第三电线不能通过光学显微镜检测。

5. 发明授权

US08110875B2 Structure for charge dissipation during fabrication of integrated circuits and isolation thereof 有权
标题翻译：集成电路制造过程中电荷耗散的结构及其分离
公开(公告)号：US08110875B2
公开(公告)日：2012-02-07
申请号：US12166362
申请日：2008-07-02
申请人： John Joseph Ellis-Monaghan , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Steven Howard Voldman
发明人： John Joseph Ellis-Monaghan , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Steven Howard Voldman
IPC分类号： H01L23/62
CPC分类号： H01L27/0248 , Y10S438/926
摘要： A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.
摘要翻译：用于在集成电路制造期间耗散电荷的结构。该结构包括：半导体衬底中的衬底接触; 衬底上的一个或多个布线层; 一个或多个导电电荷耗散结构，其从所述一个或多个布线层的最上层布线层的顶表面延伸通过所述一个或多个布线层的每个下布线层与所述基板接触电接触; 以及在基板中和在一个或多个布线层中的电路结构，电荷耗散结构在电路结构之间分散的一个或多个电荷耗散结构不会电接触任何一个或多个布线层中的任何一个电路结构。

6. 发明申请

US20080265422A1 STRUCTURE FOR CHARGE DISSIPATION DURING FABRICATION OF INTEGRATED CIRCUITS AND ISOLATION THEREOF 有权
标题翻译：集成电路制造过程中的充电结构及其隔离结构
公开(公告)号：US20080265422A1
公开(公告)日：2008-10-30
申请号：US12166362
申请日：2008-07-02
申请人： John Joseph Ellis-Monaghan , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Steven Howard Voldman
发明人： John Joseph Ellis-Monaghan , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Steven Howard Voldman
IPC分类号： H01L23/48
CPC分类号： H01L27/0248 , Y10S438/926
摘要： A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.
摘要翻译：用于在集成电路制造期间耗散电荷的结构。该结构包括：半导体衬底中的衬底接触; 衬底上的一个或多个布线层; 一个或多个导电电荷耗散结构，其从所述一个或多个布线层的最上层布线层的顶表面延伸通过所述一个或多个布线层的每个下布线层与所述基板接触电接触; 以及在基板中和在一个或多个布线层中的电路结构，电荷耗散结构在电路结构之间分散的一个或多个电荷耗散结构不会电接触任何一个或多个布线层中的任何一个电路结构。

7. 发明申请

US20130008699A1 BALL-LIMITING-METALLURGY LAYERS IN SOLDER BALL STRUCTURES 失效
标题翻译：焊接球结构中的限流金属层
公开(公告)号：US20130008699A1
公开(公告)日：2013-01-10
申请号：US13615826
申请日：2012-09-14
申请人： Charles L. Arvin , Timothy Harrison Daubenspeck , Wolfgang Sauter , Timothy Dooling Sullivan
发明人： Charles L. Arvin , Timothy Harrison Daubenspeck , Wolfgang Sauter , Timothy Dooling Sullivan
IPC分类号： H05K1/11 , H05K1/09 , H05K1/03
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/12 , H01L24/94 , H01L2224/03912 , H01L2224/0401 , H01L2224/05557 , H01L2224/05558 , H01L2224/05559 , H01L2224/1147 , H01L2224/13006 , H01L2224/13017 , H01L2224/13022 , H01L2224/13099 , H01L2224/274 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/00012
摘要： A structure. The structure includes: a first dielectric layer which includes a top dielectric surface; an electrically conductive line on the first dielectric layer; a second dielectric layer on the first dielectric layer and the electrically conductive line; a ball-limiting-metallurgy (BLM) region on the second dielectric layer and the electrically conductive line such that the BLM region is electrically connected to the electrically conductive line; and a solder ball on the BLM region. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface and is entirely in the BLM region does not exceed a pre-specified maximum value, wherein the pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface.
摘要翻译：一个结构。该结构包括：第一电介质层，其包括顶部电介质表面; 在所述第一电介质层上的导电线; 在所述第一电介质层和所述导电线上的第二电介质层; 所述第二电介质层和所述导电线上的限界冶金（BLM）区域使得所述BLM区电连接到所述导电线; 和BLM区域上的焊球。 BLM区域的特征在于，平行于顶部电介质表面并且完全在BLM区域中的最长直线段的长度不超过预定的最大值，其中预定的最大值最多为 BLM区域的最大水平尺寸的一半在平行于顶部电介质表面的水平方向上测量。

8. 发明授权

US08299611B2 Ball-limiting-metallurgy layers in solder ball structures 有权
标题翻译：焊球结构中的限界冶金层
公开(公告)号：US08299611B2
公开(公告)日：2012-10-30
申请号：US12547540
申请日：2009-08-26
申请人： Charles L. Arvin , Timothy Harrison Daubenspeck , Wolfgang Sauter , Timothy Dooling Sullivan
发明人： Charles L. Arvin , Timothy Harrison Daubenspeck , Wolfgang Sauter , Timothy Dooling Sullivan
IPC分类号： H01L23/48
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/12 , H01L24/94 , H01L2224/03912 , H01L2224/0401 , H01L2224/05557 , H01L2224/05558 , H01L2224/05559 , H01L2224/1147 , H01L2224/13006 , H01L2224/13017 , H01L2224/13022 , H01L2224/13099 , H01L2224/274 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/00012
摘要： A solder ball structure and a method for forming the same. The structure includes (i) a first dielectric layer which includes a top dielectric surface, (ii) an electrically conductive line, (iii) a second dielectric layer, (iv) a ball-limiting-metallurgy (BLM) region, and (v) a solder ball. The BLM region is electrically connected to the electrically conductive line and the solder ball. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface of the first dielectric layer and is entirely in the BLM region does not exceed a pre-specified maximum value. The pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface of the first dielectric layer.
摘要翻译：焊球结构及其形成方法。该结构包括（i）第一介电层，其包括顶部电介质表面，（ii）导电线，（iii）第二介电层，（iv）球限制冶金（BLM）区域和（v ）焊球。 BLM区域电连接到导电线和焊球。 BLM区域具有与第一介电层的顶部电介质表面平行且完全在BLM区域中的最长直线段的长度不超过预定的最大值的特性。预定的最大值为平行于第一介电层的顶部电介质表面的水平方向上测量的BLM区域的最大水平尺寸的至多一半。

9. 发明申请

US20120199983A1 ENHANCED ELECTROMIGRATION RESISTANCE IN TSV STRUCTURE AND DESIGN 有权
标题翻译： TSV结构和设计中的增强电阻率
公开(公告)号：US20120199983A1
公开(公告)日：2012-08-09
申请号：US13397004
申请日：2012-02-15
申请人： Mukta G. Farooq , John A. Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
发明人： Mukta G. Farooq , John A. Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.
摘要翻译：这些实施例提供了一种用于减少包含硅通孔（TSV）的电路中的电迁移的方法以及用于TSV的所得新颖结构。通过半导体衬底形成TSV。 TSV的第一端连接到半导体衬底的器件侧上的第一金属化层。 TSV的第二端连接到半导体衬底的研磨侧的第二金属化层。在TSV的第一端和第一金属化层的交叉点的TSV的第一端上形成第一平坦边缘。在TSV的第二端和第二金属化层的交叉点的TSV的第二端上形成第二平坦边缘。在第一端的顶部放置金属接触网格，金属覆盖率低于百分之八十。

10. 发明申请

US20080203495A1 INTEGRATION CIRCUITS FOR REDUCING ELECTROMIGRATION EFFECT 失效
标题翻译：用于降低电气效应的集成电路
公开(公告)号：US20080203495A1
公开(公告)日：2008-08-28
申请号：US11680081
申请日：2007-02-28
申请人： Anthony Kendall Stamper , Timothy Dooling Sullivan , Ping-Chuan Wang
发明人： Anthony Kendall Stamper , Timothy Dooling Sullivan , Ping-Chuan Wang
IPC分类号： H01L29/772
CPC分类号： H01L23/5221 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) directly above the first source/drain region and (ii) electrically coupled to the first source/drain region through first contact regions and second contact regions, respectively. The first and second electrically conductive line segments (i) reside in a first interconnect layer of the integrated circuit and (ii) run in the reference direction. The IC further includes an electrically conductive line being (i) directly above the first source/drain region, (ii) electrically coupled to the first and second electrically conductive line segments through a first via and a second via, respectively, (iii) resides in a second interconnect layer of the integrated circuit, and (iv) runs in the reference direction.
摘要翻译：一种降低电迁移效应的集成电路。 IC包括具有第一和第二源/漏区的衬底和功率晶体管。 IC还包括第一，第二和第三导电线段，其直接在第一源极/漏极区域的上方，以及（ii）分别通过第一接触区域和第二接触区域电耦合到第一源极/漏极区域。第一和第二导电线段（i）驻留在集成电路的第一互连层中，并且（ii）沿参考方向延伸。 IC还包括导电线，其是（i）直接在第一源极/漏极区域上方，（ii）分别通过第一通孔和第二通孔电耦合到第一和第二导电线段，（iii）驻留在集成电路的第二互连层中，以及（iv）在参考方向上延伸。

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