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21. 发明申请

US20130346830A1 ANTIPODAL-MAPPING-BASED ENCODERS AND DECODERS 有权
标题翻译：基于映射映射的编码器和解码器
公开(公告)号：US20130346830A1
公开(公告)日：2013-12-26
申请号：US14002790
申请日：2011-03-04
申请人： Erik Ordentlich , Ron M. Roth
发明人： Erik Ordentlich , Ron M. Roth
IPC分类号： G06F11/10
CPC分类号： G06F11/1076 , G06F11/1048 , G11C13/0002 , G11C13/0007 , G11C13/0023
摘要： Examples of the present invention include an electronic-memory-system component. The electronic-memory-system component includes an array of data-storage elements and an encoder that receives input data, processes the input data as a two-dimensional array of bits by carrying out two passes, in one pass subjecting a portion of each row of the two-dimensional array of bits having more than a threshold weight to a first weight-reduction operation, and, in another pass, subjecting a portion of each considered column of the two-dimensional array of bits having more than a threshold weight to a second weight-reduction operation, one of the first and second weight-reduction operations employing an antipodal mapping and the other of the first and second weight-reduction operations employing bit inversion, generates a codeword corresponding to the input data, and stores the codeword in the array of data-storage elements.
摘要翻译：本发明的实例包括电子存储系统组件。电子存储器系统部件包括数据存储元件阵列和接收输入数据的编码器，通过执行两遍来将输入数据作为二维阵列处理，在一次通过中对每一行进行一部分具有多于阈值权重的二维阵列阵列与第一加权减少运算相关联，并且在另一遍中，将具有多于阈值权重的二维阵列阵列的每个考虑的列的一部分经过第二加权减法操作中，使用对象映射的第一和第二减权操作之一，以及采用比特反转的第一和第二加权减少运算中的另一个产生与输入数据相对应的码字，并存储码字在数据存储元素阵列中。

22. 发明申请

US20120324140A1 CODING FOR CROSSBAR ARCHITECTURE 有权
标题翻译：交叉结构编码
公开(公告)号：US20120324140A1
公开(公告)日：2012-12-20
申请号：US13383644
申请日：2010-03-12
申请人： Erik Ordentlich , Ron M. Roth
发明人： Erik Ordentlich , Ron M. Roth
IPC分类号： H03M7/00 , G06F13/00
CPC分类号： G11C13/0002 , G11C2213/77
摘要： A method for encoding bits to be stored within a crossbar memory architecture performed by a physical computing system includes designating, with the physical computing system, a subset of crosspoints within a crossbar matrix, the crossbar matrix comprising a number of disjointed intersecting wire segments, the subset corresponding to a predetermined path through the crossbar matrix; and encoding, with the physical computing system, a number of data bits to be placed along the predetermined path; in which the encoding causes bits pertaining to at least one of the wire segments to be subject to a constraint when the data bits are placed along the predetermined path.
摘要翻译：用于对要存储在由物理计算系统执行的交叉开关存储器架构中的位进行编码的位的方法包括使用所述物理计算系统指定交叉矩阵内的交叉点的子集，所述交叉矩阵包括多个不相交的相交线段，子集对应于通过交叉矩阵的预定路径; 并且利用所述物理计算系统对沿着所述预定路径放置的多个数据位进行编码; 其中当沿着预定路径放置数据比特时，编码使得与至少一个线段有关的比特受到约束。

23. 发明申请

US20120017136A1 SYSTEMS AND METHODS FOR ENCODING INFORMATION FOR STORAGE IN AN ELECTRONIC MEMORY AND FOR DECODING ENCODED INFORMATION RETRIEVED FROM AN ELECTRONIC MEMORY 有权
标题翻译：用于编码电子存储器存储信息和解码从电子存储器检索的编码信息的系统和方法
公开(公告)号：US20120017136A1
公开(公告)日：2012-01-19
申请号：US12836405
申请日：2010-07-14
申请人： Erik Ordentlich , Ron M. Roth , Pascal Vontobel
发明人： Erik Ordentlich , Ron M. Roth , Pascal Vontobel
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1028 , G11C7/1006 , G11C13/0007 , G11C13/004 , G11C13/0069 , H03M13/13
摘要： Method and system embodiments of the present invention are directed to encoding information in ways that are compatible with constraints associated with electrical-resistance-based memories and useful in other, similarly constrained applications, and to decoding the encoded information. One embodiment of the present invention encodes k information bits and writes the encoded k information bits to an electronic memory, the method comprising systematically encoding the k information bits to produce a vector codeword, with additional parity bits so that the codeword is resilient to bit-transition errors that may occur during storage of the codeword in, and retrieval of the codeword from, the electronic memory, ensuring that the codeword does not violate a weight constraint, and writing the codeword to the electronic memory.
摘要翻译：本发明的方法和系统实施例涉及以与基于电阻的存储器相关联的约束兼容的方式对信息进行编码，并且在其他类似的约束应用中有用，并对编码的信息进行解码。本发明的一个实施例对k个信息比特进行编码，并将编码的k个信息比特写入电子存储器，该方法包括系统地编码k个信息比特以产生具有附加奇偶校验位的向量码字，可能在代码字存储期间发生的转换错误，以及从电子存储器检索码字，确保码字不违反权重约束，以及将码字写入电子存储器。

24. 发明授权

US06188335B1 Method and apparatus having cascaded decoding for multiple runlength-limited channel codes 失效
标题翻译：具有用于多个游程限制信道码的级联解码的方法和装置
公开(公告)号：US06188335B1
公开(公告)日：2001-02-13
申请号：US09136188
申请日：1998-08-19
申请人： Ron M. Roth , Josh N. Hogan , Gitit Ruckenstein
发明人： Ron M. Roth , Josh N. Hogan , Gitit Ruckenstein
IPC分类号： H03M700
CPC分类号： G11B20/10 , G11B20/18 , H03M7/00 , H03M13/31
摘要： Two different (d,k)-RLL codes can be used in systems such as erasable and writable dense optical disks. This is because it is typically possible to make readers capable of reading information written at a higher resolution (by a short wavelength authoring system) than the resolution that can be written by a consumer writer (using a laser of the same or longer wavelength as the reader). For one embodiment, two different decoders are used to decode the data. Alternately, we present an encoding scheme which operates with a single decoder. In one case, q1=q2 (and as a result p1
摘要翻译：两个不同的（d，k）-RLL码可以用在诸如可擦除和可写密集光盘的系统中。这是因为通常可以使阅读器能够读取以较高分辨率（通过短波长创作系统）写入的信息，而不是消费者作者可以写出的分辨率（使用相同或更长波长的激光）读者）。对于一个实施例，使用两个不同的解码器对数据进行解码。或者，我们提出一种使用单个解码器进行操作的编码方案。在一种情况下，q1 = q2（并且作为结果p1

25. 发明授权

US6002718A Method and apparatus for generating runlength-limited coding with DC control 失效
标题翻译：用于通过DC控制产生游程限制编码的方法和装置
公开(公告)号：US6002718A
公开(公告)日：1999-12-14
申请号：US549377
申请日：1995-10-27
申请人： Ron M. Roth
发明人： Ron M. Roth
IPC分类号： H03M7/14 , G11B20/14 , H03M5/14 , H04L25/34 , H04B1/66
CPC分类号： H03M5/145 , G11B20/1426
摘要： The present invention provides a lossless coding scheme that maps unconstrained binary sequences into sequences that obey the (d,k)-RLL constraint while offering a degree of DC control. In the preferred embodiment, the channel encoder is a state machine which uses a single "overlapping" table for all states rather than using multiple tables. Recognizing that a subset of codewords in a first state x.sub.i are identical to a subset of codewords in the second state x.sub.j, the overlapping encoding table uses identical addresses for the subset of identical codewords in the first and second state. Thus addresses for more than one state may point to a single codeword. A number of input bytes can be encoded into two different codewords which have different parity of ones, thus allowing for DC control. Decoding is carried out in a state-independent manner.
摘要翻译：本发明提供一种无损编码方案，其将无约束二进制序列映射到遵循（d，k）-RLL约束的序列，同时提供一定程度的DC控制。在优选实施例中，信道编码器是对所有状态使用单个“重叠”表而不是使用多个表的状态机。认识到第一状态xi中的码字的子集与第二状态xj中的码字的子集相同，所以重叠编码表对于第一和第二状态中相同码字的子集使用相同的地址。因此，多于一个状态的地址可以指向单个码字。可以将多个输入字节编码为具有不同奇偶校验位的两个不同码字，从而允许DC控制。解码以状态独立的方式进行。

26. 发明授权

US08887026B2 Efficient detection of errors in associative memory 有权
标题翻译：有效检测关联存储器中的错误
公开(公告)号：US08887026B2
公开(公告)日：2014-11-11
申请号：US13258457
申请日：2010-04-12
申请人： Anat Bremler-Barr , David Hay , Danny Hendler , Ron M. Roth
发明人： Anat Bremler-Barr , David Hay , Danny Hendler , Ron M. Roth
IPC分类号： G11C29/00 , G11C15/00 , G06F11/10 , G11C29/08
CPC分类号： G11C15/00 , G06F11/1008 , G06F11/1064 , G11C29/08
摘要： A method for error detection includes storing in an associative memory multiple data entries, each data entry including a data item together with one or more check symbols computed with respect to the data item. A predetermined sequence of search keys is applied to the memory, thereby causing the memory to generate, in parallel, match results with respect to the data entries. The match results are processed in order to identify an error in at least one of the data entries.
摘要翻译：一种用于错误检测的方法包括：在联想存储器中存储多个数据条目，每个数据条目包括数据项以及相对于数据项计算的一个或多个检验符号。将预定的搜索关键序列应用于存储器，从而使得存储器并行地生成相对于数据条目的匹配结果。处理匹配结果以便识别至少一个数据条目中的错误。

27. 发明申请

US20100299575A1 METHOD AND SYSTEM FOR DETECTION AND CORRECTION OF PHASED-BURST ERRORS, ERASURES, SYMBOL ERRORS, AND BIT ERRORS IN A RECEIVED SYMBOL STRING 审中-公开
标题翻译：用于检测和校正接收符号错误的方法和系统，接收到的符号字符中的错误，符号错误和位错误
公开(公告)号：US20100299575A1
公开(公告)日：2010-11-25
申请号：US12864233
申请日：2008-03-03
申请人： Ron M. Roth , Pascal O. Vontobel
发明人： Ron M. Roth , Pascal O. Vontobel
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： G11C7/1006 , G11C2029/0411 , H03M13/134 , H03M13/154 , H03M13/17 , H03M13/2906
摘要： Embodiments of the present invention include ECC-based encoding-and-decoding schemes that are well suited for correcting phased bursts of errors or erasures as well as additional symbol errors and bit errors. Each encoding-and-decoding scheme that represents an embodiment of the present invention is constructed from two or more component error-correcting codes and a mapping function ƒ(). The composite error-correcting codes that represent embodiments of the present invention can correct longer phased bursts or a greater number of erasures in addition to single-bit errors and symbol errors, respectively, than either of the component codes alone, and are more efficient than previously developed ECC-based encoding-and-decoding schemes for correcting phased bursts of symbol errors and erasures combined with additional bit errors and symbol errors.
摘要翻译：本发明的实施例包括基于ECC的编码和解码方案，其非常适合于校正相位的错误或擦除脉冲串以及附加符号错误和位错误。代表本发明实施例的每个编码和解码方案由两个或多个分量纠错码和映射函数ƒ（）构成。代表本发明实施例的复合纠错码可分别比单独的任何一个代码代码单独地纠正比单位错误和符号错误更长的相位脉冲串或更大数量的擦除，并且比先前开发的基于ECC的编码和解码方案用于校正符号错误和擦除的相位突发以及附加位错误和符号错误。

28. 发明申请

US20100091662A1 Defect-tolerant demultiplexers based on threshold logic 有权
标题翻译：基于阈值逻辑的容错解复用器
公开(公告)号：US20100091662A1
公开(公告)日：2010-04-15
申请号：US12288035
申请日：2008-10-15
申请人： Ron M. Roth , Joseph Warren Robinett , Philip J. Kuekes , R. Stanley Williams
发明人： Ron M. Roth , Joseph Warren Robinett , Philip J. Kuekes , R. Stanley Williams
IPC分类号： H04J3/14
CPC分类号： H04J3/047 , H03K17/002 , H03K19/0021 , H03K19/003
摘要： Embodiments of the present invention include defect-tolerant demultiplexer crossbars that employ, or that can be modeled by demultiplexer crossbars that employ, threshold logic “TL” elements. The threshold-logic elements provide for tolerance for signal variation on internal signals lines of a defect-tolerant demultiplexer crossbar, and thus tolerance for defects which produce internal signal variation.
摘要翻译：本发明的实施例包括采用阈值逻辑“TL”元素的采用或可以通过解复用器交叉开关建模的缺陷容许解复用器交叉开关。阈值逻辑元件提供了对于容错解复用器交叉开关的内部信号线上的信号变化的容限，并因此提供产生内部信号变化的缺陷的容限。

29. 发明授权

US5351246A Method and means for coding and rebuilding that data contents of unavailable DASDs or rebuilding the contents of DASDs in error in the presence of reduced number of unavailable DASDs in a DASD array 失效
标题翻译：在DASD阵列中存在减少数量不可用的DASD的情况下，编码和重建不可用DASD的数据内容或重建DASD内容的方法和手段是错误的
公开(公告)号：US5351246A
公开(公告)日：1994-09-27
申请号：US177633
申请日：1994-01-03
申请人： Miguel M. Blaum , Ron M. Roth
发明人： Miguel M. Blaum , Ron M. Roth
IPC分类号： G06F11/10 , G06F11/20 , G11B20/18 , G11C29/00 , H03M13/09 , H03M13/11 , G06F11/00
CPC分类号： H03M13/098 , G06F11/1092 , G11B20/1833 , G11C29/88 , H03M13/11 , H03M13/2918 , H03M13/2921
摘要： A method and means for coding an (M-1).times.M data array written onto an array of M synchronous recording paths and for rebuilding and writing onto spare recording path capacity when up to a preselected number R of array DASDs fail, or one DASD becomes erroneous and up to R-2 fail. Data is mapped into the parallel paths using an (M-1).times.M data and parity block array as the storage model where M is a prime number and each block extent is uniform and at least one bit in length. The (M-1).times.M data and parity block array is encoded to include zero XOR sums along a traverses of slopes 0, 1, 2, . . . , P-1, extended cyclically over said data array. Rebuilding data and parity blocks is occasioned upon unavailability of no more than R less than or equal to P recording path failures, or one recording path in error and up to R-2 recording path failures. This includes calculating XOR-sums along the traversed paths of P-1 slopes, cyclic and linear shifts and XOR operations, recovering the unavailable DASDs by means of iterative solution of a set of recursions, and finally writing the rebuilt array back to onto M recording paths inclusive of any spare paths.
摘要翻译：编写在M个同步记录路径阵列上的（M-1）个xM数据阵列的编码方法和装置，并且当直到阵列DASD的预选数量R失败时，用于重建和写入备用记录路径容量，或者一个DASD变为错误的，直到R-2失败。使用（M-1）xM数据和奇偶校验块阵列将数据映射到并行路径中作为存储模型，其中M是素数，并且每个块范围是均匀的并且至少一个位长。（M-1）xM数据和奇偶校验块阵列被编码为沿着斜率0,1,2的遍历包括零XOR和。。。，P-1，循环延伸超过所述数据阵列。重建数据和奇偶校验块是由于R不小于或等于P记录路径故障或一个错误记录路径以及高达R-2记录路径故障的R不足而产生的。这包括沿着P-1斜率的遍历路径计算XOR和，循环和线性移位和XOR运算，通过一组递归的迭代解来恢复不可用的DASD，最后将重建的阵列写回M记录包括任何备用路径的路径。

30. 发明授权

US07489583B2 Constant-weight-code-based addressing of nanoscale and mixed microscale/nanoscale arrays 有权
标题翻译：纳米尺度和混合微米级/纳米尺寸阵列的基于恒权重代码的寻址
公开(公告)号：US07489583B2
公开(公告)日：2009-02-10
申请号：US11221036
申请日：2005-09-06
申请人： Philip J. Kuekes , J. Warren Roblnett , Ron M. Roth , Gadlel Seroussl , Gregory S. Smider , R. Stanley Williams
发明人： Philip J. Kuekes , J. Warren Roblnett , Ron M. Roth , Gadlel Seroussl , Gregory S. Smider , R. Stanley Williams
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , B82Y10/00 , G11C13/00 , G11C13/0023 , G11C13/0069 , G11C2013/009 , G11C2213/77 , G11C2213/81
摘要： Various embodiments of the present invention include methods for determining nanowire addressing schemes and include microscale/nanoscale electronic devices that incorporate the nanowire addressing schemes for reliably addressing nanowire-junctions within nanowire crossbars. The addressing schemes allow for change in the resistance state, or other physical or electronic state, of a selected nanowire-crossbar junction without changing the resistance state, or other physical or electronic state, of the remaining nanowire-crossbar junctions, and without destruction of either the selected nanowire-crossbar junction or the remaining, non-selected nanowire-crossbar junctions. Additional embodiments of the present invention include nanoscale memory arrays and other nanoscale electronic devices that incorporate the nanowire-addressing-scheme embodiments of the present invention. Certain of the embodiments of the present invention employ constant-weight codes, a well-known class of error-control-encoding codes, as addressed-nanowire selection voltages applied to microscale output signal lines of microscale/nanoscale encoder-demultiplexers that are selectively interconnected with a set of nanowires.
摘要翻译：本发明的各种实施例包括用于确定纳米线寻址方案的方法，并且包括微纳米级纳米级电子器件，其纳入用于在纳米线交叉管内可靠地寻址纳米线结的纳米线寻址方案。寻址方案允许选择的纳米线 - 交叉连接点的电阻状态或其他物理或电子状态的改变，而不改变剩余的纳米线 - 交叉连接点的电阻状态或其他物理或电子状态，并且不破坏选择的纳米线 - 交叉结或剩余的未选择的纳米线交叉点结。本发明的另外的实施例包括结合本发明的纳米线寻址方案实施例的纳米级存储器阵列和其它纳米级电子器件。本发明的某些实施例采用常规权重代码，众所周知的错误控制编码代码，作为施加到微尺度/纳米级编码器 - 解复用器的微量输出信号线上的寻址纳米线选择电压，其被选择性地互连与一套纳米线。

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