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21. 发明授权

US06368950B1 Silicide gate transistors 有权
标题翻译：硅化物栅极晶体管
公开(公告)号：US06368950B1
公开(公告)日：2002-04-09
申请号：US09734186
申请日：2000-12-12
申请人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L213205
CPC分类号： H01L29/66545 , H01L21/28097
摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying metal to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The silicon is removed except for the portion of the silicon in the recess. The remaining portions of the metal are removed by manipulating the etch selectivity between the metal and the self-aligned metal silicide gate.
摘要翻译：实现自对准金属硅化物栅极的方法是通过将非晶硅限制在覆盖沟道的凹槽中并退火以使非晶硅与其上覆金属相互作用以形成自对准金属硅化物栅极来实现的。在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。除了凹部中硅的部分之外，除去硅。通过操纵金属和自对准金属硅化物栅之间的蚀刻选择性来去除金属的剩余部分。

22. 发明授权

US06342414B1 Damascene NiSi metal gate high-k transistor 有权
标题翻译：大马士革NiSi金属栅极高k晶体管
公开(公告)号：US06342414B1
公开(公告)日：2002-01-29
申请号：US09734189
申请日：2000-12-12
申请人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L218238
CPC分类号： H01L21/28194 , H01L21/28097 , H01L21/28114 , H01L29/495 , H01L29/4975 , H01L29/51 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining a low temperature silicidation metal within a recess overlying a channel and annealing to cause the low temperature silicidation metal and its overlying silicon to interact to form the self-aligned low temperature metal silicide gate. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.
摘要翻译：实现自对准低温金属硅化物栅极的方法是通过将低温硅化金属限制在覆盖沟道的凹槽内并进行退火以使低温硅化金属及其上覆的硅相互作用以形成自对准低温度金属硅化物门。进行平面化步骤以通过化学机械抛光除去剩余的未反应的硅，直到没有检测到硅。

23. 发明授权

US06784506B2 Silicide process using high K-dielectrics 失效
标题翻译：使用高K电介质的硅化物工艺
公开(公告)号：US06784506B2
公开(公告)日：2004-08-31
申请号：US09939744
申请日：2001-08-28
申请人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L2976
CPC分类号： H01L29/4933 , H01L21/28167 , H01L21/28194 , H01L29/517 , H01L29/518 , H01L29/665
摘要： A method for preventing the thermal decomposition of a high-K dielectric layer of a gate electrode during the formation of a metal silicide on the gate electrode by using nickel as the metal component of the silicide.
摘要翻译：通过使用镍作为硅化物的金属成分，在栅电极形成金属硅化物期间防止栅电极的高K电介质层的热分解的方法。

24. 发明授权

US06475874B2 Damascene NiSi metal gate high-k transistor 有权
标题翻译：大马士革NiSi金属栅极高k晶体管
公开(公告)号：US06475874B2
公开(公告)日：2002-11-05
申请号：US09731031
申请日：2000-12-07
申请人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L2120
CPC分类号： H01L21/28194 , H01L21/28097 , H01L29/495 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying low temperature silicidation metal to interact to form the self-aligned low temperature metal silicide gate. A precursor having a temporary gate is used to form the self-aligned low temperature silicide gate. The remaining portions of the low temperature silicidation metal is removed by manipulating the etch selectivity between the low temperature silicidation metal and the self-aligned low temperature metal silicide gate.
摘要翻译：实现自对准低温金属硅化物栅极的方法是通过将非晶硅限制在覆盖沟道的凹槽中并退火以使非晶硅与其上覆的低温硅化金属相互作用以形成自对准的低温金属来实现的硅化物门使用具有临时栅极的前体形成自对准低温硅化物栅极。通过操纵低温硅化金属和自对准的低温金属硅化物栅极之间的蚀刻选择性来除去低温硅化金属的剩余部分。

25. 发明授权

US06465334B1 Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors 有权
标题翻译：用于嵌入栅极MOS晶体管的电介质前体材料的增强的无电沉积
公开(公告)号：US06465334B1
公开(公告)日：2002-10-15
申请号：US09679369
申请日：2000-10-05
申请人： Matthew S. Buynoski , Paul R. Besser , Paul L. King , Eric N. Paton , Qi Xiang
发明人： Matthew S. Buynoski , Paul R. Besser , Paul L. King , Eric N. Paton , Qi Xiang
IPC分类号： H01L214763
CPC分类号： H01L21/28194 , H01L21/288 , H01L21/31683 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/66583
摘要： High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are fabricated by forming an ultra-thin catalytic metal layer, e.g., a monolayer thick layer of Pd or Pd, on a Si-based semiconductor substrate, electrolessly plating on the catalytic layer comprising at least one refractory or lanthanum series transition metal or metal-based dielectric precursor layer, such as of Zr and/or Hf, and then reacting the precursor layer with oxygen or with oxygen and the semiconductor substrate to form the at least one high-k metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.
摘要翻译：通过形成高质量的电介质层，例如由至少一种难熔或镧系列过渡金属氧化物或硅酸盐构成的高k电介质层，用作在叠层金属栅极MOS晶体管和CMOS器件中用作栅极绝缘体层超薄催化金属层，例如在Si基半导体衬底上的单层厚的Pd或Pd层，在包含至少一种难熔或镧系过渡金属或金属基电介质前体层的催化剂层上无电镀，例如Zr和/或Hf，然后使前体层与氧或与氧和半导体衬底反应以形成至少一种高k金属氧化物或硅酸盐。本发明的方法在至少形成栅极绝缘体层的初始阶段期间防止或至少基本上减少氧接触到衬底表面，从而最小化半导体衬底/栅极处的氧诱导表面状态的有害形成绝缘子接口。

26. 发明授权

US06458679B1 Method of making silicide stop layer in a damascene semiconductor structure 有权
标题翻译：在大马士革半导体结构中制造硅化物阻挡层的方法
公开(公告)号：US06458679B1
公开(公告)日：2002-10-01
申请号：US09780454
申请日：2001-02-12
申请人： Eric N. Paton , Paul R. Besser , Matthew S. Buynoski , Qi Xiang , Paul L. King , John Clayton Foster
发明人： Eric N. Paton , Paul R. Besser , Matthew S. Buynoski , Qi Xiang , Paul L. King , John Clayton Foster
IPC分类号： H01L213205
CPC分类号： H01L29/66583 , H01L21/28052 , H01L29/4941
摘要： A damascene gate semiconductor structure that is formed utilizing a silicide stop layer. Initially, a gate opening is provided in an insulating layer on a substrate. A first dielectric layer is deposited in the gate opening over the substrate. A silicide stop layer is then deposited in the gate opening over the first silicon layer. A second silicon layer is then deposited in the gate opening over the silicide stop layer. A metal or alloy layer is then deposited over the insulating and the second silicon layer. The damascene semiconductor structure is then temperature treated to react the metal or alloy layer with the second silicon layer to form a silicide layer. Any unreated metal or alloy is then removed from the metal or alloy layer.
摘要翻译：利用硅化物停止层形成的镶嵌栅极半导体结构。首先，在基板上的绝缘层中设置栅极开口。第一介电层沉积在衬底上的栅极开口中。然后在第一硅层上的栅极开口中沉积硅化物阻挡层。然后在硅化物停止层上的栅极开口中沉积第二硅层。然后在绝缘层和第二硅层上沉积金属或合金层。然后对镶嵌半导体结构进行温度处理以使金属或合金层与第二硅层反应形成硅化物层。然后从金属或合金层中除去任何未反应的金属或合金。

27. 发明授权

US07071065B1 Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication 有权
标题翻译：具有硅锗源/漏扩展的应变硅PMOS及其制造方法
公开(公告)号：US07071065B1
公开(公告)日：2006-07-04
申请号：US10738716
申请日：2003-12-17
申请人： Qi Xiang , Eric N. Paton , Haihong Wang
发明人： Qi Xiang , Eric N. Paton , Haihong Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L29/1054 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/66916 , H01L29/7842 , H01L29/7848 , H01L29/802 , Y10S438/933
摘要： A strained silicon p-type MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon germanium regions are formed on the silicon germanium layer adjacent to ends of the strained silicon channel region, and shallow source and drain extensions are implanted in the silicon germanium material. The shallow source and drain extensions do not extend into the strained silicon channel region. By forming the source and drain extensions in silicon germanium material rather than in silicon, source and drain extension distortions caused by the enhanced diffusion rate of boron in silicon are avoided.
摘要翻译：应变硅p型MOSFET利用形成在硅锗衬底上的应变硅沟道区。在邻近于应变硅沟道区的端部的硅锗层上形成硅锗区，并且在硅锗材料中注入浅的源极和漏极延伸。浅源极和漏极延伸部分不延伸到应变硅沟道区域。通过在硅锗材料而不是在硅中形成源极和漏极延伸，避免了由硅中的增强的扩散速率引起的源极和漏极扩展失真。

28. 发明授权

US06905923B1 Offset spacer process for forming N-type transistors 有权
标题翻译：用于形成N型晶体管的偏置间隔工艺
公开(公告)号：US06905923B1
公开(公告)日：2005-06-14
申请号：US10619877
申请日：2003-07-15
申请人： Eric N. Paton , Haihong Wang , Qi Xiang
发明人： Eric N. Paton , Haihong Wang , Qi Xiang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823864
摘要： A method of fabricating an SMOS integrated circuit with source and drain junctions utilizes an offset gate spacer for N-type transistors. Ions are implanted to form the source and drain regions in a strained layer. The offset spacer reduces problems associated with Arsenic (As) diffusion on strained semiconductor layers. The process can be utilized for SMOS metal oxide semiconductor field effect transistors (MOSFETs). The strained layer can be a strained silicon layer formed above a germanium layer.
摘要翻译：制造具有源极和漏极结的SMOS集成电路的方法利用用于N型晶体管的偏移栅极间隔物。植入离子以形成应变层中的源区和漏区。偏移间隔物减少了在应变半导体层上与砷（As）扩散相关的问题。该工艺可用于SMOS金属氧化物半导体场效应晶体管（MOSFET）。应变层可以是形成在锗层之上的应变硅层。

29. 发明授权

US06703648B1 Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication 有权
标题翻译：具有硅锗源/漏扩展的应变硅PMOS及其制造方法
公开(公告)号：US06703648B1
公开(公告)日：2004-03-09
申请号：US10282559
申请日：2002-10-29
申请人： Qi Xiang , Eric N. Paton , Haihong Wang
发明人： Qi Xiang , Eric N. Paton , Haihong Wang
IPC分类号： H01L2904
CPC分类号： H01L29/6656 , H01L29/1054 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/66916 , H01L29/7842 , H01L29/7848 , H01L29/802 , Y10S438/933
摘要： A strained silicon p-type MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon germanium regions are formed to the silicon germanium layer adjacent to ends of the strained silicon channel region, and shallow source and drain extensions are implanted in the silicon germanium material. The shallow source and drain extensions do not extend into the strained silicon channel region. By forming the source and drain extensions in silicon germanium material rather than in silicon, source and drain extension distortions caused by the enhanced diffusion rate of boron in silicon are avoided.
摘要翻译：应变硅p型MOSFET利用形成在硅锗衬底上的应变硅沟道区。硅锗区形成在邻近于应变硅沟道区的端部的硅锗层上，并且浅的源极和漏极延伸部被注入到硅锗材料中。浅源极和漏极延伸部分不延伸到应变硅沟道区域。通过在硅锗材料而不是在硅中形成源极和漏极延伸，避免了由硅中的增强的扩散速率引起的源极和漏极扩展失真。

30. 发明授权

US06921709B1 Front side seal to prevent germanium outgassing 失效
标题翻译：前侧密封防止锗脱气
公开(公告)号：US06921709B1
公开(公告)日：2005-07-26
申请号：US10620194
申请日：2003-07-15
申请人： Eric N. Paton , Haihong Wang , Qi Xiang
发明人： Eric N. Paton , Haihong Wang , Qi Xiang
IPC分类号： H01L21/265 , H01L21/336 , H01L21/84 , H01L29/10
CPC分类号： H01L21/84 , H01L21/2652 , H01L29/1054 , H01L29/665 , H01L29/6659 , H01L29/7842 , Y10S438/923 , Y10S438/933
摘要： A method of manufacturing an integrated circuit having a gate structure above a substrate that includes germanium utilizes at least one layer as a seal. The layer advantageously can prevent back sputtering and outdiffusion. A transistor can be formed in the substrate by doping through the layer. Another layer can be provided below the first layer. Layers of silicon dioxide, silicon carbide, silicon nitride, titanium, titanium nitride, titanium/titanium nitride, tantalum nitride, and silicon carbide can be used.
摘要翻译：制造具有在包括锗的衬底之上的栅极结构的集成电路的方法利用至少一层作为密封。该层有利地可以防止反溅射和扩散。可以通过掺杂通过层在衬底中形成晶体管。可以在第一层下面提供另一层。可以使用二氧化硅，碳化硅，氮化硅，钛，氮化钛，钛/氮化钛，氮化钽和碳化硅的层。

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