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21. 发明申请

US20090249175A1 Single Event Upset error detection within sequential storage circuitry of an integrated circuit 有权
标题翻译：单次事件在集成电路的顺序存储电路内的错误检测
公开(公告)号：US20090249175A1
公开(公告)日：2009-10-01
申请号：US12078189
申请日：2008-03-27
申请人： Vikas Chandra , Sachin Satish Idgunji
发明人： Vikas Chandra , Sachin Satish Idgunji
IPC分类号： H04L1/00 , G06F11/07
CPC分类号： G06F11/00
摘要： Sequential storage circuitry for a integrated circuit is provided, comprising a first storage element, a second storage element and an additional storage element. The first storage element stores, during a first phase of a clock signal, a first indication of an input data value received by the sequential storage circuitry. The second storage element is coupled to an output of the first storage element, and stores a second indication of the input data value during a second phase of the clock signal. The additional storage element is driven by a pulse signal derived from the clock signal, and is arranged on occurrence of that pulse signal to store a third indication of the input data value. Error detection circuitry is then provided for detecting a single event upset error in either the first storage element or the second storage element. In particular, during the first phase of the clock signal, the error detection circuitry detects the single event upset error in the first storage element if there is a difference in the input data value as indicated by the first indication and the third indication. Further, during the second phase of the clock signal, the error detection circuitry detects a single event upset error in the second storage element if there is a difference in the input data value as indicated by the second indication and the third indication. Such an arrangement provides a simple mechanism for detecting soft errors in both the first storage element and the second storage element using only one additional storage element.
摘要翻译：提供了一种用于集成电路的顺序存储电路，包括第一存储元件，第二存储元件和附加存储元件。第一存储元件在时钟信号的第一阶段存储由顺序存储电路接收的输入数据值的第一指示。第二存储元件耦合到第一存储元件的输出，并且在时钟信号的第二阶段期间存储输入数据值的第二指示。附加存储元件由从时钟信号导出的脉冲信号驱动，并且被布置为发生该脉冲信号以存储输入数据值的第三指示。然后提供错误检测电路用于检测第一存储元件或第二存储元件中的单个事件镦锻错误。特别地，在时钟信号的第一阶段期间，如果由第一指示和第三指示所指示的输入数据值存在差异，则错误检测电路检测第一存储元件中的单事件翻转错误。此外，在时钟信号的第二阶段期间，如果由第二指示和第三指示所指示的输入数据值存在差异，则错误检测电路检测第二存储元件中的单个事件不正常错误。这种布置提供了使用仅一个附加存储元件来检测第一存储元件和第二存储元件中的软错误的简单机制。

22. 发明申请

US20090245013A1 Sequential storage circuitry for an integrated circuit 有权
标题翻译：用于集成电路的顺序存储电路
公开(公告)号：US20090245013A1
公开(公告)日：2009-10-01
申请号：US12078192
申请日：2008-03-27
申请人： Vikas Chandra , Sachin Satish Idgunji
发明人： Vikas Chandra , Sachin Satish Idgunji
IPC分类号： G11C8/00
CPC分类号： G11C8/04
摘要： Sequential storage circuitry is provided for an integrated circuit, comprising input circuitry, a storage structure, and output circuitry. The input circuitry receives an input data value to the sequential storage circuitry, and generates an internal data value. The input circuitry receives a first control signal which when asserted causes it to generate as the internal data value an inverted version of the input data value, and which when not asserted causes the input circuitry to generate as the internal data value the input data value. The storage structure then stores an indication of the internal data value. The output circuitry generates, from the indication of the internal data value stored in the storage structure, an output data value for outputting from the sequential storage circuitry. More particularly, the output circuitry receives a second control signal derived from the first control signal, which causes the output circuitry to generate as said output data value an inverted version of the internal data value in the event that the input circuitry generated as the internal data value an inverted version of the input data value, and otherwise generates as the output data value the internal data value. Such a mechanism provides a simple and effective technique for annealing stress build-up within the storage structure, as for example may arise as a result of the NBTI phenomenon. The technique of the present invention can be also be used for other purposes, for example to improve security of the data held within such a sequential storage circuitry.
摘要翻译：为集成电路提供顺序存储电路，包括输入电路，存储结构和输出电路。输入电路接收到顺序存储电路的输入数据值，并产生内部数据值。输入电路接收第一控制信号，当被断言使得其产生作为内部数据值的输入数据值的反转版本，并且当不被确定时，使输入电路作为内部数据值生成输入数据值。存储结构然后存储内部数据值的指示。输出电路从存储在存储结构中的内部数据值的指示产生用于从顺序存储电路输出的输出数据值。更具体地，输出电路接收从第一控制信号导出的第二控制信号，其使得输出电路在作为内部数据产生的输入电路的情况下产生作为所述输出数据值的内部数据值的反转版本为输入数据值的反转版本赋值，否则生成内部数据值作为输出数据值。这种机制提供了一种用于在存储结构内退火应力累积的简单有效的技术，例如可能由于NBTI现象而产生。本发明的技术也可以用于其它目的，例如提高在这种顺序存储电路中保存的数据的安全性。

23. 发明申请

US20080272809A1 Integrated circuit power-on control and programmable comparator 有权
标题翻译：集成电路开机控制和可编程比较器
公开(公告)号：US20080272809A1
公开(公告)日：2008-11-06
申请号：US11797498
申请日：2007-05-03
申请人： Sachin Satish Idgunji , David Walter Flynn , David William Howard , Robert Campbell Aitken
发明人： Sachin Satish Idgunji , David Walter Flynn , David William Howard , Robert Campbell Aitken
IPC分类号： H03K5/24
CPC分类号： H03K19/0016
摘要： An integrated circuit is provided with a main supply rail and a virtual supply rail connected by strong and weak header transistors. A power-on controller controls the switching on of the strong transistors after the virtual supply rail voltage has already been driven up to close to its operating level by the weak transistor. The power-on controller comprises a comparator monitoring a single reference voltage level with its output being latched within a latch and used to switch on the strong transistor. The comparator may be programmable to detect multiple different trigger voltage levels by using opposing charging and discharging transistors with one set of these operating in a saturated regime and the other in a regime in which the current therethrough varies in dependence upon the voltage being sensed. These opposing transistors can be used to charge or discharge a node with the state of that node being taken to generate the sensed output.
摘要翻译：集成电路设置有主供电轨和通过强和弱标头晶体管连接的虚拟电源轨。在虚拟电源电压已经被弱晶体管驱动到接近其工作电平之后，上电控制器控制强晶体管的导通。上电控制器包括监视单个参考电压电平的比较器，其输出被锁存在锁存器内并用于接通强晶体管。比较器可以被编程为通过使用相反的充电和放电晶体管来检测多个不同的触发电压电平，其中一组在饱和状态下工作，另一组在其中电流根据感测电压而变化。这些相对的晶体管可以用于对具有该节点的状态的节点进行充电或放电以产生感测的输出。

24. 发明申请

US20080272652A1 Virtual power rail modulation within an integrated circuit 有权
标题翻译：集成电路内的虚拟电源轨调制
公开(公告)号：US20080272652A1
公开(公告)日：2008-11-06
申请号：US11797497
申请日：2007-05-03
申请人： Sachin Satish Idgunji , David Walter Flynn , Robert Campbell Aitken
发明人： Sachin Satish Idgunji , David Walter Flynn , Robert Campbell Aitken
IPC分类号： H02J1/00
CPC分类号： H03K19/0016 , H03K19/096 , Y10T307/461
摘要： An integrated circuit 2 is provided with logic blocks 16 which draw their power from virtual supply rails 8, 10. These virtual supply rails 8, 10 are connected by switch blocks 12, 14 to main supply rails 4, 6. The switch blocks 12, 14 are subject to modulation to maintain the virtual supply rails 8, 10 at an intermediate voltage level such that a reduced voltage difference is applied across the logic block 16. This intermediate voltage level is used in a state retention mode in which the clock signal clk to the logic block 16 is stopped and state signal values are maintained therein using this reduced virtual power rail derived voltage difference. When it is desired to resume processing then the full virtual rail voltages are restored by rendering the switch blocks 12, 14 fully conductive and then the clock is restarted. The switch blocks 12, 14 which are modulated by controllers 18 which use feedback control based upon the sensed virtual rail voltages (VVdd and VVgnd) while drawing their own power from the normal supply rails (VVdd and gnd).
摘要翻译：集成电路2设置有从虚拟电源轨8,10吸取电力的逻辑块16.这些虚拟电源轨8,10由开关块12,14连接到主电源轨4,6。 14进行调制以将虚拟电源轨8,10保持在中间电压电平，使得在逻辑块16上施加减小的电压差。该中间电压电平用于状态保持模式，其中时钟信号clk 停止逻辑块16，并且使用该减小的虚拟功率轨导出电压差来维持状态信号值。当希望恢复处理时，通过使开关块12,14完全导通然后再启动时钟来恢复完整的虚拟轨电压。开关块12,14由控制器18调制，控制器18使用基于感测的虚拟轨电压（VV）和反馈控制电压（VV）的反馈控制，同时从正常的电源轨（VV＆lt; dd＆gt;和＆lt; SUB＆gt;＆gt;）。

25. 发明授权

US08717078B2 Sequential latching device with elements to increase hold times on the diagnostic data path 有权
标题翻译：具有元件的顺序锁定装置，以增加诊断数据路径上的保持时间
公开(公告)号：US08717078B2
公开(公告)日：2014-05-06
申请号：US13495362
申请日：2012-06-13
申请人： Sachin Satish Idgunji , Robert Campbell Aitken , Imran Iqbal
发明人： Sachin Satish Idgunji , Robert Campbell Aitken , Imran Iqbal
IPC分类号： H03K3/289
CPC分类号： H03K3/0375
摘要： A latching device includes input and output latching elements to receive and output data values wherein the input and output elements are configured to receive a first and second clocks, respectively. The clocks have the same frequency but are inverted. The elements are transparent and transmit data between an input and an output in response to the first value of a received clock and are opaque and hold the data value in response to a second value of the received clock, such that in response to the first and second clocks the input data value is clocked through the input and output elements to the output. The device includes a device for selecting an operational data value or a diagnostic data value for input to the input element in response to a value of a diagnostic enable signal indicating a functional mode or a diagnostic mode.
摘要翻译：锁存装置包括用于接收和输出数据值的输入和输出锁存元件，其中输入和输出元件分别被配置为接收第一和第二时钟。时钟频率相同但反相。这些元件是透明的，并且响应于接收时钟的第一值在输入和输出之间传输数据，并且是不透明的，并且响应于所接收的时钟的第二值保持数据值，使得响应于第一和第二个时钟，输入数据值通过输入和输出元件输出到输出。该装置包括用于响应于指示功能模式或诊断模式的诊断使能信号的值来选择用于输入到输入元件的操作数据值或诊断数据值的装置。

26. 发明授权

US08639960B2 Verifying state integrity in state retention circuits 有权
标题翻译：验证状态保持电路中的状态完整性
公开(公告)号：US08639960B2
公开(公告)日：2014-01-28
申请号：US13067396
申请日：2011-05-27
申请人： David Walter Flynn , Sachin Satish Idgunji
发明人： David Walter Flynn , Sachin Satish Idgunji
IPC分类号： G06F1/32
CPC分类号： G01R31/318541 , G01R31/318544 , G06F11/10
摘要： A data processing apparatus is provided comprising data processing circuitry configured to perform data processing operations. A plurality of state retention circuits forms part of the data processing circuitry and these circuits are configured to hold respective state values at respective nodes of the data processing circuitry it enters a low power mode. One or more scan paths connect the plurality of state retention circuits together in series, such that the state values may be scanned into and out of the respective nodes. A plurality of parity information generation elements are coupled to the scan path(s) and configured to generate parity information indicative of the respective state values held at those respective nodes by the state retention circuits. The plurality of parity information generation elements are arranged to provide one or more parity path(s), such that an output parity value generated at an output of the parity path will invert if one of said respective state values changes, providing an external indication of the integrity of the state values held by the state retention circuits.
摘要翻译：提供了一种数据处理装置，包括被配置为执行数据处理操作的数据处理电路。多个状态保持电路形成数据处理电路的一部分，并且这些电路被配置为保持其进入低功率模式的数据处理电路的各个节点处的各自的状态值。一个或多个扫描路径将多个状态保持电路串联在一起，使得可以将状态值扫描进出各个节点。多个奇偶校验信息生成元件耦合到扫描路径，并被配置为通过状态保持电路产生指示保持在那些相应节点处的各个状态值的奇偶校验信息。多个奇偶信息产生元件被布置成提供一个或多个奇偶校验路径，使得如果所述各个状态值之一改变，则在奇偶校验路径的输出处产生的输出奇偶校验值将反转，提供外部指示国家保留电路所持有的状态值的完整性。

27. 发明授权

US08582389B2 Write assist in a dual write line semiconductor memory 有权
标题翻译：在双写入半导体存储器中写入辅助
公开(公告)号：US08582389B2
公开(公告)日：2013-11-12
申请号：US13067629
申请日：2011-06-15
申请人： Hemangi Umakant Gajjewar , Sachin Satish Idgunji , Gus Yeung
发明人： Hemangi Umakant Gajjewar , Sachin Satish Idgunji , Gus Yeung
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C8/16 , G11C11/419
摘要： A semiconductor memory storage device with a plurality of storage cells, each cell includes two access control devices, each providing the cell with access to or isolation from a respective one of two data lines in response to an access control signal provided by access control circuitry. The control devices are controlled to provide the storage cell with access to or isolation from either of the first and second of the two data lines. The access control circuitry is responsive to a data access request, the data access request being a write request, to apply a data value to be written to both of the first and second data lines and to apply the access control signal to both of the first and second access control lines.
摘要翻译：一种具有多个存储单元的半导体存储器存储设备，每个单元包括两个访问控制设备，每个存储控制设备响应于由访问控制电路提供的访问控制信号，为每个单元提供对两个数据线中的相应一个的访问或隔离的单元。控制设备被控制以向存储单元提供对两条数据线中的第一和第二数据线中的任一条的访问或隔离。访问控制电路响应于数据访问请求，数据访问请求是写请求，以将要写入的数据值应用于第一和第二数据线，并将访问控制信号应用于第一和第二存取控制线。

28. 发明申请

US20120170390A1 Read stability of a semiconductor memory 有权
标题翻译：读取半导体存储器的稳定性
公开(公告)号：US20120170390A1
公开(公告)日：2012-07-05
申请号：US12929138
申请日：2011-01-03
申请人： Sachin Satish Idgunji , Hemangi Umakant Gajjewar , Vincent Phillipe Schuppe , Yew Keong Chong , Hsin-Yu Chen
发明人： Sachin Satish Idgunji , Hemangi Umakant Gajjewar , Vincent Phillipe Schuppe , Yew Keong Chong , Hsin-Yu Chen
IPC分类号： G11C7/22 , G06F17/50 , G11C7/12
CPC分类号： G11C7/222 , G11C8/08 , G11C8/10 , G11C8/16 , G11C11/41 , G11C11/412 , G11C11/413 , G11C11/418 , G11C11/419
摘要： A semiconductor memory storage device is disclosed. The memory comprises a plurality of storage cells for storing data each storage cell comprising an access control device for providing the storage cell with access to or isolation from a data access port in response to an access control signal, access control circuitry for transmitting the access control signal along an access control line to control a plurality of the access control devices connected to the access control line. The access control circuitry responds to a data access request signal by increasing a voltage level supplied to the access control line to a first voltage level at a first average rate and then in response to receipt of a further signal increasing the voltage level supplied to the access control line to the predetermined higher voltage level, in such a way that a further average rate of increase of the voltage level from the first to the predetermined higher voltage level is lower than the first average rate of increase to the first level.
摘要翻译：公开了一种半导体存储器存储装置。存储器包括用于存储数据的多个存储单元，每个存储单元包括访问控制设备，用于响应于访问控制信号向存储单元提供对数据访问端口的访问或与数据访问端口的隔离，存取控制电路用于发送访问控制信号沿着访问控制线路控制连接到访问控制线路的多个访问控制设备。访问控制电路通过将提供给访问控制线的电压电平以第一平均速率增加到第一电压电平来响应于数据访问请求信号，然后响应于接收到增加提供给访问的电压电平的另外的信号控制线到预定的较高电压电平，使得从第一电压到预定的较高电压电平的电压电平的进一步的平均增加率低于第一平均增长率至第一电平。

29. 发明授权

US08171386B2 Single event upset error detection within sequential storage circuitry of an integrated circuit 有权
标题翻译：集成电路的顺序存储电路内的单事件镦粗错误检测
公开(公告)号：US08171386B2
公开(公告)日：2012-05-01
申请号：US12078189
申请日：2008-03-27
申请人： Vikas Chandra , Sachin Satish Idgunji
发明人： Vikas Chandra , Sachin Satish Idgunji
IPC分类号： G06F11/00
CPC分类号： G06F11/00
摘要： Sequential storage circuitry for a integrated circuit is provided, comprising a first storage element, a second storage element and an additional storage element. The first storage element stores, during a first phase of a clock signal, a first indication of an input data value received by the sequential storage circuitry. The second storage element is coupled to an output of the first storage element, and stores a second indication of the input data value during a second phase of the clock signal. The additional storage element is driven by a pulse signal derived from the clock signal, and is arranged on occurrence of that pulse signal to store a third indication of the input data value. Error detection circuitry is then provided for detecting a single event upset error in either the first storage element or the second storage element. In particular, during the first phase of the clock signal, the error detection circuitry detects the single event upset error in the first storage element if there is a difference in the input data value as indicated by the first indication and the third indication. Further, during the second phase of the clock signal, the error detection circuitry detects a single event upset error in the second storage element if there is a difference in the input data value as indicated by the second indication and the third indication. Such an arrangement provides a simple mechanism for detecting soft errors in both the first storage element and the second storage element using only one additional storage element.
摘要翻译：提供了一种用于集成电路的顺序存储电路，包括第一存储元件，第二存储元件和附加存储元件。第一存储元件在时钟信号的第一阶段存储由顺序存储电路接收的输入数据值的第一指示。第二存储元件耦合到第一存储元件的输出，并且在时钟信号的第二阶段期间存储输入数据值的第二指示。附加存储元件由从时钟信号导出的脉冲信号驱动，并且被布置为发生该脉冲信号以存储输入数据值的第三指示。然后提供错误检测电路用于检测第一存储元件或第二存储元件中的单个事件镦锻错误。特别地，在时钟信号的第一阶段期间，如果由第一指示和第三指示所指示的输入数据值存在差异，则错误检测电路检测第一存储元件中的单事件翻转错误。此外，在时钟信号的第二阶段期间，如果由第二指示和第三指示所指示的输入数据值存在差异，则错误检测电路检测第二存储元件中的单个事件不正常错误。这种布置提供了使用仅一个附加存储元件来检测第一存储元件和第二存储元件中的软错误的简单机制。

30. 发明授权

US08103990B2 Characterising circuit cell performance variability in response to perturbations in manufacturing process parameters 有权
标题翻译：表征响应于制造工艺参数中扰动的电路单元性能变化
公开(公告)号：US08103990B2
公开(公告)日：2012-01-24
申请号：US12073050
申请日：2008-02-28
申请人： Sachin Satish Idgunji , Robert Campbell Aitken
发明人： Sachin Satish Idgunji , Robert Campbell Aitken
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/12 , G06F2217/66 , Y02P90/265
摘要： A technique for characterising variation in a performance parameter(s) of circuit cells within a circuit cell library with perturbations in manufacturing process parameters uses a statistical approach whereby the statistical distribution of performance parameter(s) resulting from a joint distribution across manufacturing process parameter space is determined. The perturbation in manufacturing process parameter which results in a characteristic amount of variation is then identified and common sets of such perturbations used to group families of circuit cells together. Families of circuit cells have a correlation in their response to manufacturing process parameter perturbation and this is represented by a correlation matrix. Variation characterising data generated in accordance with the above technique is used to drive electronic design automation tools in integrated circuit design and manufacture.
摘要翻译：用于表征制造工艺参数中的扰动的电路单元库内的电路单元的性能参数的变化的技术使用统计方法，其中通过制造过程参数空间的联合分布产生的性能参数的统计分布决心，决意，决定。然后识别导致特征变化量的制造过程参数中的扰动，并且将用于将电路单元的族分组在一起的这种扰动的常见集合。电路单元族在其对制造工艺参数扰动的响应中具有相关性，并且由相关矩阵表示。根据上述技术生成的变化特征数据用于驱动集成电路设计和制造中的电子设计自动化工具。

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