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21. 发明授权

US3989955A Logic circuit arrangements using insulated-gate field effect transistors 失效
标题翻译：使用绝缘栅场效应晶体管的逻辑电路布置
公开(公告)号：US3989955A
公开(公告)日：1976-11-02
申请号：US668056
申请日：1976-03-18
申请人： Yasoji Suzuki
发明人： Yasoji Suzuki
IPC分类号： H03K19/096 , H03K19/08 , H03K19/20 , H03K19/34 , H03K19/36
CPC分类号： H03K19/0963
摘要： A clock pulse-controlled logic circuit arrangement wherein the source-drain path of a first transistor having its gate electrode supplied with a clock pulse and the source-drain paths of at least two second transistors jointly constituting a logic gate by having the respective gate electrodes supplied with data input are connected in series between a first and a second operating voltage supply point. To the junction of the first transistor and logic gate or an output point is connected an operation stabilizing circuit for replenishing the output point with a voltage signal having the same polarity as the output voltage signal to prevent any change in the level of the output voltage signal while the first transistor is rendered nonconducting.
摘要翻译：一种时钟脉冲控制逻辑电路装置，其中其第一晶体管的源极 - 漏极路径被提供有时钟脉冲，并且至少两个第二晶体管的源极 - 漏极通路共同构成逻辑门，该第二晶体管具有各自的栅电极提供有数据输入的串联连接在第一和第二工作电压提供点之间。连接到第一晶体管与逻辑门或输出点的结点，连接一个操作稳定电路，用于补偿具有与输出电压信号相同极性的电压信号的输出点，以防止输出电压信号的电平发生任何变化而第一个晶体管是不导通的。

22. 发明授权

US3958187A Clock signal generating device with complementary MOS transistors 失效
标题翻译：具有补充MOS晶体管的时钟信号发生器件
公开(公告)号：US3958187A
公开(公告)日：1976-05-18
申请号：US578985
申请日：1975-05-19
申请人： Yasoji Suzuki , Teruaki Tanaka
发明人： Yasoji Suzuki , Teruaki Tanaka
IPC分类号： H01L27/06 , G04F5/06 , G04G3/02 , H01L21/8234 , H03K3/354 , H03B5/36 , H03K23/30
CPC分类号： H03K3/3545 , G04F5/06 , G04G3/02
摘要： Disclosed is a clock signal generating integrated circuit device comprising a quartz crystal oscillator section and a multistage frequency divider section. The crystal oscillator section and each frequency divider stage includes respectively complementary insulated gate field effect transistors. According to the present invention, the high frequency-operated field effect transistors have a lower threshold voltage than the remaining field effect transistors, so that the occupied area of the oscillator section can be decreased and simultaneously the power dissipation can also be reduced.

23. 发明授权

US06459416B1 Multi-gray level display apparatus and method of displaying an image at many gray levels 有权
标题翻译：多灰度级显示装置和在许多灰度级显示图像的方法
公开(公告)号：US06459416B1
公开(公告)日：2002-10-01
申请号：US09265795
申请日：1999-03-10
申请人： Itsuo Sasaki , Yasoji Suzuki , Hirofumi Kato , Isao Arita , Toshio Yanagisawa , Kazuyoshi Yamamoto , Hiroyoshi Murata , Hiroyuki Hamagawa
发明人： Itsuo Sasaki , Yasoji Suzuki , Hirofumi Kato , Isao Arita , Toshio Yanagisawa , Kazuyoshi Yamamoto , Hiroyoshi Murata , Hiroyuki Hamagawa
IPC分类号： G09G328
CPC分类号： G09G3/3648 , G09G3/2007 , G09G3/2018 , G09G2310/027
摘要： A multi-gray level display designed to display multi-gray level images free of flicker or the like, by using a small number of voltages. The display comprises a first gray-level pattern generating circuit 311 for generating a first gray-level pattern which acquires a gray level during m frame periods, a second gray-level pattern generating circuit 321 for generating a second gray-level pattern which acquires another gray level during n frame periods (n is a positive integer greater than m), and a selection circuit 341 for selecting and outputting one of the preset voltages, in accordance with an output from the first gray-level pattern generating circuit 311 or the second gray-level pattern generating circuit 321 when the input multi-gray level display data corresponds to a gray level of either the first gray-level pattern or the second gray-level pattern.
摘要翻译：通过使用少量电压，设计用于显示无闪烁等的多灰度级图像的多灰度级显示器。显示器包括：第一灰度级图形生成电路311，用于产生在m个帧周期期间获取灰度级的第一灰度级图形;第二灰度级图形生成电路321，用于生成获取另一灰度级图案的第二灰度级图案在n个帧周期（n是大于m的正整数）的灰度级，以及根据来自第一灰度级图形生成电路311或第二灰度级图形生成电路311的输出，选择并输出预设电压之一的选择电路341 当输入的多灰度级显示数据对应于第一灰度级图案或第二灰度级图案的灰度级时，灰度级图形产生电路321。

24. 发明授权

US5719649A Light guide and liquid crystal display device using it 失效
标题翻译：光导和液晶显示装置使用它
公开(公告)号：US5719649A
公开(公告)日：1998-02-17
申请号：US466796
申请日：1995-06-06
申请人： Yasuo Shono , Yasoji Suzuki , Yoshinori Higuchi , Naoto Ide
发明人： Yasuo Shono , Yasoji Suzuki , Yoshinori Higuchi , Naoto Ide
IPC分类号： F21V8/00 , G02B6/00 , G02F1/1335
CPC分类号： G02B6/0036 , G02B6/0001 , G02B6/0053 , G02B6/0065
摘要： On a light exit surface which is the first principal plane of a light guide, multiple projections are fabricated in specific rows. These projections have light exit surfaces and continuous multiple slopes, and are fabricated from optically identical materials having the same refractive index as the substrate of the light guide. The slope farthest from the light entry edge surface is formed as a light exit surface, i.e., a surface which breaks the conditions for the total reflection of the incident light. On the other hand, the slope nearest the light entry edge surface which is the total reflection surface is formed such that the incident light is totally reflected.
摘要翻译：在作为光导的第一主平面的光出射面上，以特定的行制造多个突起。这些突起具有光出射表面和连续的多个斜面，并且由具有与光导的基底相同的折射率的光学上相同的材料制成。从光入射边缘表面最远的斜面形成为光出射表面，即破坏入射光全反射条件的表面。另一方面，最接近作为全反射面的光入射边缘面的斜率被形成为入射光被全反射。

25. 发明授权

US5058063A Nonvolatile semiconductor memory device incorporating level shifting circuits 失效
标题翻译：非线性半导体存储器件并入电平放大电路
公开(公告)号：US5058063A
公开(公告)日：1991-10-15
申请号：US454740
申请日：1989-12-21
申请人： Yukio Wada , Tadashi Maruyama , Yasoji Suzuki
发明人： Yukio Wada , Tadashi Maruyama , Yasoji Suzuki
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/14
CPC分类号： G11C16/10 , G11C16/0433 , G11C16/14
摘要： In a nonvolatile semiconductor memory system comprising a memory chip and a batttery for driving the memory chip, the memory chip includes a memory-cell matrix, a row decoder, a first level-shifting circuit for shifting the level of the output of the row decoder, a column-selecting circuit, a column decoder, a second level-shifting circuit for shifting the level of the output of the column decoder, a sense amplifier, a third level-shifting circuit for shifting the level of the data which is to be written into the memory-cell matrix, a voltage-booster circuit, a timer circuit, and an oscillator circuit. The nonvolatile semiconductor memory system operates stably when driven by a low voltage or by a voltage over a broad range.

26. 发明授权

US4301427A Astable MOS FET multivibrator 失效
标题翻译：可靠的MOS FET多谐振荡器
公开(公告)号：US4301427A
公开(公告)日：1981-11-17
申请号：US129737
申请日：1980-03-12
申请人： Yasoji Suzuki , Tetsuya Iida
发明人： Yasoji Suzuki , Tetsuya Iida
IPC分类号： H03K3/354 , H03K4/501
CPC分类号： H03K3/354 , H03K4/501
摘要： A Schmitt trigger astable multivibrator circuit includes a first inverter, a second inverter whose input terminal is connected to the output terminal of the first inverter, a third inverter which is constituted by a first P-channel transistor and a first N-channel transistor serially connected and whose input and output terminals are respectively connected to the output and input terminals of the second inverter. The Schmitt trigger astable multivibrator circuit further includes a second P-channel transistor connected between a positive power supply terminal and the first P-channel transistor, and a second N-channel transistor connected between a ground terminal and the first N-channel transistor, and an input signal supplied to the first inverter is also applied to the gates of the second P-channel and N-channel transistors. The astable multivibrator also includes a time constant circuit, activated in response to the second inverter's output, which connects to the first inverter's input.
摘要翻译：施密特触发器非稳态多谐振荡器电路包括第一反相器，其输入端连接到第一反相器的输出端的第二反相器，由第一P沟道晶体管和第一N沟道晶体管串联连接的第三反相器并且其输入和输出端分别连接到第二反相器的输出端和输入端。施密特触发器非稳态多谐振荡器电路还包括连接在正电源端子和第一P沟道晶体管之间的第二P沟道晶体管，以及连接在接地端子和第一N沟道晶体管之间的第二N沟道晶体管，以及提供给第一反相器的输入信号也被施加到第二P沟道和N沟道晶体管的栅极。不稳定的多谐振荡器还包括响应于第二反相器输出而被激活的时间常数电路，其连接到第一反相器的输入端。

27. 发明授权

US4268761A Interface circuit for converting logic signal levels 失效
标题翻译：用于转换逻辑信号电平的接口电路
公开(公告)号：US4268761A
公开(公告)日：1981-05-19
申请号：US16565
申请日：1979-03-01
申请人： Yasoji Suzuki , Tetsuya Iida
发明人： Yasoji Suzuki , Tetsuya Iida
IPC分类号： H03K5/02 , H03K19/0185 , H03L5/00
CPC分类号： H03K19/018528 , H03K5/023
摘要： An input terminal of an interface circuit is connected to a first logic circuit which produces a first logic signal. The interface circuit compares the first logic signal with a reference voltage whose level is set between a high level and a low level of the first logic signal. The interface circuit converts levels of the signal compared. An output terminal of the interface circuit is connected to a second logic circuit whose signal levels are different from levels of the first logic signal and which is driven by the output signal compared and amplified.
摘要翻译：接口电路的输入端连接到产生第一逻辑信号的第一逻辑电路。接口电路将第一逻辑信号与其电平设置在第一逻辑信号的高电平和低电平之间的参考电压进行比较。接口电路转换信号的电平进行比较。接口电路的输出端子连接到第二逻辑电路，其信号电平与第一逻辑信号的电平不同，并且被比较和放大的输出信号驱动。

28. 发明授权

US4259686A Circuit for producing a polarity-reversed voltage with opposite polarity to that of a power supply voltage 失效
标题翻译：用于产生与电源电压相反的极性的极性反转电压的电路
公开(公告)号：US4259686A
公开(公告)日：1981-03-31
申请号：US947432
申请日：1978-10-02
申请人： Yasoji Suzuki , Tetsuya Iida
发明人： Yasoji Suzuki , Tetsuya Iida
IPC分类号： H02J1/00 , G05F3/24 , H02M3/07 , H03K5/003 , H03K5/00
CPC分类号： H03K5/003 , H02M3/07
摘要： An inverter is controlled by first clock pulses for converting a positive power supply into second clock pulses having a first voltage level of the power supply and a second voltage level of a reference voltage. The second clock pulses are supplied to a capacitor. The source-drain path of a first impedance varying P-FET is connected between the output terminal of the capacitor and the reference voltage and is controlled so as to take a low impedance when the second clock pulses are at the first voltage level while a high impedance when the second clock pulses are at the second voltage level. The source-drain path of a second impedance varying P-FET is connected between the output terminal and a terminal for taking out a polarity-reversed voltage. The second impedance varying P-FET is supplied at the gate with the first clock pulses so as to be controlled to take a high impendance when the second clock pulses are at the first voltage level and a low impedance when the second clock pulses are at the second level.
摘要翻译：逆变器由第一时钟脉冲控制，用于将正电源转换成具有电源的第一电压电平和参考电压的第二电压电平的第二时钟脉冲。第二个时钟脉冲被提供给电容器。第一阻抗变化P-FET的源极 - 漏极路径被连接在电容器的输出端子和参考电压之间，并且当第二时钟脉冲处于第一电压电平时被控制成低阻抗，而高当第二时钟脉冲处于第二电压电平时的阻抗。第二阻抗变化P-FET的源极 - 漏极路径连接在输出端子和用于取出极性反转电压的端子之间。第二阻抗变化P-FET在栅极处以第一时钟脉冲提供，以便当第二时钟脉冲处于第一电压电平时被控制以产生高阻抗，而当第二时钟脉冲处于第二时钟脉冲时二级

29. 发明授权

US4209713A Semiconductor integrated circuit device in which difficulties caused by parasitic transistors are eliminated 失效
标题翻译：消除了由寄生晶体管引起的困难的半导体集成电路器件
公开(公告)号：US4209713A
公开(公告)日：1980-06-24
申请号：US911164
申请日：1978-05-31
申请人： Kazuo Satou , Mitsuhiko Ueno , Yasoji Suzuki
发明人： Kazuo Satou , Mitsuhiko Ueno , Yasoji Suzuki
IPC分类号： H01L27/092 , H03K17/16 , H01L27/02 , H03K17/72 , H03K19/40
CPC分类号： H01L27/0921 , H03K17/162
摘要： A semiconductor integrated circuit device comprising a CMOS circuit in which parasitic transistors form a parasitic thyristor circuit. In this device, noise absorption resistances are provided at the noise inputs to absorb noise which otherwise might become trigger pulses for the thyristors.
摘要翻译：一种半导体集成电路器件，包括其中寄生晶体管形成寄生晶闸管电路的CMOS电路。在该装置中，在噪声输入处提供噪声吸收电阻以吸收另外可能成为可控硅的触发脉冲的噪声。

30. 发明授权

US4136292A Voltage sensing circuit of differential input type 失效
标题翻译：差分输入型电压感应电路
公开(公告)号：US4136292A
公开(公告)日：1979-01-23
申请号：US827721
申请日：1977-08-25
申请人： Yasoji Suzuki , Kiyofumi Ochii
发明人： Yasoji Suzuki , Kiyofumi Ochii
IPC分类号： G11C11/409 , G11C11/406 , G11C11/4091 , G11C11/412 , G11C11/419 , H03K5/02 , H03K5/20
CPC分类号： G11C11/419 , G11C11/4091 , H03K5/023
摘要： A voltage sensing circuit of differential input type includes at least one differential amplifier circuit connected between two complementary data lines of a semiconductor memory. The differential amplifier circuit detects data in response to a minute potential difference between the data lines and amplifies the same by a substantial change in conductance g.sub.m of metal oxide semiconductor field effect transistors (MOSFET) used in the circuit. When data is read from a semiconductor memory onto the data lines, the differential amplifier sensing circuit detects the data quickly by detecting potential changes of the data lines.

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