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21. 发明授权

US5757682A Parallel calculation of exponent and sticky bit during normalization 失效
标题翻译：在归一化期间并行计算指数和粘点
公开(公告)号：US5757682A
公开(公告)日：1998-05-26
申请号：US414072
申请日：1995-03-31
申请人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
发明人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
IPC分类号： G06F5/01 , G06F7/57 , G06F7/00 , G06F7/38
CPC分类号： G06F5/012 , G06F7/483 , G06F7/49952 , G06F7/49957
摘要： A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing. The group sticky bits are further multiplexed according to subsequent shift amounts in the fractional dataflow to provide an output sticky bit at substantially the same time as when the final fractional shift amount is available, and thereby at substantially the same time as the normalized fraction.
摘要翻译：根据分数位移数据流，根据将指数分解成部分指数组，实现用于在归一化期间确定分数移位的方法来确定指数的方法的系统，根据分数确定每个部分指数组的所有可能的部分指数值数据流，并且通过根据分数据流选择性地组合来自每个部分指数组的可能部分指数来提供指数。还提供了一种实现在归一化过程中产生粘性位的方法的系统。粘滞位信息根据分数据流进行预先计算和复用。在本发明的一个实施例中，以树形式计算组粘性信号，每组粘性具有与多路复用的移位增量量相对应的多个可能的粘性位。组粘性位根据分数据流中的随后的移位量进一步复用，以在与最终分数移位量可用时基本相同的时间提供输出粘性位，并且因此与归一化分数基本上相同。

22. 发明申请

US20110225438A1 COMPUTER PROGRAM PRODUCT FOR CONTROLLING A STORAGE DEVICE HAVING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES 有权
标题翻译：用于控制具有各元件选择电源电压的存储设备的计算机程序产品
公开(公告)号：US20110225438A1
公开(公告)日：2011-09-15
申请号：US13115149
申请日：2011-05-25
申请人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G06F1/32
CPC分类号： G11C11/417 , G11C5/14
摘要： A computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：用于使用每元件可选择的电源电压来控制存储设备的计算机程序产品在保持特定性能水平的同时在存储设备中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

23. 发明申请

US20090302929A1 Methods and Apparatus for Varying a Supply Voltage or Reference Voltage Using Independent Control of Diode Voltage in Asymmetrical Double-Gate Devices 有权
标题翻译：使用非对称双栅极器件中二极管电压的独立控制改变电源电压或参考电压的方法和装置
公开(公告)号：US20090302929A1
公开(公告)日：2009-12-10
申请号：US12511658
申请日：2009-07-29
申请人： Ching-Te Kent Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
发明人： Ching-Te Kent Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03K3/01
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
摘要翻译：提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。提供由电源电压和参考电压中的一个或多个控制的集成电路。集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。独立控制可以包括例如背栅偏置。独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。

24. 发明申请

US20090129193A1 ENERGY EFFICIENT STORAGE DEVICE USING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES 失效
标题翻译：使用全能选择电源电压的能源效率存储设备
公开(公告)号：US20090129193A1
公开(公告)日：2009-05-21
申请号：US11941168
申请日：2007-11-16
申请人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G11C5/14 , G06F12/00
CPC分类号： G11C11/417 , G11C5/14
摘要： An energy efficient storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：使用每元件可选择的电源电压的节能存储装置在保持特定的性能水平的同时在存储装置中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

25. 发明申请

US20080137455A1 Storage Cell Design Evaluation Circuit Including a Wordline Timing and Cell Access Detection Circuit 失效
标题翻译：包括字线定时和单元访问检测电路的存储单元设计评估电路
公开(公告)号：US20080137455A1
公开(公告)日：2008-06-12
申请号：US11609598
申请日：2006-12-12
申请人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Cai Ngo
发明人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Cai Ngo
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/02 , G11C29/025 , G11C29/50012
摘要： A method for storage cell design evaluation provides accurate information about state changes in static storage cells. A wordline select pulse is propagated along the wordline select path of the test row to an output driver circuit, in order to test the clock and/or address timing of the row, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. An access detection cell holds the input of the output driver circuit until a simulated access operation activated by the wordline select pulse is complete. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.
摘要翻译：用于存储单元设计评估的方法提供关于静态存储单元中的状态变化的准确信息。字线选择脉冲沿着测试行的字线选择路径传播到输出驱动器电路，以便测试该行的时钟和/或地址时序，使得访问时序，读取稳定性和可写性与字线强度的变化 /访问电压可以确定。访问检测单元保持输出驱动器电路的输入，直到由字线选择脉冲激活的模拟访问操作完成。多个测试行可以在列之间级联，以提供长延迟线或环形振荡器，以提高测量分辨率。

26. 发明授权

US06407574B1 Method and system for utilizing hostile-switching neighbors to improve interconnect speed for high performance processors 有权
标题翻译：利用敌对交换邻居提高高性能处理器互连速度的方法和系统
公开(公告)号：US06407574B1
公开(公告)日：2002-06-18
申请号：US09670436
申请日：2000-09-26
申请人： Huajun Wen , Hung Cai Ngo
发明人： Huajun Wen , Hung Cai Ngo
IPC分类号： H03K1716
CPC分类号： H03K19/00361 , H03K19/01721
摘要： Disclosed is a system for reducing propagation delays caused by capacitive coupling of RC interconnects. The system comprises a first interconnect utilized for propagating signals, a second interconnect also utilized for propagating signals but which propagates signals at a faster rate than the first interconnect, and a charge dumping circuit with an input coupled to a point on the second interconnect and an output coupled to a corresponding point on the first interconnect. The charge dumping circuit includes a pulse generation circuit and a select-signal generation circuit, both of which are utilized to enable charge to be dumped from the second interconnect to the first interconnect to increase switching times of the signals propagating on the first interconnect and improve overall propagation speed.
摘要翻译：公开了一种用于减少由RC互连的电容耦合引起的传播延迟的系统。该系统包括用于传播信号的第一互连，还用于传播信号但以比第一互连更快的速率传播信号的第二互连，以及具有耦合到第二互连上的点的输入的电荷倾倒电路，以及输出耦合到第一互连上的对应点。电荷倾倒电路包括脉冲发生电路和选择信号产生电路，它们都被用于使电荷能够从第二互连转移到第一互连，以增加在第一互连上传播的信号的切换时间并提高总体传播速度。

27. 发明授权

US06175852B1 High-speed binary adder 失效
标题翻译：高速二进制加法器
公开(公告)号：US06175852B1
公开(公告)日：2001-01-16
申请号：US09114117
申请日：1998-07-13
申请人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
发明人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G06F750
CPC分类号： G06F7/508
摘要： A high-speed carry-lookahead binary adder is disclosed. The binary adder includes multiple rows of carry-lookahead circuits, a half-sum module, and a sum/carry module. A first carry-lookahead circuit row includes multiple eight-bit group generate circuits and multiple eight-bit group propagate circuits. Each of the eight-bit group generate circuits produces a generate signal for a corresponding bit location. Each of the eight-bit group propagate circuits produces a propagate signal for a corresponding bit location. The half-sum module is utilized to generate a half-sum signal. By utilizing the half-sum signal, the generate signals, and the propagate signals, the sum/carry module generates sum signals and a carry signal.
摘要翻译：公开了一种高速进位 - 前瞻二进制加法器。二进制加法器包括多行进位查找电路，半和模块和和/进位模块。第一进位 - 前瞻电路行包括多个8位组生成电路和多个8位组传播电路。八位组生成电路中的每一个产生相应位位置的生成信号。八位组传播电路中的每一个产生相应位位置的传播信号。半和模块用于产生半和信号。通过利用半和信号，生成信号和传播信号，和/进位模块产生和信号和进位信号。

28. 发明授权

US5742536A Parallel calculation of exponent and sticky bit during normalization 失效
标题翻译：在归一化期间并行计算指数和粘点
公开(公告)号：US5742536A
公开(公告)日：1998-04-21
申请号：US478416
申请日：1995-06-07
申请人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
发明人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
IPC分类号： G06F5/01 , G06F7/57 , G06F7/38
CPC分类号： G06F5/012 , G06F7/483 , G06F7/49952 , G06F7/49957
摘要： A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing. The group sticky bits are further multiplexed according to subsequent shift amounts in the fractional damflow to provide an output sticky bit at substantially the same time as when the final fractional shift amount is available, and thereby at substantially the same time as the normalized fraction.
摘要翻译：根据分数位移数据流，根据将指数分解成部分指数组，实现用于在归一化期间确定分数移位的方法来确定指数的方法，根据分数确定每个部分指数组的所有可能的部分指数值数据流，并且通过根据分数据流选择性地组合来自每个部分指数组的可能部分指数来提供指数。还提供了一种实现在归一化过程中产生粘性位的方法的系统。粘滞位信息根据分数据流进行预先计算和复用。在本发明的一个实施例中，以树形式计算组粘性信号，每组粘性具有与多路复用的移位增量量相对应的多个可能的粘性位。组粘性位根据分数阻力流中的后续移位量进一步复用，以在与最终分数位移量可用时基本相同的时间提供输出粘性位，从而与标准化分数基本上相同。

29. 发明授权

US5742535A Parallel calculation of exponent and sticky bit during normalization 失效
公开(公告)号：US5742535A
公开(公告)日：1998-04-21
申请号：US461676
申请日：1995-06-05
申请人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
发明人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
IPC分类号： G06F5/01 , G06F7/57 , G06F7/38
CPC分类号： G06F5/012 , G06F7/483 , G06F7/49952 , G06F7/49957
摘要： A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing. The group sticky bits are further multiplexed according to subsequent shift amounts in the fractional dataflow to provide an output sticky bit at substantially the same time as when the final fractional shift amount is available, and thereby at substantially the same time as the normalized fraction.

30. 发明授权

US07952422B2 Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices 有权
标题翻译：使用不对称双栅极器件中二极管电压的独立控制来改变电源电压或参考电压的方法和装置
公开(公告)号：US07952422B2
公开(公告)日：2011-05-31
申请号：US12511658
申请日：2009-07-29
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03K3/01
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
摘要翻译：提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。提供由电源电压和参考电压中的一个或多个控制的集成电路。集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。独立控制可以包括例如背栅偏置。独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。

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