发明申请
US20080137455A1 Storage Cell Design Evaluation Circuit Including a Wordline Timing and Cell Access Detection Circuit
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基本信息:
- 专利标题： Storage Cell Design Evaluation Circuit Including a Wordline Timing and Cell Access Detection Circuit
- 专利标题（中）：包括字线定时和单元访问检测电路的存储单元设计评估电路
- 申请号：US11609598 申请日：2006-12-12
- 公开(公告)号：US20080137455A1 公开(公告)日：2008-06-12
- 发明人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Cai Ngo
- 申请人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Cai Ngo
- 主分类号： G11C29/00
- IPC分类号： G11C29/00
摘要：
A method for storage cell design evaluation provides accurate information about state changes in static storage cells. A wordline select pulse is propagated along the wordline select path of the test row to an output driver circuit, in order to test the clock and/or address timing of the row, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. An access detection cell holds the input of the output driver circuit until a simulated access operation activated by the wordline select pulse is complete. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.
摘要（中）：
用于存储单元设计评估的方法提供关于静态存储单元中的状态变化的准确信息。 字线选择脉冲沿着测试行的字线选择路径传播到输出驱动器电路，以便测试该行的时钟和/或地址时序，使得访问时序，读取稳定性和可写性与字线强度的变化 /访问电压可以确定。 访问检测单元保持输出驱动器电路的输入，直到由字线选择脉冲激活的模拟访问操作完成。 多个测试行可以在列之间级联，以提供长延迟线或环形振荡器，以提高测量分辨率。