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1. 发明授权

US5757682A Parallel calculation of exponent and sticky bit during normalization 失效
标题翻译：在归一化期间并行计算指数和粘点
公开(公告)号：US5757682A
公开(公告)日：1998-05-26
申请号：US414072
申请日：1995-03-31
申请人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
发明人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
IPC分类号： G06F5/01 , G06F7/57 , G06F7/00 , G06F7/38
CPC分类号： G06F5/012 , G06F7/483 , G06F7/49952 , G06F7/49957
摘要： A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing. The group sticky bits are further multiplexed according to subsequent shift amounts in the fractional dataflow to provide an output sticky bit at substantially the same time as when the final fractional shift amount is available, and thereby at substantially the same time as the normalized fraction.
摘要翻译：根据分数位移数据流，根据将指数分解成部分指数组，实现用于在归一化期间确定分数移位的方法来确定指数的方法的系统，根据分数确定每个部分指数组的所有可能的部分指数值数据流，并且通过根据分数据流选择性地组合来自每个部分指数组的可能部分指数来提供指数。还提供了一种实现在归一化过程中产生粘性位的方法的系统。粘滞位信息根据分数据流进行预先计算和复用。在本发明的一个实施例中，以树形式计算组粘性信号，每组粘性具有与多路复用的移位增量量相对应的多个可能的粘性位。组粘性位根据分数据流中的随后的移位量进一步复用，以在与最终分数移位量可用时基本相同的时间提供输出粘性位，并且因此与归一化分数基本上相同。

2. 发明授权

US5742536A Parallel calculation of exponent and sticky bit during normalization 失效
标题翻译：在归一化期间并行计算指数和粘点
公开(公告)号：US5742536A
公开(公告)日：1998-04-21
申请号：US478416
申请日：1995-06-07
申请人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
发明人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
IPC分类号： G06F5/01 , G06F7/57 , G06F7/38
CPC分类号： G06F5/012 , G06F7/483 , G06F7/49952 , G06F7/49957
摘要： A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing. The group sticky bits are further multiplexed according to subsequent shift amounts in the fractional damflow to provide an output sticky bit at substantially the same time as when the final fractional shift amount is available, and thereby at substantially the same time as the normalized fraction.
摘要翻译：根据分数位移数据流，根据将指数分解成部分指数组，实现用于在归一化期间确定分数移位的方法来确定指数的方法，根据分数确定每个部分指数组的所有可能的部分指数值数据流，并且通过根据分数据流选择性地组合来自每个部分指数组的可能部分指数来提供指数。还提供了一种实现在归一化过程中产生粘性位的方法的系统。粘滞位信息根据分数据流进行预先计算和复用。在本发明的一个实施例中，以树形式计算组粘性信号，每组粘性具有与多路复用的移位增量量相对应的多个可能的粘性位。组粘性位根据分数阻力流中的后续移位量进一步复用，以在与最终分数位移量可用时基本相同的时间提供输出粘性位，从而与标准化分数基本上相同。

3. 发明授权

US5742535A Parallel calculation of exponent and sticky bit during normalization 失效
公开(公告)号：US5742535A
公开(公告)日：1998-04-21
申请号：US461676
申请日：1995-06-05
申请人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
发明人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
IPC分类号： G06F5/01 , G06F7/57 , G06F7/38
CPC分类号： G06F5/012 , G06F7/483 , G06F7/49952 , G06F7/49957
摘要： A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing. The group sticky bits are further multiplexed according to subsequent shift amounts in the fractional dataflow to provide an output sticky bit at substantially the same time as when the final fractional shift amount is available, and thereby at substantially the same time as the normalized fraction.

4. 发明授权

US5654911A Carry select and input select adder for late arriving data 失效
公开(公告)号：US5654911A
公开(公告)日：1997-08-05
申请号：US472962
申请日：1995-06-07
申请人： Eric Mark Schwarz , Robert Michael Bunce
发明人： Eric Mark Schwarz , Robert Michael Bunce
IPC分类号： G06F7/50 , G06F7/507
CPC分类号： G06F7/507
摘要： An adder which takes advantage of the early arriving bits of a time skewed operand to provide a result to an add or substract operation without additional latency. Possible partial results are calculated and then selectively combined according to the late arriving data as the late arriving data becomes available. In an embodiment of the present invention, a first operand is partitioned into groups according to the arrival time of the skewed data, and possible partial results for each group are calculated for the full range of partial inputs that affect it. In addition, the high order groups are calculated with and without a borrow (carry) which is propagated from a low order group. Once the delayed partial operands are known and the borrows (carrys) determined the partial results are gated through multiplexers according to the borrows and partial results, and thus the result is provided with a delay similar to the delay in arrival of the skewed operand.

5. 发明授权

US6044454A IEEE compliant floating point unit 失效
标题翻译：符合IEEE标准的浮点单元
公开(公告)号：US6044454A
公开(公告)日：2000-03-28
申请号：US26328
申请日：1998-02-19
申请人： Eric Mark Schwarz , Christopher A. Krygowski , Timothy John Slegel , David Frazelle McManigal , Mark Steven Farrell
发明人： Eric Mark Schwarz , Christopher A. Krygowski , Timothy John Slegel , David Frazelle McManigal , Mark Steven Farrell
IPC分类号： G06F7/00 , G06F7/76 , G06F9/302 , G06F9/318 , G06F9/38
CPC分类号： G06F9/30014 , G06F9/3017 , G06F9/3861 , G06F9/3885
摘要： IEEE compliant floating point unit mechanism allows variability in the execution of floating point operations according to the IEEE 754 standard and allowing variability of the standard to co-exist in hardware or in the combination of hardware and millicode. The FPU has a detector of special conditions which dynamically detects an event that the hardware execution of an IEEE compliant Binary Floating Point instruction will require millicode emulation. The complete set of events which millicode may emulate are predetermined early in the design process of the hardware. An exception handling unit assist millicode emulation by trapping the result of an exceptional condition without invoking the trap handler. When an exceptional condition is detected during execution, the IEEE 754 standard requires two different actions under control of a mask bit. If the mask bit is on, the result is written into an FPR and the trap handler is invoked. Otherwise, a default value is written, a flag is set, and the program continues execution. This allows a variation to the IEEE 754 standard. Two different versions of the function of the Multiply-then-Substract instruction are implemented for two different IEEE 754 compliant architectures.
摘要翻译：符合IEEE标准的浮点单元机制允许根据IEEE 754标准执行浮点运算的可变性，并允许标准的可变性在硬件或硬件和毫代数的组合中共存。 FPU具有特殊条件检测器，可动态检测符合IEEE标准的二进制浮点指令的硬件执行需要进行微码仿真的事件。在硬件的设计过程的早期，预先确定了一系列可能模拟的事件。异常处理单元通过捕获特殊条件的结果而不调用陷阱处理程序来辅助millicode仿真。当在执行期间检测到异常情况时，IEEE 754标准在屏蔽位的控制下需要两个不同的动作。如果掩码位打开，则将结果写入FPR，并调用陷阱处理程序。否则，将写入默认值，设置一个标志，程序继续执行。这允许对IEEE 754标准的变化。对于两种不同的符合IEEE 754标准的架构，实现了两种不同版本的“乘法 - 再次抽取”指令的功能。

6. 发明授权

US6021422A Partitioning of binary quad word format multiply instruction on S/390 processor 失效
标题翻译：在S / 390处理器上分配二进制四字格式乘法指令
公开(公告)号：US6021422A
公开(公告)日：2000-02-01
申请号：US33626
申请日：1998-03-05
申请人： Eric Mark Schwarz
发明人： Eric Mark Schwarz
IPC分类号： G06F7/52 , G06F7/44 , G06F7/38
CPC分类号： G06F7/5324 , G06F7/4876 , G06F2207/382
摘要： There is a unique partitioning problem in determining how to execute the floating point multiply instruction defined by IEEE 754 standard for the quad word format on a S/390 processor. Several manufacturers including IBM and HP define the binary quad word format to have a 113 bit significand. IBM S/390 hexadecimal long floating point format has a 56 bit significand and most S/390 floating point units only contain a long format multiplier. Quad word format multiplication must be executed as a series of several long precision multiplications and extended precision or long precision additions. The S/390 hexadecimal quad word format is easier to implement than binary format since it has a 112 bit significand and can easily be partitioned into two 56 bit parts. But a 113 bit significand would just exceed two partitions and require a third. For extended precision multiplies each partition is multiplied by each other, so if there are two partitions only four multiplies are required but for three partitions this increases to nine multiplies. Methods for partitioning are disclosed here.
摘要翻译：确定如何在S / 390处理器上执行由IEEE 754标准定义的四字格式的浮点乘法指令，存在独特的划分问题。包括IBM和HP在内的几家制造商将二进制四字格式定义为具有113位有效位数。 IBM S / 390十六进制长浮点格式具有56位有效位数，大多数S / 390浮点单元仅包含长格式乘数。四字格式乘法必须作为一系列长精度乘法和扩展精度或长精度加法执行。 S / 390十六进制四进制字格式比二进制格式更容易实现，因为它具有112位有效位数，并且可以轻松地分为两个56位的部分。但是一个113位的有效位数只会超过两个分区，需要三分之一。对于扩展精度乘法，每个分区彼此相乘，因此如果有两个分区只需要四个乘法，但是对于三个分区，这增加到九个乘法。这里公开了划分方法。

7. 发明授权

US07493480B2 Method and apparatus for prefetching branch history information 失效
标题翻译：用于预取分支历史信息的方法和装置
公开(公告)号：US07493480B2
公开(公告)日：2009-02-17
申请号：US10197714
申请日：2002-07-18
申请人： Philip G. Emma , Klaus J. Getzlaff , Allan M. Hartstein , Thomas Pflueger , Thomas R. Puzak , Eric Mark Schwarz , Vijayalakshmi Srinivasan
发明人： Philip G. Emma , Klaus J. Getzlaff , Allan M. Hartstein , Thomas Pflueger , Thomas R. Puzak , Eric Mark Schwarz , Vijayalakshmi Srinivasan
IPC分类号： G06F9/00
CPC分类号： G06F9/3806
摘要： A two level branch history table (TLBHT) is substantially improved by providing a mechanism to prefetch entries from the very large second level branch history table (L2 BHT) into the active (very fast) first level branch history table (L1 BHT) before the processor uses them in the branch prediction process and at the same time prefetch cache misses into the instruction cache. The mechanism prefetches entries from the very large L2 BHT into the very fast L1 BHT before the processor uses them in the branch prediction process. A TLBHT is successful because it can prefetch branch entries into the L1 BHT sufficiently ahead of the time the entry is needed. This feature of the TLBHT is also used to prefetch instructions into the cache ahead of their use. In fact, the timeliness of the prefetches produced by the TLBHT can be used to remove most of the cycle time penalty incurred by cache misses.
摘要翻译：通过提供一种将超大型第二级分支历史表（L2 BHT）中的条目预取到活动（非常快）的第一级分支历史表（L1 BHT）中的条目之前，两级分支历史表（TLBHT）被大大改善处理器在分支预测过程中使用它们，并且同时将高速缓存未命中预取到指令高速缓存中。在处理器在分支预测过程中使用它们之前，该机制将从非常大的L2 BHT中将条目预取到非常快的L1 BHT中。 TLBHT是成功的，因为它可以在需要输入的时间之前将分支条目预取到L1 BHT中。 TLBHT的这个功能也用于在使用之前将指令预取到高速缓存中。实际上，由TLBHT产生的预取的及时性可以用来消除高速缓存未命中引起的大部分周期时间损失。

8. 发明授权

US6075937A Preprocessing of stored target routines for controlling emulation of incompatible instructions on a target processor and utilizing target processor feedback for controlling non-sequential incompatible instruction emulation 失效
公开(公告)号：US6075937A
公开(公告)日：2000-06-13
申请号：US40671
申请日：1998-03-18
申请人： Casper Anthony Scalzi , Eric Mark Schwarz , William John Starke , James Robert Urquhart , Douglas Wayne Westcott
发明人： Casper Anthony Scalzi , Eric Mark Schwarz , William John Starke , James Robert Urquhart , Douglas Wayne Westcott
IPC分类号： G06F9/455
CPC分类号： G06F9/455
摘要： Preprocessing emulation methods utilizing search argument controls for a template routine address table in a target computing system. Target routines are stored in a target computing system for emulating incompatible instructions of an incompatible architecture which need not be recognized by the architecture of the target computing system. Preprocessing of template routines is preferrably executed on an Auxiliary Emulation Processor (AEP) which may access and patch (modify) some or all of the target instructions in any selected target routine and send them through a queue to a target processor for execution. Execution of the target routines on a target processor emulates the execution of incompatible instructions in an incompatible program in the incompatible architecture. The target processor feeds back results from the execution of target routines to modify any search argument being generated for a currently accessed incompatible instruction to allow the preprocessing selection among multiple target routines for any incompatible instruction currently executing on the target processor to represent any mode or state set by for the incompatible instruction. Another type of feed back from a currently executing target template routine enables non-sequential virtual addressing selection by the preprocessor's access of incompatible instructions during execution of the incompatible program to support incompatible instruction branches and incompatible authority controls. End routine controls are provided in the template routines for feedback synchronization of the accessing of each next incompatible instruction with execution results of each current incompatible instruction having its tempate routine currently executed by the target processor.

9. 发明授权

US5903479A Method and system for executing denormalized numbers 失效
标题翻译：执行非正规化数字的方法和系统
公开(公告)号：US5903479A
公开(公告)日：1999-05-11
申请号：US922191
申请日：1997-09-02
申请人： Eric Mark Schwarz , Bruce Giamei , Christopher A. Krygowski , Mark Anthony Check , John Stephen Liptay
发明人： Eric Mark Schwarz , Bruce Giamei , Christopher A. Krygowski , Mark Anthony Check , John Stephen Liptay
IPC分类号： G06F5/01 , G06F9/38
CPC分类号： G06F5/012 , G06F9/3861 , G06F9/3875 , G06F2207/3884
摘要： A method and system for processing instructions in a floating point unit for executing denormalized numbers in floating point pipeline via serializing uses an instruction unit and having a control unit and a pipelined data flow unit, a shifter and a rounding unit. The floating point unit has an external feedback path for providing intermediate result data from said rounding unit to an input of the pipelined data flow unit to reuse the pipeline for denormalization by passing intermediate results in the pipeline which have a denormalized condition computed after the exponent calculation of the shifting circuit directly from the rounding unit to the top of the dataflow in the pipeline via an external feedback path. The pipelined has two paths which are selected based on the presence of other instructions in the pipeline. If no other instructions are in the pipeline a first path is taken which uses the external feedback path from the rounding unit back into the top of the dataflow. When there are instructions in the pipeline a shifter unit performing normalization of the fraction indicates possible underflow of the exponent, and prepares to hold the exponent and the fraction in a floating point data flow register; and upon detection of exponent underflow during the rounder stage and detection of any other instructions in pipeline; then the control unit forces an interrupt for serialization, and cancels execution of this instruction and other instructions in pipeline.
摘要翻译：用于处理浮点单元中的指令的方法和系统，用于通过串行化来执行浮点流水线中的非正规化数字，使用指令单元并具有控制单元和流水线数据流单元，移位器和舍入单元。浮点单元具有用于将来自所述舍入单元的中间结果数据提供给流水线数据流单元的输入的外部反馈路径，以通过将具有在指数计算之后计算的非归一化状态的流水线中的中间结果重新使用来进行非规范化的移位电路通过外部反馈路径直接从舍入单元到流水线中的数据流的顶部。流水线有两个路径，这些路径是根据流水线中其他指令的存在而选择的。如果没有其他指令在流水线中，则采用第一路径，其使用从舍入单元返回到数据流的顶部的外部反馈路径。当在流水线中存在指令时，执行分数的归一化的移位单元指示指数的可能下溢，并准备将指数和分数保持在浮点数据流寄存器中; 并且在更整理阶段检测到指数下溢并检测管道中的任何其他指令; 那么控制单元强制中断进行串行化，并取消执行该指令和其他指令。

10. 发明授权

US6105126A Address bit decoding for same adder circuitry for RXE instruction format with same XBD location as RX format and dis-jointed extended operation code 失效
标题翻译：地址比特解码用于RXE指令格式的相同加法器电路，具有与RX格式相同的XBD位置和解码的扩展操作码
公开(公告)号：US6105126A
公开(公告)日：2000-08-15
申请号：US70359
申请日：1998-04-30
申请人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
发明人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
IPC分类号： G06F9/355 , G06F9/30 , G06F9/318 , G06F9/38 , G06F9/34
CPC分类号： G06F9/355 , G06F9/30185
摘要： A computer processor floating point processor six cycle pipeline system where instruction text is fetched prior to the first cycle and decoded during the first cycle for the fetched particular instruction and the base (B) and index (X) register values are read for use in address generation. RXE Instructions are of the RX-type but extended by placing the extension of the operation code beyond the first four bytes of the instruction format and to assign the operation codes in such a way that the machine may determine the exact format from the first 8 bits of the operation code alone. ESA/390 instructions SS, RR; RX; S; RRE; RI; and the new RXE instructions have a format which can be used for fixed point processing as well as floating point processing where instructions of the RXE format have their R1, X2, B2, and D2 fields in the identical positions in said instruction register as in the RX format to enable the processor to determine from the first 8 bits of the operation code alone that an instruction being decoded is an RXE format instruction and the register indexed extensions of the RXE format instruction, after which it gates the correct information to said X-B-D adder. During the second cycle the address add of B+X+Displacement is performed and sent to the cache processor's, and during the third and fourth cycles the cache is respectively accessed and data is returned, and during a fifth cycle execution of the fetched instruction occurs with the result putaway in a sixth cycle.
摘要翻译：计算机处理器浮点处理器六循环流水线系统，其中指令文本在第一周期之前获取并且在第一周期期间被解码用于所提取的特定指令，并且基准（B）和索引（X）寄存器值被读取用于地址代。 RXE指令是RX型，但通过将操作码的扩展置于指令格式的前四个字节之外进行扩展，并以这样的方式分配操作码，使得机器可以从前8位确定确切的格式的操作代码。 ESA / 390指令SS，RR; RX; S; RRE; RI; 并且新的RXE指令具有可用于固定点处理以及浮点处理的格式，其中RXE格式的指令在所述指令寄存器中的相同位置具有其R1，X2，B2和D2字段，如 RX格式，使处理器能够从操作代码的前8位确定正在解码的指令是RXE格式指令和RXE格式指令的寄存器索引扩展，之后它将正确信息锁定到所述XBD加法器。在第二周期期间，执行B + X +位移的地址添加并发送到高速缓存处理器，并且在第三和第四周期期间，分别访问高速缓存并返回数据，并且在第五周期期间执行所取出的指令结果放在第六个周期。

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