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1. 发明申请

US20090302929A1 Methods and Apparatus for Varying a Supply Voltage or Reference Voltage Using Independent Control of Diode Voltage in Asymmetrical Double-Gate Devices 有权
标题翻译：使用非对称双栅极器件中二极管电压的独立控制改变电源电压或参考电压的方法和装置
公开(公告)号：US20090302929A1
公开(公告)日：2009-12-10
申请号：US12511658
申请日：2009-07-29
申请人： Ching-Te Kent Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
发明人： Ching-Te Kent Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03K3/01
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
摘要翻译：提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。提供由电源电压和参考电压中的一个或多个控制的集成电路。集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。独立控制可以包括例如背栅偏置。独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。

2. 发明申请

US20090303778A1 Methods and Apparatus for Varying a Supply Voltage or Reference Voltage Using Independent Control of Diode Voltage in Asymmetrical Double-Gate Devices 审中-公开
公开(公告)号：US20090303778A1
公开(公告)日：2009-12-10
申请号：US12511666
申请日：2009-07-29
申请人： Ching-Te Kent Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
发明人： Ching-Te Kent Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G11C11/00
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

3. 发明授权

US09076509B2 Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices 有权
标题翻译：使用不对称双栅极器件中二极管电压的独立控制来改变电源电压或参考电压的方法和装置
公开(公告)号：US09076509B2
公开(公告)日：2015-07-07
申请号：US12511666
申请日：2009-07-29
申请人： Ching-Te Kent Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
发明人： Ching-Te Kent Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G11C11/00 , G11C5/14 , G11C11/412 , G11C11/417
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
摘要翻译：提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。提供由电源电压和参考电压中的一个或多个控制的集成电路。集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。独立控制可以包括例如背栅偏置。独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。

4. 发明授权

US07952422B2 Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices 有权
标题翻译：使用不对称双栅极器件中二极管电压的独立控制来改变电源电压或参考电压的方法和装置
公开(公告)号：US07952422B2
公开(公告)日：2011-05-31
申请号：US12511658
申请日：2009-07-29
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03K3/01
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
摘要翻译：提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。提供由电源电压和参考电压中的一个或多个控制的集成电路。集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。独立控制可以包括例如背栅偏置。独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。

5. 发明申请

US20090302894A1 DUAL GATE TRANSISTOR KEEPER DYNAMIC LOGIC 有权
标题翻译：双门晶体管保持器动态逻辑
公开(公告)号：US20090302894A1
公开(公告)日：2009-12-10
申请号：US11859351
申请日：2007-09-21
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Kevin John Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Kevin John Nowka
IPC分类号： H03K19/20 , H03K19/096
CPC分类号： H03K19/0963
摘要： A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.
摘要翻译：动态逻辑门具有用于在时钟的预充电阶段对动态节点充电的装置。逻辑树在时钟的评估阶段使用设备来评估动态节点。动态节点具有保持器电路，其包括反相器，其输入耦合到动态节点，其输出耦合到双栅极PFET器件的背栅极。双栅极PFET的源极耦合到电源，并且其漏极耦合到形成半锁存器的动态节点。双栅极PFET的前栅极耦合到具有模式输入和逻辑输入的逻辑电路，逻辑输入耦合回到感测动态节点的状态的节点。模式输入可能是缓慢的模式，以保持动态节点状态或时钟延迟，在评估后打开强守护者。

6. 发明授权

US07265589B2 Independent gate control logic circuitry 失效
标题翻译：独立门控逻辑电路
公开(公告)号：US07265589B2
公开(公告)日：2007-09-04
申请号：US11168717
申请日：2005-06-28
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Kevin John Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Kevin John Nowka
IPC分类号： H03K19/20 , H03K19/094 , H03K19/00 , H03K19/096
CPC分类号： H03K19/0963
摘要： A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combination of the logic inputs. The logic tree has a stacked configuration with at least one multi-gate FEAT device for coupling an intermediate node of the logic tree to the dynamic node in response to a first logic input of the plurality of logic inputs or in response to the pre-charge phase of the clock signal. The multi-gate FEAT device has one gate coupled to the first logic input and a second gate coupled to a complement of the clock signal used to pre-charge the dynamic node.
摘要翻译：动态逻辑门具有响应于时钟信号的预充电阶段和具有多个逻辑输入的逻辑树预充电的动态节点，用于在响应于时钟信号的时钟信号的估计阶段期间评估动态节点逻辑输入的布尔组合。逻辑树具有堆叠配置，其具有至少一个多栅极FEAT装置，用于响应于多个逻辑输入的第一逻辑输入或响应于预充电而将逻辑树的中间节点耦合到动态节点时钟信号的相位。多栅极FEAT器件具有耦合到第一逻辑输入的一个栅极和耦合到用于对动态节点预充电的时钟信号的补码的第二栅极。

7. 发明授权

US07336105B2 Dual gate transistor keeper dynamic logic 有权
标题翻译：双栅晶体管保持器动态逻辑
公开(公告)号：US07336105B2
公开(公告)日：2008-02-26
申请号：US11168692
申请日：2005-06-28
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Kevin John Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Kevin John Nowka
IPC分类号： H03K19/20 , H03K19/094 , H01L21/84
CPC分类号： H03K19/0963
摘要： A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.
摘要翻译：动态逻辑门具有用于在时钟的预充电阶段对动态节点充电的装置。逻辑树在时钟的评估阶段使用设备来评估动态节点。动态节点具有保持器电路，其包括反相器，其输入耦合到动态节点，其输出耦合到双栅极PFET器件的背栅极。双栅极PFET的源极耦合到电源，并且其漏极耦合到形成半锁存器的动态节点。双栅极PFET的前栅极耦合到具有模式输入和逻辑输入的逻辑电路，逻辑输入耦合回到感测动态节点的状态的节点。模式输入可能是缓慢的模式，以保持动态节点状态或时钟延迟，在评估后打开强守护者。

8. 发明授权

US07876131B2 Dual gate transistor keeper dynamic logic 有权
标题翻译：双栅晶体管保持器动态逻辑
公开(公告)号：US07876131B2
公开(公告)日：2011-01-25
申请号：US11859351
申请日：2007-09-21
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Kevin John Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Kevin John Nowka
IPC分类号： H03K19/20 , H03K19/094 , H01L21/84
CPC分类号： H03K19/0963
摘要： A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.
摘要翻译：动态逻辑门具有用于在时钟的预充电阶段对动态节点充电的装置。逻辑树在时钟的评估阶段使用设备来评估动态节点。动态节点具有保持器电路，其包括反相器，其输入耦合到动态节点，其输出耦合到双栅极PFET器件的背栅极。双栅极PFET的源极耦合到电源，并且其漏极耦合到形成半锁存器的动态节点。双栅极PFET的前栅极耦合到具有模式输入和逻辑输入的逻辑电路，逻辑输入耦合回到感测动态节点的状态的节点。模式输入可能是缓慢的模式，以保持动态节点状态或时钟延迟，在评估后打开强守护者。

9. 发明授权

US07382162B2 High-density logic techniques with reduced-stack multi-gate field effect transistors 有权
标题翻译：具有减少堆叠多栅极场效应晶体管的高密度逻辑技术
公开(公告)号：US07382162B2
公开(公告)日：2008-06-03
申请号：US11181954
申请日：2005-07-14
申请人： Meng-Hsueh Chiang , Ching-Te Kent Chuang , Keunwoo Kim
发明人： Meng-Hsueh Chiang , Ching-Te Kent Chuang , Keunwoo Kim
IPC分类号： H03K19/20 , H03K19/094
CPC分类号： H03K19/0948 , H01L29/78648
摘要： Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.
摘要翻译：提供了在由逻辑门形成的逻辑电路中采用多栅极场效应晶体管（FETS）的技术。只有当两个晶体管栅极有效时才导通的双栅极晶体管可以用于减少逻辑门串联或“堆叠”部分所需的器件数量。可以减小电路面积，提高性能。

10. 发明申请

US20100026346A1 HIGH-DENSITY LOGIC TECHNIQUES WITH REDUCED-STACK MULTI-GATE FIELD EFFECT TRANSISTORS 有权
标题翻译：具有减少堆叠多栅极场效应晶体管的高密度逻辑技术
公开(公告)号：US20100026346A1
公开(公告)日：2010-02-04
申请号：US12102097
申请日：2008-04-14
申请人： Meng-Hsueh Chiang , Ching-Te Kent Chuang , Keunwoo Kim
发明人： Meng-Hsueh Chiang , Ching-Te Kent Chuang , Keunwoo Kim
IPC分类号： H03K19/094 , G06F17/50
CPC分类号： H03K19/0948 , H01L29/78648
摘要： Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.
摘要翻译：提供了在由逻辑门形成的逻辑电路中采用多栅极场效应晶体管（FETS）的技术。只有当两个晶体管栅极有效时才导通的双栅极晶体管可以用于减少逻辑门串联或“堆叠”部分所需的器件数量。可以减小电路面积，提高性能。

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