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21. 发明申请

US20050244304A1 Tailored and uniform coatings in microchannel apparatus 有权
标题翻译：微通道设备中定制均匀的涂层
公开(公告)号：US20050244304A1
公开(公告)日：2005-11-03
申请号：US11089440
申请日：2005-03-23
申请人： Anna Tonkovich , Barry Yang , Terry Mazanec , Francis Daly , Sean Fitzgerald , Ravi Arora , Dongming Qiu , Bin Yang , Steven Perry , Kai Jarosh , Paul Neagle , David Hesse , Rachid Taha , Richard Long , Jeff Marco , Thomas Yuschak , Jeffrey Ramler , Mike Marchiando
发明人： Anna Tonkovich , Barry Yang , Terry Mazanec , Francis Daly , Sean Fitzgerald , Ravi Arora , Dongming Qiu , Bin Yang , Steven Perry , Kai Jarosh , Paul Neagle , David Hesse , Rachid Taha , Richard Long , Jeff Marco , Thomas Yuschak , Jeffrey Ramler , Mike Marchiando
IPC分类号： B01J19/00 , B01J35/04 , B01J37/02 , B01L3/00 , C23C10/50 , C23C16/04
CPC分类号： B01J37/0226 , B01J19/0093 , B01J35/04 , B01J37/0215 , B01J37/0238 , B01J2219/00783 , B01J2219/00822 , B01J2219/00824 , B01J2219/00835 , B01J2219/00837 , B01J2219/00873 , B01J2219/00891 , B01J2219/00905 , B01J2219/00995 , B01L3/502707 , B01L3/502746 , B01L2200/12 , B01L2300/16 , B01L2400/0406 , B01L2400/086 , B01L2400/088
摘要： Interior microchannels within microchannel apparatus are uniformly coated. Remarkably, these uniform coatings are formed from materials that are applied to the interior microchannels after an apparatus has been assembled or manufactured. Coatings can be made uniform along the length of a microchannel, in the corner of a microchannel, and/or throughout numerous microchannels in an array of microchannels. Techniques for tailoring the application of washcoats onto microchannels is also described.
摘要翻译：微通道设备内部的微通道均匀涂覆。值得注意的是，这些均匀的涂层由在装置组装或制造之后施加到内部微通道的材料形成。涂层可以沿着微通道的长度，微通道的角部和/或整个微通道阵列中的许多微通道而均匀。还描述了将洗衣布应用于微通道的技术。

22. 发明授权

US08825730B1 Matrix decomposition using dataflow techniques 有权
标题翻译：使用数据流技术进行矩阵分解
公开(公告)号：US08825730B1
公开(公告)日：2014-09-02
申请号：US13252562
申请日：2011-10-04
申请人： Steven Perry , Coleman C. Cheung
发明人： Steven Perry , Coleman C. Cheung
IPC分类号： G06F17/16
CPC分类号： G06F17/16
摘要： Efficient and scalable circuitry for performing Cholesky decomposition is based on a dataflow style architecture which uses self-timed circuitry and eliminates the need for complicated state machines. Calculations are ordered such that partial sums of products are created in parallel subject to data dependency requirements, allowing a single accumulator to perform the summation. A Vector FIFO receives a partial sum of products from a vector processing engine. A Feedback FIFO stores partial results and feeds the partial results back to the data path based on signals from a dataflow controller. The circuitry is flexible to allow different matrix sizes, speed grades, and target frequencies without recompilation.
摘要翻译：用于执行Cholesky分解的高效和可扩展的电路基于使用自定时电路的数据流风格架构，并且不需要复杂的状态机。按照数据依赖性要求并行创建产品的部分和来进行计算，允许单个累加器执行求和。向量FIFO从矢量处理引擎接收产品的部分和。反馈FIFO存储部分结果，并且基于来自数据流控制器的信号将部分结果反馈给数据路径。该电路灵活，允许不同的矩阵尺寸，速度等级和目标频率，无需重新编译。

23. 发明授权

US08793629B1 Method and apparatus for implementing carry chains on FPGA devices 有权
标题翻译：用于在FPGA器件上实现进位链的方法和装置
公开(公告)号：US08793629B1
公开(公告)日：2014-07-29
申请号：US12987519
申请日：2011-01-10
申请人： Steven Perry
发明人： Steven Perry
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5054
摘要： A method for designing a system to be implemented on a field programmable gate array (FPGA) includes identifying an adder from an intermediate representation of the system. Components on the target device are designated to support and implement the adder as a partitioned adder having a plurality of sub-adders each registering an intermediate result.
摘要翻译：用于设计要在现场可编程门阵列（FPGA）上实现的系统的方法包括从系统的中间表示识别加法器。目标设备上的组件被指定为支持并实现加法器作为具有多个分别加入中间结果的子加法器的分区加法器。

24. 发明授权

US08739108B1 Method and apparatus for implementing loop-based control in an electronic design automation tool 有权
标题翻译：在电子设计自动化工具中实现循环控制的方法和装置
公开(公告)号：US08739108B1
公开(公告)日：2014-05-27
申请号：US13199588
申请日：2011-09-03
申请人： Steven Perry , Simon Finn
发明人： Steven Perry , Simon Finn
IPC分类号： G06F15/04 , G06F17/50
CPC分类号： G06F17/5045
摘要： A selectable block in a graphical user interface of an electric design automation tool for generating a design of a system on a target device includes a token passing unit operable to pass a token through one of a first output port and second output port in response to a result from a loop test. The selectable block also includes a counter operable to increment a step value in response to the selectable block receiving the token at a first input port.
摘要翻译：用于在目标设备上生成系统的设计的电气设计自动化工具的图形用户界面中的可选块包括令牌传递单元，其可操作以响应于第一输出端口和第二输出端口将令牌传递通过第一输出端口和第二输出端口中的一个来自循环测试。可选块还包括计数器，可操作以响应于在第一输入端口处接收令牌的可选择块增加步长值。

25. 发明授权

US08499262B1 Method and apparatus for implementing a parameterizable filter block with an electronic design automation tool 有权
标题翻译：用电子设计自动化工具实现可参数化过滤块的方法和装置
公开(公告)号：US08499262B1
公开(公告)日：2013-07-30
申请号：US12807959
申请日：2010-09-17
申请人： Steven Perry
发明人： Steven Perry
IPC分类号： G06F17/50 , G06F9/455 , G06F11/22
CPC分类号： G06F17/5045 , H03H17/0294 , H03H17/0664
摘要： An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array. (FPGA) includes a graphical user interface to create a block based schematic. The EDA tool includes a library that includes a parameterizable filter block selectable by a designer to include in the block based schematic to represent a component in the design that filters data. The EDA tool includes a design adjustment unit to automatically modify previously programmed and selected components and wires in the block based schematic without input from the designer upon determining a change made to the parameterizable filter block by the designer.
摘要翻译：一种用于在现场可编程门阵列上生成系统设计的电气设计自动化（EDA）工具。（FPGA）包括用于创建基于块的原理图的图形用户界面。 EDA工具包括一个库，其中包括可由设计者选择的可参数化过滤器块，以包含在基于块的原理图中，以表示过滤数据的设计中的组件。 EDA工具包括设计调整单元，用于在确定由设计者对可参数化滤波器块进行的改变时，自动修改基于块的原理图中的先前编程和选择的部件和导线，而无需设计者的输入。

26. 发明授权

US08468476B1 Method and apparatus for designing a system on multiple field programmable gate array device types 有权
公开(公告)号：US08468476B1
公开(公告)日：2013-06-18
申请号：US13053178
申请日：2011-03-21
申请人： Steven Perry
发明人： Steven Perry
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054
摘要： A method for designing a system to be implemented on a target device includes generating a register transfer language (RTL) representation of the system from a description of the system without pipelined delays. The RTL representation of the system includes pipelined delays to facilitate timing of the system as implemented on a target device identified by a designer.

27. 发明授权

US07895549B1 Method and apparatus for implementing a processor interface block with an electronic design automation tool 有权
标题翻译：一种用电子设计自动化工具实现处理器接口块的方法和装置
公开(公告)号：US07895549B1
公开(公告)日：2011-02-22
申请号：US11986606
申请日：2007-11-23
申请人： Steven Perry
发明人： Steven Perry
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/68
摘要： An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array (FPGA) includes a library that includes a processor interface block selectable by a designer to represent a component in the design that is accessible to a processor. The EDA tool also includes a processor interface circuitry generation unit to automatically generate circuitry in the design to support the processor interface block without input from the designer.
摘要翻译：用于在现场可编程门阵列（FPGA）上生成系统设计的电气设计自动化（EDA）工具包括一个库，其包括由设计者可选择的处理器接口块，以表示处理器可访问的设计中的组件。 EDA工具还包括处理器接口电路生成单元，用于在设计中自动生成电路以支持处理器接口块，而无需设计者的输入。

28. 发明申请

US20070140955A1 MICROCHANNEL WITH INTERNAL FIN SUPPORT FOR CATALYST OR SORPTION MEDIUM 有权
标题翻译：具有内部FIN支持的微型通道用于催化剂或吸附介质
公开(公告)号：US20070140955A1
公开(公告)日：2007-06-21
申请号：US11617158
申请日：2006-12-28
申请人： Anna Tonkovich , Dongming Qiu , Richard Long , Barry Yang , Thomas Yuschak , Steven Perry
发明人： Anna Tonkovich , Dongming Qiu , Richard Long , Barry Yang , Thomas Yuschak , Steven Perry
IPC分类号： C01B3/26
CPC分类号： C01B3/386 , B01D53/02 , B01D53/0407 , B01D53/0446 , B01D2253/112 , B01D2253/25 , B01D2253/306 , B01D2253/34 , B01J19/0093 , B01J23/63 , B01J37/0225 , B01J37/0244 , B01J2219/00822 , B01J2219/00831 , B01J2219/00833 , B01J2219/00835 , B01J2219/00862 , B01J2219/00873 , B01J2219/00889 , C01B3/384 , C01B2203/00 , C01B2203/0233 , C01B2203/0261 , C01B2203/0844 , C01B2203/0872 , C01B2203/0883 , C01B2203/0894 , C01B2203/1011 , C01B2203/1023 , C01B2203/1029 , C01B2203/1035 , C01B2203/1052 , C01B2203/1064 , C01B2203/1082 , C01B2203/1094 , C01B2203/1211 , C01B2203/1241 , C01B2203/1247 , C01B2203/141 , C01B2203/1633 , C01B2203/82 , C07C45/46 , F28F3/048 , F28F21/065 , F28F2255/06 , F28F2260/02 , Y02C20/20 , Y02P20/52
摘要： This invention relates to an apparatus, comprising: at least one process microchannel having a height, width and length, the height being up to about 10 mm, the process microchannel having a base wall extending in one direction along the width of the process microchannel and in another direction along the length of the process microchannel; at least one fin projecting into the process microchannel from the base wall and extending along at least part of the length of the process microchannel; and a catalyst or sorption medium supported by the fin.
摘要翻译：本发明涉及一种装置，包括：至少一个具有高度，宽度和长度的工艺微通道，高度高达约10mm，工艺微通道具有沿着工艺微通道的宽度沿一个方向延伸的底壁，以及沿着工艺微通道长度的另一个方向; 至少一个翅片，其从所述底壁突出到所述工艺微通道中并沿所述工艺微通道的长度的至少一部分延伸; 以及由翅片支撑的催化剂或吸附介质。

29. 发明授权

US07234044B1 Processor registers having state information 有权
标题翻译：具有状态信息的处理器寄存器
公开(公告)号：US07234044B1
公开(公告)日：2007-06-19
申请号：US10727850
申请日：2003-12-03
申请人： Steven Perry
发明人： Steven Perry
IPC分类号： G06F9/302 , G06F9/30
CPC分类号： G06F9/3851 , G06F9/30094 , G06F9/30105 , G06F9/3012 , G06F9/30123 , G06F9/321 , G06F9/3867
摘要： Methods and apparatus are provided for implementing an efficient processor having state information included in each register. A processor has registers configured to hold both data and state information, such as carry and overflow information. State information and data can be read and written in the same operation. Holding state information along with data in the same register can provide a variety of benefits, particularly in the context of multithreaded programmable chips.
摘要翻译：提供了用于实现具有包括在每个寄存器中的状态信息的有效处理器的方法和装置。处理器具有被配置为保持数据和状态信息（诸如进位和溢出信息）的寄存器。状态信息和数据可以在相同的操作中进行读写。保持状态信息以及同一寄存器中的数据可以提供各种好处，特别是在多线程可编程芯片的上下文中。

30. 发明申请

US20070085227A1 Multi-phase contacting process using microchannel technology 审中-公开
标题翻译：使用微通道技术的多相接触过程
公开(公告)号：US20070085227A1
公开(公告)日：2007-04-19
申请号：US11483136
申请日：2006-07-07
申请人： Anna Tonkovich , Maddalena Fanelli , Ravi Arora , Timothy Sullivan , Steven Perry , David Kuhlmann
发明人： Anna Tonkovich , Maddalena Fanelli , Ravi Arora , Timothy Sullivan , Steven Perry , David Kuhlmann
IPC分类号： B01F3/04 , F28D7/00
CPC分类号： B01F3/04468 , B01D1/14 , B01D19/0031 , B01F5/061 , B01F13/0059 , B01F2005/0621 , B01F2005/0636 , F25J3/0219 , F25J3/0238 , F25J3/0295 , F25J3/04624 , F25J3/04896 , F25J2200/90 , F25J2210/12 , F25J2215/62 , F25J2290/44
摘要： The disclosed technology relates to a process for contacting a liquid phase and a second fluid phase, comprising: flowing the liquid phase and/or second fluid phase in a process microchannel in contact with surface features in the process microchannel, the contacting of the surface features with the liquid phase and/or second fluid phase imparting a disruptive flow to the liquid phase and/or second fluid phase; contacting the liquid phase with the second fluid phase in the process microchannel; and transferring mass from the liquid phase to the second fluid phase and/or from the second fluid phase to the liquid phase.
摘要翻译：所公开的技术涉及一种用于使液相和第二流体相接触的方法，包括：将液相和/或第二流体相流动在与工艺微通道中的表面特征接触的工艺微通道中，使表面特征液相和/或第二流体相向液相和/或第二流体相施加破坏性流动; 使液相与工艺微通道中的第二流体相接触; 并将质量从液相转移到第二流体相和/或从第二流体相转移到液相。

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