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21. 发明申请

US20130243107A1 BAUD RATE TIMING RECOVERY FOR NYQUIST PATTERNS IN A COMMUNICATION SYSTEM 审中-公开
标题翻译：通信系统中NYQUIC模式的波特率时间恢复
公开(公告)号：US20130243107A1
公开(公告)日：2013-09-19
申请号：US13422259
申请日：2012-03-16
申请人： Erik V. Chmelar , Choshu Ito
发明人： Erik V. Chmelar , Choshu Ito
IPC分类号： H04L27/06 , H04L27/04
CPC分类号： H04L7/033 , H04L7/046 , H04L25/03057
摘要： Described embodiments recover timing data from a received signal. An analog-to-digital converter (ADC) generates a value for each sample of the signal at a sample phase. A phase detector selects a window of n received bit samples, where n is a positive integer. If the bit window includes any Nyquist patterns, the phase detector enables a bang-bang trap. The bang-bang-trap iteratively, for each bit transition between a first consecutive bit and a second consecutive bit in the Nyquist patterns, samples the received signal at a zero crossing between the first and second consecutive bits and determines the polarity of the bit transition. Based on the polarity of the bit transition and the sample value at the zero crossing, the bang-bang trap determines whether the sample phase of the bit sample for the second consecutive bit is correct. If the sample phase is incorrect, the bang-bang trap adjusts the sample phase.
摘要翻译：所描述的实施例从接收到的信号中恢复定时数据。模拟数字转换器（ADC）在样本阶段产生每个信号样本的值。相位检测器选择n个接收位样本的窗口，其中n是正整数。如果位窗口包括任何奈奎斯特图案，则相位检测器能够进行爆炸陷阱。迭代地，对于奈奎斯特图案中的第一连续位和第二连续位之间的每个位转换，对第一和第二连续位之间的零交叉处的接收信号进行采样，并确定位转换的极性。基于位过渡的极性和过零点处的采样值，爆炸阱确定第二个连续位的位采样的采样相位是否正确。如果样品相不正确，则爆炸阱会调整样品相。

22. 发明申请

US20100195776A1 Systems and Methods for Synchronous, Retimed Analog to Digital Conversion 失效
标题翻译：用于同步，重定时模数转换的系统和方法
公开(公告)号：US20100195776A1
公开(公告)日：2010-08-05
申请号：US12669482
申请日：2008-06-06
申请人： Erik Chmelar , Choshu Ito , William Loh
发明人： Erik Chmelar , Choshu Ito , William Loh
IPC分类号： H04L7/02 , H03K5/153
CPC分类号： H03M1/1215 , H03M1/002 , H03M1/361
摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch.
摘要翻译：本发明的各种实施例提供了用于模数转换的系统和方法。例如，公开了一种基于锁存器的模数转换器，其包括与一组比较器的第一交错，选择器电路和锁存器。该组比较器可操作以将模拟输入与相应的参考电压进行比较，并且与时钟相位同步。选择器电路可操作以至少部分地基于选择器输入来选择该组比较器之一的输出。从所选择的输出中导出第一交错输出。锁存器接收来自第二交错的第二交织输出，并且在时钟相位被断言时是透明的。选择器输入包括锁存器的输出。

23. 发明申请

US20090267821A1 Analog-to-Digital Converter 有权
标题翻译：模数转换器
公开(公告)号：US20090267821A1
公开(公告)日：2009-10-29
申请号：US12108791
申请日：2008-04-24
申请人： Erik Chmelar , Choshu Ito
发明人： Erik Chmelar , Choshu Ito
IPC分类号： H03M1/36
CPC分类号： H03M1/182 , H03M1/002 , H03M1/004 , H03M1/361 , H03M1/367
摘要： An ADC circuit includes multiple comparators and a controller coupled to the comparators. Each of the comparators is operative to generate an output indicative of a difference between a first signal representative of an input signal applied to the ADC circuit and a corresponding reference signal. The controller is operative to perform at least one of: (i) activating a subset of the comparators during a given sample period being; and (ii) controlling levels of the corresponding reference signals of the comparators as a function of a level of the input signal. A number of active comparators during the given sample period is no greater than one less than a number of regions into which the input signal is quantized.
摘要翻译： ADC电路包括多个比较器和耦合到比较器的控制器。每个比较器可操作以产生指示表示施加到ADC电路的输入信号的第一信号与对应的参考信号之间的差的输出。控制器可操作以执行以下至少之一：（i）在给定的采样周期期间激活比较器的子集; 和（ii）根据输入信号的电平来控制比较器的相应参考信号的电平。给定采样周期内的多个有源比较器不小于输入信号被量化的区域数量的一个。

24. 发明申请

US20070138973A1 Electrostatic discharge series protection 失效
标题翻译：静电放电系列保护
公开(公告)号：US20070138973A1
公开(公告)日：2007-06-21
申请号：US11300938
申请日：2005-12-15
申请人： William Loh , Choshu Ito , Jau-Wen Chen
发明人： William Loh , Choshu Ito , Jau-Wen Chen
IPC分类号： H05B37/00
CPC分类号： H01L27/0248
摘要： An improvement to a digital integrated circuit of the type having a functional circuit that is susceptible to damage from an electrostatic discharge. An electrostatic discharge protection element is placed in series with the functional circuit and disposed upstream in a normal direction of current flow from the functional circuit. The electrostatic discharge protection element includes at least one of a resistive choke that exhibits thermal runaway and an inductive choke.
摘要翻译：对具有易受静电放电损坏的功能电路的类型的数字集成电路的改进。静电放电保护元件与功能电路串联放置并且设置在来自功能电路的电流的正常方向的上游。静电放电保护元件包括具有热失控的电阻扼流圈和感应扼流圈中的至少一个。

25. 发明申请

US20060245127A1 CDM ESD event simulation and remediation thereof in application circuits 失效
标题翻译： CDM ESD事件模拟及其在应用电路中的修复
公开(公告)号：US20060245127A1
公开(公告)日：2006-11-02
申请号：US11349358
申请日：2006-02-07
申请人： Choshu Ito , Li Ooi , William Loh
发明人： Choshu Ito , Li Ooi , William Loh
IPC分类号： H02H9/00
CPC分类号： G06F17/5036
摘要： Methods and structure for improved simulation of CDM ESD events and for remediation of circuit designs correcting for previously inexplicable damage to core circuits of an application circuit design caused by such events. Features and aspects hereof note that such previously inexplicable damage to core circuits of an application circuit design is caused by inductive coupling between the non-core circuits and the core circuits of an application circuit design. Improved simulation techniques in accordance with features and aspects hereof may predict where such inductive coupling may cause damage to core circuits. Other features and aspects hereof may alter an application circuit design to provide remediation by automated insertion of additional buffer circuitry to core traces of the core circuitry that may be impacted by such inductive coupling.
摘要翻译：改进CDM ESD事件仿真和修复电路设计的方法和结构，以纠正由此类事件引起的应用电路设计对核心电路的以前不可思议的损害。本发明的特征和方面注意到，对应用电路设计的核心电路的这种以前的莫名其妙的损害是由非核心电路和应用电路设计的核心电路之间的电感耦合引起的。根据其特征和方面的改进的仿真技术可以预测这种感应耦合可能会对核心电路造成损害。本发明的其它特征和方面可以改变应用电路设计，以通过将附加的缓冲电路自动插入到可能受这种电感耦合影响的核心电路的芯线迹来提供补救。

26. 发明申请

US20060245126A1 CDM ESD event protection in application circuits 失效
公开(公告)号：US20060245126A1
公开(公告)日：2006-11-02
申请号：US11349356
申请日：2006-02-07
申请人： William Loh , Li Ooi , Choshu Ito
发明人： William Loh , Li Ooi , Choshu Ito
IPC分类号： H02H9/00
CPC分类号： G06F17/5036
摘要： Methods and structure for improved design remediation for previously inexplicable damage to core circuits of an application circuit design caused by CDM ESD events. Features and aspects hereof note that such previously inexplicable damage to core circuits of an application circuit design is caused by inductive coupling between the non-core circuits and the core circuits of an application circuit design. Features and aspects hereof automatically alter an application circuit design to provide remediation by various techniques to reduce the magnitude of such inductive coupling and to thereby reduce susceptibility of the application circuit to damage from CDM ESD events. The modifications may be enforced as rules during initial design of the application circuit or as reconfiguration of a design in response to simulation to discover inappropriate coupling in the design.

27. 发明授权

US09239896B2 Methodology for preventing functional failure caused by CDM ESD 有权
标题翻译：防止CDM ESD引起的功能障碍的方法
公开(公告)号：US09239896B2
公开(公告)日：2016-01-19
申请号：US12255002
申请日：2008-10-21
申请人： Choshu Ito , Tze Wee Chen , William Loh
发明人： Choshu Ito , Tze Wee Chen , William Loh
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5036 , G06F2217/72 , G06F2217/82
摘要： A design methodology which prevents functional failure caused by CDM ESD events. A transistor model is used to model the final states of cells, and a simulator is then used to identify invulnerable cells. Cells that are potential failure sites are then identified. The cells which have been identified as being potential victims are replaced by the previously-identified invulnerable cells that have the identical logic function. On the other hand, if a cell with identical function cannot be found, an invulnerable buffer cell (that will not effect logic function) can be inserted in front of the potential victim transistor as protection. By replacing all the potential victim cells with cells which have been determined to be invulnerable, the resulting design will be guaranteed to be CDM ESD tolerant.
摘要翻译：一种防止CDM ESD事件引起功能故障的设计方法。晶体管模型用于对细胞的最终状态建模，然后使用模拟器来识别不可侵入的细胞。然后鉴定潜在的故障部位的细胞。被识别为潜在受害者的细胞由具有相同逻辑功能的先前识别的无形细胞所取代。另一方面，如果不能发现具有相同功能的单元，则可以在潜在的牺牲晶体管的前面插入不可变缓冲单元（不会影响逻辑功能）作为保护。通过用已被确定为无害的细胞代替所有潜在的受害细胞，所得到的设计将被保证是CDM耐受性的。

28. 发明授权

US08923382B2 Tap adaptation with a fully unrolled decision feedback equalizer 有权
标题翻译：点击适应与完全展开的决策反馈均衡器
公开(公告)号：US08923382B2
公开(公告)日：2014-12-30
申请号：US13422403
申请日：2012-03-16
申请人： Choshu Ito , Erik V. Chmelar
发明人： Choshu Ito , Erik V. Chmelar
IPC分类号： H04L25/03
CPC分类号： H04L27/01 , H04L25/03057 , H04L2025/03687 , H04L2025/037
摘要： Described embodiments adapt one or more taps of a decision feedback equalizer of a receiver by setting a reference voltage for each of one or more data recovery comparators to a corresponding predetermined initial value. The data recovery comparators generate a bit value for each sample of a received signal. A tap adaptation module of the receiver selects a window of n received bit samples. The tap adaptation module iteratively, for each of the one or more data recovery comparators, tracks (i) a detected number of bits having a logic 0 value, and (ii) a detected number of bits having a logic 1 value. The tap adaptation module adjusts, based on a ratio of the detected number of bits having a logic 0 value to the detected number of bits having a logic 1 value, the reference voltage for the corresponding data recovery comparator by a predetermined step amount.
摘要翻译：描述的实施例通过将一个或多个数据恢复比较器中的每一个的参考电压设置为相应的预定初始值来适配接收机的判决反馈均衡器的一个或多个抽头。数据恢复比较器为接收信号的每个采样产生一个位值。接收机的抽头适配模块选择n个接收位样本的窗口。对于一个或多个数据恢复比较器中的每一个，迭代地分接自适应模块，跟踪（i）具有逻辑0值的检测到的比特数，以及（ii）具有逻辑1值的检测到的比特数。抽头适配模块基于检测到的具有逻辑0值的位数与检测到的具有逻辑1值的位数的比率，将相应数据恢复比较器的参考电压调整预定步长量。

29. 发明申请

US20130243127A1 DYNAMIC DESKEW FOR BANG-BANG TIMING RECOVERY IN A COMMUNICATION SYSTEM 有权
标题翻译：用于通信系统中的BANG-BANG定时恢复的动态DESKEW
公开(公告)号：US20130243127A1
公开(公告)日：2013-09-19
申请号：US13422329
申请日：2012-03-16
申请人： Erik V. Chmelar , Choshu Ito
发明人： Erik V. Chmelar , Choshu Ito
IPC分类号： H04L27/00
CPC分类号： H04L7/033 , H04L25/03057 , H04L2025/03363
摘要： Described embodiments calibrate a sampling phase adjustment of a receiver. An analog-to-digital converter generates samples of a received signal at a sample phase. A phase detector selects a window of n samples. If the window includes a Nyquist pattern, a bang-bang trap is enabled. The bang-bang trap iteratively, for each transition between a first consecutive bit and a second consecutive bit in the Nyquist pattern, samples the received signal at a zero crossing between the first and second consecutive bits and determines the transition polarity. Based on the transition polarity and the zero crossing sample value, the bang-bang trap determines whether the sample phase is correct. If Nyquist patterns are absent from the window, a margin phase detector determines a target voltage margin value and a voltage of a cursor bit of the window. Based on the target voltage margin value and the voltage of the cursor bit, the margin phase detector determines whether the sample phase is correct.
摘要翻译：描述的实施例校准接收机的采样相位调整。模拟 - 数字转换器在采样阶段产生接收信号的采样。相位检测器选择n个样本的窗口。如果窗口包含奈奎斯特（Nyquist）模式，则会启用“爆炸”陷阱。迭代地，对于奈奎斯特图案中的第一连续位和第二连续位之间的每个转换，对第一和第二连续位之间的零交叉处的接收信号进行采样，并确定转换极性。基于过渡极性和零交叉采样值，轰击陷阱确定采样相位是否正确。如果窗口中不存在奈奎斯特图案，则边缘相位检测器确定窗口的目标电压余量值和光标位的电压。基于目标电压余量值和光标位电压，边缘相位检测器确定采样相位是否正确。

30. 发明申请

US20130243056A1 VOLTAGE MARGIN BASED BAUD RATE TIMING RECOVERY IN A COMMUNICATION SYSTEM 审中-公开
标题翻译：基于电压基准的波特率通信系统中的时钟恢复
公开(公告)号：US20130243056A1
公开(公告)日：2013-09-19
申请号：US13422226
申请日：2012-03-16
申请人： Erik V. Chmelar , Choshu Ito
发明人： Erik V. Chmelar , Choshu Ito
IPC分类号： H04B1/06 , H04B1/02 , H04B17/00
CPC分类号： H04L7/033
摘要： Described embodiments provide a method of recovering timing data from a received signal. An analog-to-digital converter (ADC) of a receiver generates an actual ADC value for each bit sample of a received signal. Each bit sample occurs at an associated sample phase of the receiver. A margin phase detector of the receiver recovers timing information from the received signal by determining a target voltage margin value. The margin phase detector selects a window of n received bit samples, where n is a positive integer, and determines a voltage of a cursor bit of the selected window of bit samples. The margin phase detector determines, based on the target voltage margin value and the voltage of the cursor bit, whether the sample phase is correct. If the sample phase is incorrect, the margin phase detector adjusts the sample phase of the receiver by a predetermined amount.
摘要翻译：描述的实施例提供了一种从接收信号中恢复定时数据的方法。接收机的模数转换器（ADC）为接收信号的每个位采样产生实际的ADC值。每个位采样发生在接收器的相关采样相位。接收器的边沿相位检测器通过确定目标电压余量值来从接收信号中恢复定时信息。边缘相位检测器选择n个接收位样本的窗口，其中n是正整数，并且确定所选择的位采样窗口的光标位的电压。边缘相位检测器基于目标电压余量值和光标位的电压来确定采样相位是否正确。如果采样相位不正确，则边沿相位检测器将接收器的采样相位调整预定量。

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