专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US08201111B2 Table-based DFM for accurate post-layout analysis 有权
标题翻译：基于表的DFM，用于精确的布局后分析
公开(公告)号：US08201111B2
公开(公告)日：2012-06-12
申请号：US13195907
申请日：2011-08-02
申请人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
发明人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
摘要翻译：公开了一种用于集成电路设计和后期布局分析的系统和方法。集成电路设计方法包括提供具有各种设计尺寸的多个IC器件; 收集IC器件的电气性能数据; 提取IC器件的等效尺寸; 产生形状相关模型以将等效尺寸与IC器件的电性能数据相关联; 以及使用等效尺寸和电气性能数据创建数据细化表。

22. 发明授权

US08119310B1 Mask-shift-aware RC extraction for double patterning design 有权
标题翻译：面罩移位感知RC提取双图案设计
公开(公告)号：US08119310B1
公开(公告)日：2012-02-21
申请号：US12872938
申请日：2010-08-31
申请人： Lee-Chung Lu , Yi-Kan Cheng , Hsiao-Shu Chao , Ke-Ying Su , Cheng-Hung Yeh , Dian-Hau Chen , Ru-Gun Liu , Wen-Chun Huang
发明人： Lee-Chung Lu , Yi-Kan Cheng , Hsiao-Shu Chao , Ke-Ying Su , Cheng-Hung Yeh , Dian-Hau Chen , Ru-Gun Liu , Wen-Chun Huang
IPC分类号： G03F9/00 , G06F17/50
CPC分类号： G03F1/70
摘要： A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.
摘要翻译：一种方法包括提供集成电路设计的布局，以及从布局生成多个双重图案化分解，多个双重图案化分解中的每一个包括分离到第一掩模的图案和双图案掩模组的第二掩模。确定第一和第二掩模之间的最大偏移，其中最大偏移是用于在晶片上实现布局的制造过程中的最大预期掩模移位。对于多个双重图案化分解中的每一个，使用由最大偏移限定的范围内的掩模移位来模拟最坏情况的性能值。

23. 发明授权

US08001494B2 Table-based DFM for accurate post-layout analysis 有权
标题翻译：基于表的DFM，用于精确的布局后分析
公开(公告)号：US08001494B2
公开(公告)日：2011-08-16
申请号：US12250424
申请日：2008-10-13
申请人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
发明人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
摘要翻译：公开了一种用于集成电路设计和后期布局分析的系统和方法。集成电路设计方法包括提供具有各种设计尺寸的多个IC器件; 收集IC器件的电气性能数据; 提取IC器件的等效尺寸; 产生形状相关模型以将等效尺寸与IC器件的电性能数据相关联; 以及使用等效尺寸和电气性能数据创建数据细化表。

24. 发明申请

US20110035717A1 Design Optimization for Circuit Migration 有权
标题翻译：电路迁移的设计优化
公开(公告)号：US20110035717A1
公开(公告)日：2011-02-10
申请号：US12846594
申请日：2010-07-29
申请人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu Alex Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
发明人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu Alex Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/505 , G06F17/5068 , G06F17/5072
摘要： An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.
摘要翻译：本发明的实施例是一种用于提供集成电路布局的经调整的电子表示的计算机程序产品。计算机程序产品具有其上体现计算机程序的介质。此外，计算机程序包括用于从完整节点网表提供全节点单元的计算机程序代码，用于缩放全节点单元以提供收缩节点单元的计算机程序代码，用于提供全节点单元的定时性能的计算机程序代码和收缩节点单元，用于将全节点单元的定时性能与收缩节点单元的定时性能进行比较的计算机程序代码以及用于提供第一网表的计算机程序代码。

25. 发明授权

US09672315B2 Optimization for circuit migration 有权
公开(公告)号：US09672315B2
公开(公告)日：2017-06-06
申请号：US12846594
申请日：2010-07-29
申请人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu “Alex” Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
发明人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu “Alex” Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/505 , G06F17/5068 , G06F17/5072
摘要： An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

26. 发明授权

US08751975B2 RC corner solutions for double patterning technology 有权
标题翻译：用于双重图案化技术的RC角解决方案
公开(公告)号：US08751975B2
公开(公告)日：2014-06-10
申请号：US13479076
申请日：2012-05-23
申请人： Ke-Ying Su , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Ke-Ying Su , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method includes determining model parameters for forming an integrated circuit, and generating a techfile using the model parameters. The techfile includes at least two of a C_worst table, a C_best table, and a C_nominal table. The C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other. The C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other. The techfile is embodied on a tangible non-transitory storage medium.
摘要翻译：一种方法包括确定用于形成集成电路的模型参数，以及使用模型参数生成技术文件。该技术文件包括C_worst表，C_best表和C_nominal表中的至少两个。当包括布局图案的光刻掩模相对于彼此移动时，C_worst表存储集成电路的布局图案之间的最大寄生电容。当光刻掩模相对于彼此移动时，C_best表存储布局图案之间的最小寄生电容。当光刻掩模不相对于彼此移动时，C_nominal表存储布局图案之间的标称寄生电容。该技术文件体现在有形的非暂时性存储介质上。

27. 发明授权

US08418117B2 Chip-level ECO shrink 有权
标题翻译：芯片级ECO收缩
公开(公告)号：US08418117B2
公开(公告)日：2013-04-09
申请号：US12831982
申请日：2010-07-07
申请人： Huang-Yu Chen , Ho Che Yu , Chung-Hsing Wang , Hsiao-Shu Chao , Yi-Kan Cheng , Lee-Chung Lu
发明人： Huang-Yu Chen , Ho Che Yu , Chung-Hsing Wang , Hsiao-Shu Chao , Yi-Kan Cheng , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L27/0207
摘要： In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed.
摘要翻译：在形成集成电路的方法中，提供包括第一知识产权（IP）的芯片表示的布局。生成与第一个IP重叠并从第一个IP边缘延伸出来的切割线。切割线将芯片表示划分成多个电路区域。多个电路区域相对于第一IP的位置向外偏移以产生空间。第一个IP被吹入空间，产生一个IP地址。然后执行直接收缩。

28. 发明申请

US20130014070A1 SYSTEMS AND METHODS FOR CREATING FREQUENCY-DEPENDENT NETLIST 有权
标题翻译：用于创建频率依赖的网络列表的系统和方法
公开(公告)号：US20130014070A1
公开(公告)日：2013-01-10
申请号：US13176823
申请日：2011-07-06
申请人： Ke-Ying SU , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng , Huang-Yu Chen , Chung-Hsing Wang
发明人： Ke-Ying SU , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng , Huang-Yu Chen , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5077 , G06F17/5081
摘要： A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.
摘要翻译：一种方法包括创建包括用于集成电路的数据的技术文件，所述集成电路包括耦合到插入器的至少一个管芯以及所述至少一个管芯和所述插入器之间的布线，b）创建包括接近电容或电感基于所述技术文件，在所述至少一个管芯中和所述插入器中的导体之间的耦合，c）基于所述网表来模拟所述集成电路的性能，d）基于所述网表调整所述至少一个管芯和所述插入器之间的布线模拟以减少电容或电感耦合中的至少一个，以及e）重复步骤c）和d）以优化电容或电感耦合中的至少一个。

29. 发明申请

US20110289466A1 Table-Based DFM for Accurate Post-Layout Analysis 有权
标题翻译：基于表的DFM，用于精确的后期布局分析
公开(公告)号：US20110289466A1
公开(公告)日：2011-11-24
申请号：US13195907
申请日：2011-08-02
申请人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
发明人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
摘要翻译：公开了一种用于集成电路设计和后期布局分析的系统和方法。集成电路设计方法包括提供具有各种设计尺寸的多个IC器件; 收集IC器件的电气性能数据; 提取IC器件的等效尺寸; 产生形状相关模型以将等效尺寸与IC器件的电性能数据相关联; 以及使用等效尺寸和电气性能数据创建数据细化表。

30. 发明授权

US08037575B2 Method for shape and timing equivalent dimension extraction 有权
标题翻译：形状和时间等值尺寸提取方法
公开(公告)号：US08037575B2
公开(公告)日：2011-10-18
申请号：US12211624
申请日：2008-09-16
申请人： Ying-Chou Cheng , Chih-Ming Lai , Ru-Gun Liu , Tsong-Hua Ou , Min-Hong Wu , Yih-Yuh Doong , Hsiao-Shu Chao , Yi-Kan Cheng , Yao-Ching Ku , Cliff Hou
发明人： Ying-Chou Cheng , Chih-Ming Lai , Ru-Gun Liu , Tsong-Hua Ou , Min-Hong Wu , Yih-Yuh Doong , Hsiao-Shu Chao , Yi-Kan Cheng , Yao-Ching Ku , Cliff Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/12 , Y02P90/265 , Y10T16/2771
摘要： An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.
摘要翻译：集成电路（IC）设计方法包括基于IC器件的IC设计布局和IC制造数据提供IC布局轮廓; 生成有效的矩形布局来表示IC布局轮廓; 并使用有效的矩形布局模拟IC器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式